CN114116592A - Satellite-borne high-performance computing module system - Google Patents
Satellite-borne high-performance computing module system Download PDFInfo
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- CN114116592A CN114116592A CN202111342320.1A CN202111342320A CN114116592A CN 114116592 A CN114116592 A CN 114116592A CN 202111342320 A CN202111342320 A CN 202111342320A CN 114116592 A CN114116592 A CN 114116592A
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- 238000004148 unit process Methods 0.000 claims abstract description 3
- 230000015654 memory Effects 0.000 claims description 22
- 239000005441 aurora Substances 0.000 claims description 7
- 230000006870 function Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4406—Loading of operating system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
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Abstract
The invention provides a satellite-borne high-performance computing module system, which comprises a CPU (central processing unit), an FPGA (field programmable gate array) control unit, a storage unit and a communication unit, wherein: the CPU processing unit is connected with the FPGA control unit and is used for managing and controlling the FPGA control unit, the storage unit and the communication unit through a LocalBus bus and allocating resources; the FPGA control unit processes the data sent by the CPU processing unit and sends the processed data to external equipment; the storage unit stores a CPU processing unit program and an FPGA control unit program; the communication unit is used for realizing an internal RapidIO interface and a serial port. On the premise of meeting the requirement of high performance, the invention operates a 3+1 working mode, provides a scheme of taking two out of three aiming at application data, and solves the problem of reliability of a high-performance processor on a commercial satellite. The present invention provides a hardware architecture that achieves high performance processor reliability.
Description
Technical Field
The invention relates to the field of satellite-borne satellites, in particular to a satellite-borne high-performance computing module system.
Background
In order to meet the high reliability requirement of commercial satellites on satellite-borne embedded computers, a 3CPU + FPGA structural scheme is adopted, a 3+1 working mode is operated on the premise of meeting high performance, a two-out-of-three scheme is provided for application data, and an online reconfiguration technology of CPU software and FPGA software is supported.
The invention patent with patent document CN103853561B discloses an embedded satellite-borne software reconfiguration system and method, wherein the system comprises a loading table, an external interface unit, a private data definition unit and a private data operation implementation unit; the loading table comprises information data of a plurality of software modules; the external interface unit comprises a data operation interface, an interface for responding to a calling instruction of a user and providing a packaged interface function; the private data definition unit is used for defining the structure of data in the loading table; the private data operation implementation unit is used for operating the loading table through an encapsulated interface function according to a ground instruction and implementing dynamic satellite-ground loop reconstruction of software according to information provided in the loading table. But the scheme cannot meet the high reliability requirement of commercial satellites on the satellite-borne embedded computer.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a satellite-borne high-performance computing module system.
The invention provides a satellite-borne high-performance computing module system which comprises a CPU (central processing unit), an FPGA (field programmable gate array) control unit, a storage unit and a communication unit, wherein:
the CPU processing unit is connected with the FPGA control unit through a high-speed RapidIO interface, and controls and allocates resources to the FPGA control unit, the storage unit and the communication unit through a LocalBus bus;
the FPGA control unit processes the data sent by the CPU processing unit and sends the processed data to external equipment;
the storage unit stores a CPU processing unit program and an FPGA control unit program;
the communication unit is used for realizing an internal RapidIO interface and a serial port.
Preferably, the CPU processing unit comprises three P2020 processor chips, and each P2020 processor chip is respectively connected with one FIFO communication of the FPGA control unit.
Preferably, the CPU processing unit includes a DDR memory controller with a memory chip.
Preferably, the FPGA control unit includes a refresh chip and an SRAM type FPGA chip, wherein:
the refreshing chip is used for realizing the overloading, the readback and the refreshing of the FPGA software;
the SRAM type FPGA chip is used for switching between the CPU processing unit and the storage unit and controlling the sequential starting of the three CPU processing units.
Preferably, DDR3 memory is expanded outside the SRAM type FPGA chip to manage and use the memory unit.
Preferably, the SRAM type FPGA chip comprises a Kintex-7 chip and the refresh chip comprises a JFMSR01RH chip.
Preferably, the storage unit includes a memory of a CPU program and a memory of an FPGA program, wherein:
the memory of the CPU program comprises 2 FLASH chips which are all hung on an SRAM type FPGA chip, one FLASH is an aerospace level FLASH with the size of 8MB, the other FLASH is an industrial level FLASH with the size of 32MZ, a CPU boot, operating system and application program are stored in the aerospace level FLASH, and 4 same CPU boot and application programs are stored in the industrial level FLASH;
the memory of the FPGA program comprises a main memory and a standby memory which are hung on a refreshing chip, and the main-standby switching of the FLASH and the reconfiguration of the program are realized through the refreshing chip.
Preferably, the RapidIO interface is 2-way 1X, and the rate is 3.125 Gbps.
Preferably, the system also comprises an external GTX interface, wherein the external GTX interface is 1 path of 1X, realizes an Aurora protocol, adopts a Xilinx Aurora64B/66B protocol, and has the speed of 6.25 Gbps.
Preferably, the FPGA control unit performs two out of three operation on the data sent by the CPU processing unit, and sends the data to the external device through the Aurora interface.
Compared with the prior art, the invention has the following beneficial effects:
1. according to the invention, through the structural scheme of 3CPU + FPGA, on the premise of meeting high performance, a 3+1 working mode is operated, a scheme of taking three out of two is provided for application data, and the problem of reliability of a high-performance processor on a commercial satellite is solved.
2. The invention provides a hardware structure for realizing the reliability of a high-performance processor, and provides a hardware foundation for a software framework.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a schematic diagram of a satellite-borne high-performance computing module system according to the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
As shown in fig. 1, the system of the satellite-borne high-performance computing module provided by the invention comprises a hardware product and supporting software, wherein the hardware part comprises a high-performance processing unit, an FPGA control unit, a storage unit and a communication unit, and the software part comprises boot software, a board-level support package BSP and FPGA control software. The software part is the existing relatively mature scheme and is not described in detail here.
The high-performance processing unit of the invention adopts a 3-piece NXP high-performance and low-power processor P2020, the dominant frequency can reach 1GHz at most, the power consumption is 5W at most, the processor is manufactured by adopting a 45nm process, and 2 high-performance processor cores are integrated in a single chip. The 3 CPUs work simultaneously, are mainly responsible for data processing, algorithm operation, connection of a high-speed RapidIO interface and the FPGA, and conduct management and control and resource allocation on the FPGA control unit, the storage unit and the communication unit through a LocalBus bus. The memory chip is hung on a DDR memory controller of the P2020 processor, and a debugging interface of a network and a serial port is realized.
The FPGA control unit adopts a refreshing chip and an SRAM type FPGA chip (a Kintex-7 series of re-denier microelectronics), the refreshing chip mainly realizes the heavy load, the read back and the refreshing of FPGA software, the FPGA is mainly responsible for the switching between a CPU processing unit and a storage unit, the sequential starting control of 3CPU processors, the third to two of algorithm data, a DDR3 storage is externally expanded to manage and use the storage unit, and in addition, the FPGA control unit is responsible for the control and the realization of a GTX interface.
The storage unit mainly comprises storage of a CPU program and storage of an FPGA program. The CPU program memory includes 2 FLASH chips, one is an aerospace level device with a size of 8MB, one is an industrial level device with a size of 32MZ, wherein one CPU boot, operating system and application program are stored in the aerospace level FLASH, 4 same CPU boot and application programs are stored in the industrial level FLASH, the CPU is powered on to default to be started from the aerospace level FLASH, and if the starting is unsuccessful, three files are started after two out from the industrial level FLASH, so that the starting reliability of the CPU is improved. The two FLASH chips are hung on the FPGA, access is carried out through a LocalBus bus, and starting configuration of the CPU is achieved through the FPGA. The FPGA program has 2 memories which are mutually main and standby, and are hung on a refreshing chip, and the main and standby switching of the FLASH and the reconfiguration of the program are realized through the refreshing chip.
The communication interface unit mainly realizes an internal RapidIO interface and a 2-path serial port. The RapidIO interface is 2 paths of 1X, the speed is 3.125Gbps, the external GTX interface is 1 path of 1X, the Aurora protocol is realized, and the Xilinx Aurora64B/66B protocol is adopted, and the speed is 6.25 Gbps. The two serial ports are respectively used for the reconstruction of the CPU program and the reconstruction interface of the FPGA program.
The implementation scheme of the invention is as follows:
after the module is powered on, the FPGA program is read from the main FLASH to load the FPGA after the refresh chip is reset, after the FPGA is started, firstly, the CPU1 reads a bootstrap program of the CPU from the aerospace level FLASH through an interface realized by the FPGA, after the bootstrap program is started, the operating system is loaded, after the operating system is started, a start completion mark is sent to the FPGA, the CPU2 reads the CPU program from the aerospace level FLASH through the interface realized by the FPGA, after the start is completed, the start completion mark is sent to the FPGA, after the CPU3 reads the CPU program from the aerospace level FLASH through the interface realized by the FPGA, after the start is completed, the start completion mark is sent to the FPGA, after the FPGA receives the start completion marks of 3 CPUs, 3 CPUs start the application programs at the same time, and the synchronous operation of the application programs is ensured.
When 3 CPUs simultaneously run the same algorithm, the data are simultaneously sent to 3 fifo of the FPGA through RapidIO interfaces, and after the FPGA carries out three-out-of-two operation on the data of the 3 fifo, the data are sent to external equipment through Aurora interfaces. When receiving data, the FPGA firstly caches the data from the Aurora interface in the DDR3, and then simultaneously sends the data to 3 CPUs for processing.
The FPGA software is stored in 2 FLASH simultaneously, hung on an interface of a refreshing chip, the refreshing chip defaults to read data from the main FLASH to load the FPGA when being powered on and started, when the main FLASH data fails to start the FPGA successfully, the FPGA can be automatically switched to a standby FLASH, and FLASH programs can be updated through a refreshed serial port. The refresh function can also control the on-off and frequency of refresh through the serial port.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (10)
1. The utility model provides a satellite-borne high performance calculation module system which characterized in that, includes CPU processing unit, FPGA control unit, memory cell and communication unit, wherein:
the CPU processing unit is connected with the FPGA control unit through a high-speed RapidIO interface, and controls and allocates resources to the FPGA control unit, the storage unit and the communication unit through a LocalBus bus;
the FPGA control unit processes the data sent by the CPU processing unit and sends the processed data to external equipment;
the storage unit stores a CPU processing unit program and an FPGA control unit program;
the communication unit is used for realizing an internal RapidIO interface and a serial port.
2. The system according to claim 1, wherein the CPU comprises three P2020 processor chips, and each P2020 processor chip is communicatively connected to one FIFO of the FPGA control unit.
3. The on-board high-performance computing module system of claim 2, wherein the CPU processing unit comprises a DDR memory controller with a memory chip on board.
4. The system of claim 1, wherein the FPGA control unit comprises a refresh chip and an SRAM type FPGA chip, wherein:
the refreshing chip is used for realizing the overloading, the readback and the refreshing of the FPGA software;
the SRAM type FPGA chip is used for switching between the CPU processing unit and the storage unit and controlling the sequential starting of the three CPU processing units.
5. The system according to claim 4, characterized in that the DDR3 memory is externally extended to SRAM type FPGA chip for managing and using the memory unit.
6. The on-board high performance computing module system of claim 4, wherein the SRAM-type FPGA chip comprises a Kintex-7 chip and the refresh chip comprises a JFMSR01RH chip.
7. The on-board high performance computing module system of claim 4, wherein the storage unit comprises a memory for a CPU program and a memory for an FPGA program, wherein:
the memory of the CPU program comprises 2 FLASH chips which are all hung on an SRAM type FPGA chip, one FLASH is an aerospace level FLASH with the size of 8MB, the other FLASH is an industrial level FLASH with the size of 32MZ, a CPU boot, operating system and application program are stored in the aerospace level FLASH, and 4 same CPU boot and application programs are stored in the industrial level FLASH;
the memory of the FPGA program comprises a main memory and a standby memory which are hung on a refreshing chip, and the main-standby switching of the FLASH and the reconfiguration of the program are realized through the refreshing chip.
8. The on-board high performance computing module system of claim 1, wherein the RapidIO interface is 2-way 1X with a rate of 3.125 Gbps.
9. The spaceborne high-performance computing module system according to claim 1, further comprising an external GTX interface, wherein the external GTX interface is 1-way 1X, realizes an Aurora protocol, adopts a Xilinx Aurora64B/66B protocol, and has a rate of 6.25 Gbps.
10. The spaceborne high-performance computing module system according to claim 1, wherein the FPGA control unit sends the data to the external device through an Aurora interface after performing two-out-of-three operation on the data sent by the CPU processing unit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111342320.1A CN114116592A (en) | 2021-11-12 | 2021-11-12 | Satellite-borne high-performance computing module system |
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| CN202111342320.1A CN114116592A (en) | 2021-11-12 | 2021-11-12 | Satellite-borne high-performance computing module system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116737649A (en) * | 2023-06-15 | 2023-09-12 | 上海国宇智链航天科技有限公司 | Multi-layer redundancy reconfigurable computing system of commercial spacecraft and implementation method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116737649A (en) * | 2023-06-15 | 2023-09-12 | 上海国宇智链航天科技有限公司 | Multi-layer redundancy reconfigurable computing system of commercial spacecraft and implementation method |
| CN116737649B (en) * | 2023-06-15 | 2024-06-07 | 上海国宇智链航天科技有限公司 | Multi-layer redundancy reconfigurable computing system of commercial spacecraft and implementation method |
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