CN114115720B - High-frame-rate low-delay graph generating device based on FPGA - Google Patents
High-frame-rate low-delay graph generating device based on FPGA Download PDFInfo
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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Abstract
The invention provides a high-frame-rate low-delay graph generating device based on an FPGA, which comprises a graph drawing processor, the FPGA, a character memory, a graph video memory and an external video memory; the FPGA comprises a drawing command buffer unit, a graph drawing unit, a video memory read-write control unit, an ECC check unit, an external video control unit, a display superposition unit and a display output adjustment unit. The invention is suitable for generating graphics in aviation military and civil aircraft display systems, can effectively solve the design bottleneck caused by the current application of commercial COTS display chips, has the remarkable advantages of high frame rate, low delay, high integration level and low power consumption, and can powerfully support the design and development work of the display systems.
Description
Technical Field
The invention relates to a high-frame-rate low-delay graph generating device based on an FPGA, and belongs to the field of avionic design.
Background
The airborne display system is an important component of an aircraft avionics system and is a window for a pilot to acquire flight attitude parameters and control the pilot to fly. Devices such as head-up displays, downview displays and the like serve as important man-machine interface devices to convert flight parameter information into display information so as to provide visual flight guidance for pilots.
At present, commercial COTS display chips are adopted in an airborne display system to complete graph generation, but the following problems exist:
1. the delay is large, the real-time requirement of the airborne display equipment is high, the delay of the commercial display chip is large, and the delay index of the system is a constraint;
2. the frame rate is low, the frame rate of the complex display picture is low, and the timely display of flight parameter information is affected;
3. the civil aircraft displays that the application of the product is suitable for the navigation support data is few, restrict the commercial COTS device to be applied in the product.
4. The common commercial COTS display chip also requires additional design circuitry to complete the external video overlay.
Disclosure of Invention
Aiming at the problems existing in the prior art, the invention provides the high-frame-rate low-delay graph generating device based on the FPGA, which uses an FPGA device to complete the functions of drawing instruction receiving, graph generating, external video superposition and display adjustment output, has the characteristics of high frame rate, low delay and low power consumption, is beneficial to the system heat dissipation design, integrates the video superposition function and the graph generating function, has high integration degree, and further reduces superposition processing delay.
The technical scheme of the invention is as follows:
the high-frame-rate low-delay graph generating device based on the FPGA comprises a graph drawing processor, the FPGA, a character memory, a graph video memory and an external video memory;
the FPGA comprises the following components: the device comprises a drawing command buffer unit, a graph drawing unit, a video memory read-write control unit, an ECC check unit, an external video control unit, a display superposition unit and a display output adjustment unit;
the drawing command buffer unit buffers drawing commands sent to the FPGA by the graphic drawing processor and outputs the drawing commands to the graphic drawing unit, wherein the drawing commands comprise setting commands and graphic commands;
under the condition that a vertical synchronous instruction is started, the drawing command buffer unit adopts a three-level buffer arbitration mechanism to solve the problem of asynchronous transfer of drawing instructions, and ensures that the drawing instructions read by the graphic drawing unit are a frame of complete data instructions; under the condition that the vertical synchronous instruction is closed, the second-level buffer area of the three-level buffer arbitration mechanism is switched from double buffer to single buffer so as to ensure low-delay transmission of the drawing instruction; the read-write clocks at two ends of a second-stage buffer area of the three-stage buffer arbitration mechanism are configured to have the same rate;
the graphic drawing unit analyzes the graphic command and draws the graphic elements by adopting a multichannel parallel drawing mechanism according to different graphic elements; after the drawing of the graphic primitive is completed, storing the graphic primitive in a direct result buffer area, an interpolation result buffer area, a filling result buffer area and a first interpolation result buffer area according to different characteristics of drawing results; the direct result buffer area is used for storing data of pixel points which are to be directly output and are irrelevant to background colors, the interpolation result buffer area is used for storing data of pixel points which need interpolation correction, the filling result buffer area is used for storing data of filling triangles, filling rectangles and filling circles, and the first interpolation result buffer area is used for storing data of single-side anti-aliasing of the outer edge of the graph when the filling triangles, the filling rectangles and the filling circles are anti-aliasing;
the video memory read-write control unit writes the drawn result of the graphic primitive into the graphic video memory, and reads the data in the graphic video memory along with the graphic data read-out time sequence of the display superposition unit; the video memory read-write control unit performs interrupt judgment and judgment on data writing and reading operations of the direct result buffer area, the interpolation result buffer area, the filling result buffer area and the first interpolation result buffer area, wherein the priority is graphic reading out, direct result buffer area writing, interpolation result buffer area writing, filling result buffer area writing and first interpolation result buffer area writing; the image data reading time sequence is determined according to the video time sequence which is finally required to be output;
the ECC check unit performs ECC check on the data written into the graphic video memory and the drawing data read out of the video memory by taking the data frame as a unit;
when the external video superposition function is started, the external video control unit caches the input external video data in the external video memory, and the display superposition unit reads out the external video pixel data and the graphic data from the external video control unit according to the timing sequence of the graphic data reading out, performs pixel level superposition on the external video pixel data and the graphic data, and sends the external video pixel data and the graphic data to the display output adjustment unit; under the condition that the external video superposition function is closed, the display superposition unit directly sends the graphic data read from the graphic display memory to the display output adjustment unit;
and the display output adjusting unit adjusts the input data according to the set output video protocol and outputs the adjusted data.
Further, the setting command includes graphic resolution, windowing, occlusion region, background color, vertical synchronization function on-off, and external video overlay function on-off parameter setting.
Further, the graphic command comprises a graphic primitive type drawing instruction and a graphic primitive drawing parameter; the primitive types comprise points, lines, circles, triangles, arcs and characters; the primitive drawing parameters comprise color and line width.
Further, the drawing command buffer unit comprises a three-stage buffer unit, wherein the first-stage buffer unit is an instruction receiving and storing unit, the second-stage buffer unit is provided with two instruction buffer areas, and the third-stage buffer unit is an instruction sending and storing unit;
after the command receiving and storing unit receives a frame of drawing command, under the condition that a vertical synchronous command is opened, the drawing command is sequentially and alternately written into two command buffer areas of the second-stage buffer unit by taking a frame as a unit; under the condition that the vertical synchronous instruction is closed, writing the drawing instruction into a certain designated instruction cache area in the second-stage buffer unit by taking a frame as a unit;
for the first frame drawing instruction after power-on, the first frame drawing instruction is directly read from the second-stage buffer unit to the instruction sending storage unit; for the subsequent drawing instruction, after receiving the drawing completion signal sent by the drawing unit, the drawing instruction is read from the second-stage buffer unit to the instruction sending storage unit, and the reading rule is as follows:
in the vertical synchronization instruction on case:
when the data in the first instruction cache region is to be read, judging a flag1 signal, if the flag1 signal is valid, reading the data in the first instruction cache region, otherwise, continuing to read the data in the second instruction cache region; the flag1 signal indicates whether the first instruction buffer area is written with data again after the first instruction buffer area is read last time, wherein if the first instruction buffer area is written with data again, the flag1 signal is valid, otherwise the flag1 signal is invalid;
judging a flag2 signal when the data in the second instruction cache region is to be read, if the flag2 signal is valid, reading the data in the second instruction cache region, otherwise, continuing to read the data in the first instruction cache region; the flag2 signal indicates whether the second instruction buffer is written with data again after the data of the second instruction buffer is read last time, wherein if the data is written with the second instruction buffer again, the flag2 signal is valid, otherwise the flag2 signal is invalid;
in the case of vertical synchronization instruction off:
and directly reading the drawing instruction from the certain designated instruction cache area to the instruction sending storage unit.
Further, the drawing channels comprise a point drawing channel, a horizontal straight line drawing channel, an oblique line drawing channel, a round drawing channel, an arc drawing channel, a triangle filling drawing channel, a rectangular filling drawing channel, a round filling drawing channel and a character drawing channel.
Further, besides character drawing, the other primitive drawing is real-time drawing by the FPGA algorithm, and the character drawing is to read the character to be drawn from the character memory.
Furthermore, a ping-pong buffer mechanism is adopted in the graphic video memory to solve the problem of asynchronous complete frame data reading and writing.
Further, the formula of the display superimposing unit for pixel level superimposition is as follows:
R(x,y)＝(255-gray(x,y))*bg_R(x,y)/255；
G(x,y)＝(255-gray(x,y))*bg_G(x,y)/255；
B(x,y)＝(255-gray(x,y))*bg_B(x,y)/255；
where gray represents a graphic data gray value, bg_r, bg_g, bg_b represents an external video gray value.
Further, the output timing adjusted by the display output adjusting unit includes VESA timing, LVDS, digital RGB, ARINC818 timing.
Further, after the frame check instruction is started in the setting instruction, the display output adjustment unit completes CRC check of the whole frame output picture, replaces the last row and the last column of the output pixel point with a CRC check value, and transmits the CRC check value to a subordinate device so as to ensure data safety of a transmission chain.
Advantageous effects
The invention provides a high-frame-rate low-delay graph generating device based on an FPGA, which is suitable for graph generation in aviation military and civil aircraft display systems. The implementation of the method can effectively solve the design bottleneck caused by the current application of commercial COTS display chips, has the remarkable advantages of high frame rate, low delay, high integration level and low power consumption, and powerfully supports the design and development work of the display system.
Compared with the existing graph generating device in the aviation display system, the method has the following advantages:
1. high frame rate, drawing pictures in parallel by adopting multiple channels;
2. low delay, pipelined data transfer and storage mechanisms;
3. the integration level is high, and the video superposition function and the graph generation function are seamlessly coupled;
4. the power consumption of the FPGA device is low.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
fig. 1: a hardware schematic block diagram of the device implementation;
fig. 2: the drawing command buffer unit forms a schematic diagram;
fig. 3: the graphic drawing unit constitutes a schematic diagram:
fig. 4: the video memory read-write control unit forms a schematic diagram.
Detailed Description
The following detailed description of embodiments of the invention is exemplary and intended to be illustrative of the invention and not to be construed as limiting the invention.
The embodiment provides a high-frame-rate low-delay graph generating device based on an FPGA, which is applied to an aviation display system and generates equipment pictures by using a Yu Pingxian display, a multifunctional display and the like.
As shown in fig. 1, the high frame rate low delay graphics generating device based on the FPGA comprises a graphics drawing processor, an FPGA, a character memory, a graphics video memory and an external video memory.
The FPGA comprises the following components: the device comprises a drawing command buffer unit, a graph drawing unit, a video memory read-write control unit, an ECC check unit, an external video control unit, a display superposition unit and a display output adjustment unit.
The drawing command buffer unit buffers drawing commands sent to the FPGA by the graphic drawing processor through an external bus and outputs the drawing commands to the graphic drawing unit, wherein the drawing commands comprise setting commands and graphic commands. The setting command comprises parameter settings such as graphic resolution, windowing, blocking area, background color, vertical synchronization function opening and closing, external video superposition function opening and closing, frame verification opening and closing and the like; the graphic command includes graphic primitive type drawing instructions such as points, lines, circles, triangles, arcs, characters and the like, and graphic primitive drawing parameters such as colors, line widths and the like.
The external bus for the graphics rendering processor to send the drawing instructions includes PCI, PCIE, high-speed LINK ports, etc.
Under the condition that a vertical synchronous instruction is started, the drawing command buffer unit adopts a three-level buffer arbitration mechanism to solve the problem of asynchronous transfer of drawing instructions, and ensures that the drawing instructions read by the graphic drawing unit are a frame of complete data instructions; under the condition that the vertical synchronous instruction is closed, the second-level buffer area of the three-level buffer arbitration mechanism is switched from double buffer to single buffer so as to ensure low-delay transmission of the drawing instruction; the read-write clocks at two ends of the second-stage buffer area of the three-stage buffer arbitration mechanism are configured to have the same rate.
As shown in fig. 2, the drawing command buffer unit includes three levels of buffer units, the first level of buffer unit is an instruction receiving and storing unit, the second level of buffer unit has two instruction buffers, and the third level of buffer unit is an instruction sending and storing unit.
After the command receiving and storing unit receives a frame of drawing command, under the condition that a vertical synchronous command is opened, the drawing command is sequentially and alternately written into two command buffer areas of the second-stage buffer unit by taking a frame as a unit; when the vertical synchronous command is closed, the drawing command is written into a designated command buffer area in the second stage buffer unit in a frame unit.
For the first frame drawing instruction after power-on, the first frame drawing instruction is directly read from the second-stage buffer unit to the instruction sending storage unit; for the subsequent drawing instruction, after receiving the drawing completion signal sent by the drawing unit, the drawing instruction is read from the second-stage buffer unit to the instruction sending storage unit, and the reading rule is as follows:
in the vertical synchronization instruction on case:
when the data in the first instruction cache region is to be read, judging a flag1 signal, if the flag1 signal is valid, reading the data in the first instruction cache region, otherwise, continuing to read the data in the second instruction cache region; the flag1 signal indicates whether the first instruction buffer area is written with data again after the first instruction buffer area is read last time, wherein if the first instruction buffer area is written with data again, the flag1 signal is valid, otherwise the flag1 signal is invalid;
judging a flag2 signal when the data in the second instruction cache region is to be read, if the flag2 signal is valid, reading the data in the second instruction cache region, otherwise, continuing to read the data in the first instruction cache region; the flag2 signal indicates whether the second instruction buffer is written with data again after the data of the second instruction buffer is read last time, wherein if the data is written with the second instruction buffer again, the flag2 signal is valid, otherwise the flag2 signal is invalid;
in the case of vertical synchronization instruction off:
and directly reading the drawing instruction from the certain designated instruction cache area to the instruction sending storage unit.
Under the condition that the vertical synchronous instruction is opened, the integrity of the data frame transferred by the drawing instruction under the transmission bus clock domain and the graph drawing clock domain can be ensured; under the condition that the vertical synchronous instruction is closed, the second-stage buffer unit only uses one instruction buffer area to transmit the drawing instruction, so that low delay of data transmission is ensured.
The graphic drawing unit analyzes the graphic command and draws the graphic elements by adopting a multichannel parallel drawing mechanism according to different graphic elements; the drawing channels comprise a point drawing channel, a horizontal straight line drawing channel, an oblique line drawing channel, a circular drawing channel, an arc drawing channel, a triangle filling drawing channel, a rectangular filling drawing channel, a circular filling drawing channel and a character drawing channel; besides character drawing, the other primitive drawing is real-time drawing by an FPGA algorithm, and the character drawing is to read characters to be drawn from a character memory. After the drawing of the graphic primitive is completed, the graphic primitive is stored in a direct result buffer area, an interpolation result buffer area, a filling result buffer area and a first interpolation result buffer area according to different characteristics of drawing results.
As shown in fig. 3, after receiving the drawing instruction, the graphics drawing unit distinguishes drawing of different primitives according to different command words in the instruction, and increases the drawing speed by adopting a multi-channel parallel drawing mode. After drawing is completed, the drawing result is stored in a buffer area: the direct result buffer area is used for storing the data of the pixel points which are to be directly output and are irrelevant to the background color; the interpolation result buffer area is used for storing the data of pixel points needing interpolation correction, and is mostly used for drawing anti-aliasing graphs such as oblique lines, circles, arcs and the like and anti-aliasing characters; the filling result buffer area is used for storing data of filling triangles, filling rectangles and filling circles, and the filling result buffer area is added mainly when the triangle and the circle are filled and anti-aliasing is carried out, the triangle and the solid circle data which are not anti-aliasing need to be covered on the data of the edge anti-aliasing, namely, the writing data of the filling result buffer area is executed after the writing data of the interpolation result buffer area; the first interpolation result buffer area is used for storing data of unilateral anti-aliasing of the outer edge of the graph when filling triangles, filling rectangles and filling circles are anti-aliasing.
The video memory read-write control unit writes the drawn result of the graphic primitive into the graphic video memory, and reads the data in the graphic video memory along with the graphic data read-out time sequence of the display superposition unit; the video memory read-write control unit performs interrupt judgment and judgment on data writing and reading operations of the direct result buffer area, the interpolation result buffer area, the filling result buffer area and the first interpolation result buffer area, an arbitration mechanism of image video memory writing and reading is shown in fig. 4, and the priority is that the image reading is that the direct result buffer area writing is conducted, the interpolation result buffer area writing is conducted, and the filling result buffer area writing is conducted; and the graphic data read-out timing is determined according to the video timing that is finally required to be output.
The problem of asynchronous complete frame data reading and writing is solved by adopting a ping-pong buffer mechanism in the graphic video memory.
And the ECC checking unit performs ECC checking on the data written into the graphic video memory and the drawing data read out of the video memory by taking the data frame as a unit, so that the correctness of the drawing data is ensured. And (3) performing ECC coding when the graphic element drawing result is written into the graphic display memory, performing ECC decoding when the graphic display memory is read out, and reporting errors to a graphic drawing processor once errors occur in monitoring decoding.
When the external video superposition function is started, the external video control unit caches the input external video data in the external video memory, and the display superposition unit reads out the external video pixel data and the graphic data from the external video control unit according to the timing sequence of the graphic data reading out, performs pixel level superposition on the external video pixel data and the graphic data, and sends the external video pixel data and the graphic data to the display output adjustment unit; when the external video superimposing function is turned off, the display superimposing unit directly sends the graphics data read from the graphics memory to the display output adjusting unit.
The formula of the display superimposing unit for pixel level superimposition is as follows:
R(x,y)＝(255-gray(x,y))*bg_R(x,y)/255；
G(x,y)＝(255-gray(x,y))*bg_G(x,y)/255；
B(x,y)＝(255-gray(x,y))*bg_B(x,y)/255；
where gray represents a graphic data gray value, bg_r, bg_g, bg_b represents an external video gray value.
The display output adjusting unit adjusts the input data according to the set output video VESA protocol and outputs the adjusted data.
The output timing adjusted by the display output adjusting unit may be LVDS, digital RGB, ARINC818 timing in addition to VESA timing.
After a frame check instruction is started in the setting instruction, the display output adjusting unit completes CRC check of the whole frame output picture, the RGB 24 bit gray scale value of the last point of the whole frame picture is replaced by a CRC check result, and then output is carried out, so that the data safety of a transmission chain is ensured.
In the following, for example, the whole frame CRC check calculation method, if the video resolution is 1280×1024, calculates the CRC value of (1280×1024-1) pixels, and replaces the pixel value of the last point with the calculated result of (1280×1024-1) pixels, as shown in the following table.
Although embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives, and variations may be made in the above embodiments by those skilled in the art without departing from the spirit and principles of the invention.
Claims (9)
1. The utility model provides a high frame rate low delay figure generation device based on FPGA which characterized in that: the system comprises a graph drawing processor, an FPGA, a character memory, a graph video memory and an external video memory;
the FPGA comprises the following components: the device comprises a drawing command buffer unit, a graph drawing unit, a video memory read-write control unit, an ECC check unit, an external video control unit, a display superposition unit and a display output adjustment unit;
the drawing command buffer unit buffers drawing commands sent to the FPGA by the graphic drawing processor and outputs the drawing commands to the graphic drawing unit, wherein the drawing commands comprise setting commands and graphic commands;
under the condition that a vertical synchronous instruction is started, the drawing command buffer unit adopts a three-level buffer arbitration mechanism to solve the problem of asynchronous transfer of drawing instructions, and ensures that the drawing instructions read by the graphic drawing unit are one-frame complete data instructions; under the condition that the vertical synchronous instruction is closed, the second-level buffer area of the three-level buffer arbitration mechanism is switched from double buffer to single buffer so as to ensure low-delay transmission of the drawing instruction; the read-write clocks at two ends of a second-stage buffer area of the three-stage buffer arbitration mechanism are configured to have the same rate;
the graphic drawing unit analyzes the graphic command and draws the graphic elements by adopting a multichannel parallel drawing mechanism according to different graphic elements; after the drawing of the graphic primitive is completed, storing the graphic primitive in a direct result buffer area, an interpolation result buffer area, a filling result buffer area and a first interpolation result buffer area according to different characteristics of drawing results; the direct result buffer area is used for storing data of pixel points which are to be directly output and are irrelevant to background colors, the interpolation result buffer area is used for storing data of pixel points which need interpolation correction, the filling result buffer area is used for storing data of filling triangles, filling rectangles and filling circles, and the first interpolation result buffer area is used for storing data of single-side anti-aliasing of the outer edge of the graph when the filling triangles, the filling rectangles and the filling circles are anti-aliasing;
the video memory read-write control unit writes the drawn result of the graphic primitive into the graphic video memory, and reads the data in the graphic video memory along with the graphic data read-out time sequence of the display superposition unit; the video memory read-write control unit performs interrupt judgment and judgment on data writing and reading operations of the direct result buffer area, the interpolation result buffer area, the filling result buffer area and the first interpolation result buffer area, wherein the priority is graphic reading out, direct result buffer area writing, interpolation result buffer area writing, filling result buffer area writing and first interpolation result buffer area writing; the image data reading time sequence is determined according to the video time sequence which is finally required to be output;
the ECC check unit performs ECC check on the data written into the graphic video memory and the drawing data read out of the video memory by taking the data frame as a unit;
when the external video superposition function is started, the external video control unit caches the input external video data in the external video memory, and the display superposition unit reads out the external video pixel data and the graphic data from the external video control unit according to the timing sequence of the graphic data reading out, performs pixel level superposition on the external video pixel data and the graphic data, and sends the external video pixel data and the graphic data to the display output adjustment unit; under the condition that the external video superposition function is closed, the display superposition unit directly sends the graphic data read from the graphic display memory to the display output adjustment unit;
and the display output adjusting unit adjusts the input data according to the set output video protocol and outputs the adjusted data.
2. The FPGA-based high frame rate low latency graphics generating device according to claim 1, wherein: the setting command comprises graphic resolution, windowing, blocking area, background color, vertical synchronization function on/off and external video superposition function on/off parameter setting.
3. The FPGA-based high frame rate low latency graphics generating device according to claim 1, wherein: the graphic command comprises a graphic primitive type drawing instruction and graphic primitive drawing parameters; the primitive types comprise points, lines, circles, triangles, arcs and characters; the primitive drawing parameters comprise color and line width.
4. The FPGA-based high frame rate low latency graphics generating device according to claim 1, wherein: the drawing channels comprise a point drawing channel, a horizontal straight line drawing channel, an oblique line drawing channel, a circular drawing channel, an arc drawing channel, a triangle filling drawing channel, a rectangular filling drawing channel, a circular filling drawing channel and a character drawing channel.
5. The FPGA-based high frame rate low latency graphics generating device according to claim 4, wherein: besides character drawing, the other primitive drawing is real-time drawing by an FPGA algorithm, and the character drawing is to read characters to be drawn from a character memory.
6. The FPGA-based high frame rate low latency graphics generating device according to claim 1, wherein: the problem of asynchronous complete frame data reading and writing is solved by adopting a ping-pong buffer mechanism in the graphic video memory.
7. The FPGA-based high frame rate low latency graphics generating device according to claim 1, wherein: the formula of the display superimposing unit for pixel level superimposition is as follows:
R(x,y)＝(255-gray(x,y))*bg_R(x,y)/255；
G(x,y)＝(255-gray(x,y))*bg_G(x,y)/255；
B(x,y)＝(255-gray(x,y))*bg_B(x,y)/255；
where gray represents a graphic data gray value, bg_r, bg_g, bg_b represents an external video gray value.
8. The FPGA-based high frame rate low latency graphics generating device according to claim 1, wherein: the output timing adjusted by the display output adjusting unit includes VESA timing, LVDS, digital RGB, ARINC818 timing.
9. The FPGA-based high frame rate low latency graphics generating device according to claim 1, wherein: after a frame check instruction is started in the setting instruction, the display output adjustment unit completes CRC check of the whole frame output picture, the last row and the last column of values of the output pixel points are replaced by CRC check values, and the CRC check values are transmitted to a subordinate device so as to ensure data safety of a transmission chain.
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