CN114114891A - double-Beidou satellite synchronous clock system and method - Google Patents
double-Beidou satellite synchronous clock system and method Download PDFInfo
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- CN114114891A CN114114891A CN202111440236.3A CN202111440236A CN114114891A CN 114114891 A CN114114891 A CN 114114891A CN 202111440236 A CN202111440236 A CN 202111440236A CN 114114891 A CN114114891 A CN 114114891A
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- G—PHYSICS
- G04—HOROLOGY
- G04R—RADIO-CONTROLLED TIME-PIECES
- G04R20/00—Setting the time according to the time information carried or implied by the radio signal
- G04R20/02—Setting the time according to the time information carried or implied by the radio signal the radio signal being sent by a satellite, e.g. GPS
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention discloses a Beidou satellite synchronous clock system and a Beidou satellite synchronous clock method, which comprise a Beidou antenna, a power divider and Beidou synchronous clock equipment, wherein the Beidou antenna is connected with the power divider, the power divider is connected with the Beidou synchronous clock equipment, the Beidou antenna is used for receiving satellite signals, the power divider divides the received satellite signals into two paths of Beidou signals, the two paths of Beidou signals are used as reference source signals and are transmitted into the Beidou synchronous clock equipment together with IRIGB power clock signals, and the Beidou synchronous clock equipment is used for correcting and compensating deviations of the input IRIGB power clock signals and outputting the deviations after reducing deviation values. The invention solves the technical current situation that the domestic existing power grid time synchronization system excessively depends on a GPS system, and improves the safety and reliability of the power grid time synchronization system.
Description
Technical Field
The invention relates to a time synchronization technology of a power system, in particular to a double Beidou satellite synchronous clock system and a method.
Background
In recent years, with the high-speed development and construction of power systems in China, a large number of transformer substation intelligent devices are applied, and national power grid interconnection and intercommunication are also rapidly promoted, so that the requirements of the power systems on time synchronization precision are more and more strict. The time synchronization network is used as a core component of the functions of the power system, provides guarantee for the safe and stable operation of the power system, and is used for providing a uniform and accurate time reference standard for all intelligent equipment and a central control center in the power system.
The satellite navigation technology research of China starts late, and the research of related terminal equipment is immature, so that the satellite time service of the domestic electric power system mainly depends on a GPS system at present, which not only has serious potential safety hazard, but also because of the limitation of the current GPS technology, each time service terminal is in a passive one-way GPS time signal receiving mode, and the time synchronization unification among the systems is not easy to realize.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a double Beidou satellite synchronous clock system and a method. The system adopts the autonomous Beidou satellite navigation system in China, gets rid of the transitional dependence on a GPS satellite system, and improves the safety and reliability of a power grid.
In order to solve the problems in the prior art, the invention adopts the technical scheme that:
the double-Beidou satellite synchronous clock system comprises a Beidou antenna, a power divider and double-Beidou synchronous clock equipment, wherein the Beidou antenna is connected with the power divider, the power divider is connected with the double-Beidou synchronous clock equipment, the Beidou antenna is used for receiving satellite signals, the power divider divides the received satellite signals into two Beidou signals, the two Beidou signals are used as reference source signals and are transmitted into the double-Beidou synchronous clock equipment simultaneously with IRIGB electric power clock signals, and the double-Beidou synchronous clock equipment is used for correcting and compensating deviation of input IRIGB electric power clock signals and outputting the deviation value.
Furthermore, the double-Beidou synchronous clock device comprises a mainboard, a clock synchronization module, a superheterodyne receiver, a power supply module, a monitoring module and a human-computer interface, wherein the clock synchronization module, the power supply and the monitoring module are all connected with the mainboard, an output interface and an input interface are arranged on the mainboard, the superheterodyne receiver is connected with the clock synchronization module, and the keyboard interface is connected with the clock synchronization module.
Furthermore, the clock synchronization module includes a signal processing unit and an arithmetic unit, the signal processing unit is configured to monitor and measure a phase of the reference source signal, and then transmit data to the arithmetic unit, and the arithmetic unit is configured to compare the reference source signal preferentially, and correct the IRIGB signal.
Further, the signal processing unit includes a reference source signal monitoring module and a phase measurement module, the reference source signal monitoring module is configured to monitor a reference source signal, and the phase measurement module (configured to perform phase measurement on an input reference source signal and transmit measurement data to the operation unit in real time.
Furthermore, the operation unit comprises a reference source comparison module, a reference source optimization module, a reference source switching module and a deviation correction module, wherein the reference source comparison module is used for comparing reference source signals after phase measurement; the reference source optimization module is used for optimizing the compared reference source signal according to the IRGB signal; the reference source switching module is used for switching and selecting the reference source signal according to the optimal result, and the deviation rectifying module is used for synchronously optimizing the IRIGB signal according to the switched reference source signal.
Further, the superheterodyne receiver includes an oscillator and a voltage-controlled circuit, the oscillator is connected to the signal processing unit, and the voltage-controlled circuit is connected to the arithmetic unit.
The double Beidou satellite synchronous clock method comprises the following steps:
s1: monitoring an input reference source signal;
s2: carrying out phase measurement on an input reference source signal, and transmitting measurement data to an arithmetic unit in real time;
s3: comparing the reference source signals after phase measurement,
s4: optimizing the compared reference source signal according to the IRGB signal;
s5: the reference source signal is selected according to the preference result,
s6: and carrying out synchronous optimization on the IRIGB signal according to the switched reference source signal.
Compared with the prior art, the invention has the advantages and beneficial effects that:
the double-Beidou system is adopted, is an autonomous Beidou satellite navigation system in China, gets rid of transitional dependence on a GPS satellite system, and improves the safety and reliability of a power grid. Meanwhile, the Beidou system is a geosynchronous satellite, and the transmitted signals can be stably received by most regions in China, so that the timing precision of the Beidou system synchronous clock product is obviously improved.
Drawings
The invention is described in further detail below with reference to the accompanying drawings:
FIG. 1 is a schematic view of the overall structure of the present invention;
FIG. 2 is a functional block diagram of a synchronous clock device;
FIG. 3 is a functional block diagram of a clock synchronization module;
fig. 4 is a flow chart of a double beidou satellite synchronous clock method.
Detailed Description
The present invention is further described in detail with reference to the following specific examples, but the scope of the present invention is not limited by the specific examples, which are defined by the claims. In addition, any modification or change that can be easily made by a person having ordinary skill in the art without departing from the technical solution of the present invention will fall within the scope of the claims of the present invention.
As shown in fig. 1, the double-Beidou satellite synchronous clock system comprises a Beidou antenna, a power divider and double-Beidou synchronous clock equipment, wherein the Beidou antenna is connected with the power divider, the power divider is connected with the double-Beidou synchronous clock equipment, the Beidou antenna is used for receiving satellite signals, the power divider divides the received satellite signals into two Beidou signals which are mutually standby, the two obtained Beidou signals are used as reference source signals, and IRIGB power clock signals and the reference source signals are transmitted into the double-Beidou synchronous clock equipment at the same time. The double-Beidou synchronous clock equipment is used for correcting and compensating the deviation of the input IRIGB power clock signal, outputting the output signal after the deviation value is reduced, and simultaneously outputting a time tick message and a pulse null node.
As shown in fig. 2, the big dipper synchronous clock device includes a motherboard, a clock synchronization module, a superheterodyne receiver, a power module, a monitoring module, and a human-computer interface, where the human-computer interface includes a keyboard interface, a VFD display interface, an indicator light interface, an output interface, and an input interface, the clock synchronization module, the power module, and the monitoring module are respectively connected to the motherboard, the motherboard is provided with the output interface and the input interface, the superheterodyne receiver is connected to the clock synchronization module, and the keyboard interface is connected to the clock synchronization module.
The clock synchronization module is used for switching and selecting the reference source signal, performing closed-loop control on the superheterodyne receiver and outputting a power clock signal.
The monitoring module is used for equipment alarm, has perfect monitoring management function, can collect the working state of each functional module in real time, can give alarm information by the alarm terminal once each functional module breaks down, can position and alarm to each functional module and display on the VFD panel, and can store historical alarm information. The set instruction command can be issued to the system through the keyboard.
The power module can adopt a high-performance AC/DC input power module, the power supply is compatible with 220VAC/DC input, and the power module converts the power into a direct-current power supply to be used by each internal module, is provided with a switch, a safety and the like, and is convenient for a user to maintain.
The input interface is used for receiving Beidou satellite signals, local rubidium clock 10MHz signals or upstream transmitted DCLS signals and input IRIGB/1PPS signals.
The output interface is used for outputting IRIGB signals, pulse empty nodes, time synchronization messages and NTP. The output of IRIGB signal is completed by IRIGB code generator, which receives internal clock bus signal to obtain system time reference and time information, and generates DC IRIGB signal via drive and interface protection circuit by B code generating unit. The IRIGB code decoder can output signals of TTL/RS 232/RS 422 interface through jumper wires. The IRIGB code generator outputs a 1PPS/1PPM/1PPH signal based on the 1PPS signal. The IRIGB code generator can simultaneously output 8 paths of pulse signals, wherein the 1 st path and the 2 nd path are used as TTL/empty contact pulse output and can be configured into TTL/empty contact level output through a jumper wire, the type of the output signal can be configured into 1PPS/1PPM/1PPH, the other 6 paths can be configured into 1PPS/1PPM/1PPH through the jumper wire, and the output level is in an empty contact mode. The time tick message is time ticked to the terminal user by a serial port message mode, and the first rising edge of the serial port pulse of the time tick message is aligned with the 1PPS signal generated by the timing card.
The man-machine interface can be connected with four indicator lamps, a VFD display screen with high brightness, wide temperature and wide visual angle and a functional keyboard.
As shown in fig. 3, the clock synchronization module includes a signal processing unit and an arithmetic unit, the signal processing unit is configured to monitor and measure a phase of a reference source signal, and then transmit measurement data to the arithmetic unit in real time, the arithmetic unit completes reference source signal performance comparison and reference source optimization according to the measurement data, completes switching of each reference source, and completes correction and rectification of an IRIGB signal, and completes control of a local oscillator through a voltage control circuit, thereby forming a timing closed loop.
The signal processing unit comprises a reference source signal monitoring module and a phase measurement module, the phase measurement module can adopt a high-speed logic chip, the reference source signal monitoring module is used for monitoring a reference source signal, and the phase measurement module is used for performing phase measurement on an input reference source signal and sending measurement data to the operation unit in real time.
The operation unit comprises a reference source comparison module, a reference source optimization module, a reference source switching module and a deviation correction module, wherein the reference source comparison module is used for comparing reference source signals after phase measurement; the reference source optimization module is used for optimizing the compared reference source signal according to the IRGB signal; the reference source switching module is used for switching and selecting the reference source signal according to the optimal result, and the deviation rectifying module is used for synchronously optimizing the IRIGB signal according to the switched reference source signal, correcting and compensating the deviation of the output power clock signal and reducing the deviation statistic value.
The superheterodyne receiver comprises an oscillator and a voltage-controlled circuit, wherein the oscillator is connected with the signal processing unit, and the voltage-controlled circuit is connected with the operation unit. The super-heterodyne receiver is used for providing a local 10MHz clock signal for a system, and can be configured with a high-performance rubidium oscillator, a constant-temperature crystal oscillator or a temperature compensation crystal oscillator.
The working principle of the invention is as follows:
the double-Beidou antenna receives satellite signals, the satellite signals are divided into two paths after passing through the power divider, two paths of Beidou signals are respectively obtained and are Beidou signals 1 and Beidou signals 2, the obtained two paths of Beidou signals serve as reference source signals, the reference source signals and IRIGB signals are simultaneously transmitted into synchronous clock equipment, a clock synchronization module in the synchronous clock equipment switches and selects the reference source signals, closed-loop control is conducted on a superheterodyne receiver, and electric power clock signals are output. The invention adopts a passive Beidou time service technology, a high-precision phase measurement technology and a multi-channel clock lossless switching technology to finish a synchronous clock taking a double Beidou satellite system as a time reference.
As shown in fig. 4, the double beidou satellite synchronous clock method includes the following steps:
s1: monitoring an input reference source signal;
s2: carrying out phase measurement on an input reference source signal, and sending measurement data to an arithmetic unit in real time;
s3: comparing the reference source signals after phase measurement,
s4: optimizing the compared reference source signal according to the IRGB signal;
s5: the reference source signal is selected according to the preference result,
s6: and carrying out synchronous optimization on the IRIGB signal according to the switched reference source signal.
Claims (7)
1. Two big dipper satellite synchronization clock systems, its characterized in that: the big dipper antenna is connected with the power divider, the power divider is connected with the big dipper synchronous clock equipment, the big dipper antenna is used for receiving satellite signals, the power divider divides the received satellite signals into two big dipper signals, the two big dipper signals obtained are used as reference source signals, the big dipper synchronous clock equipment is simultaneously transmitted into with IRIGB electric power clock signals, the big dipper synchronous clock equipment is used for correcting and compensating the deviation of the input IRIGB electric power clock signals, and the big dipper antenna is output after reducing the deviation value.
2. The big Dipper satellite synchronous clock system of claim 1, wherein: the double-Beidou synchronous clock equipment comprises a mainboard, a clock synchronization module, a superheterodyne receiver, a power supply module, a monitoring module and a human-computer interface, wherein the clock synchronization module, the power supply and the monitoring module are all connected with the mainboard, an output interface and an input interface are arranged on the mainboard, the superheterodyne receiver is connected with the clock synchronization module, and the keyboard interface is connected with the clock synchronization module.
3. The big Dipper satellite synchronous clock system of claim 2, wherein: the clock synchronization module comprises a signal processing unit and an operation unit, wherein the signal processing unit is used for monitoring and phase measurement of a reference source signal and then transmitting data to the operation unit, and the operation unit is used for comparing and optimizing the reference source signal and correcting an IRIGB signal.
4. The big Dipper satellite synchronous clock system of claim 3, wherein: the signal processing unit comprises a reference source signal monitoring module and a phase measurement module, wherein the reference source signal monitoring module is used for monitoring a reference source signal, and the phase measurement module is used for performing phase measurement on an input reference source signal and transmitting measurement data to the operation unit in real time.
5. The big Dipper satellite synchronous clock system of claim 3, wherein: the operation unit comprises a reference source comparison module, a reference source optimization module, a reference source switching module and a deviation correction module, wherein the reference source comparison module is used for comparing reference source signals after phase measurement; the reference source optimization module is used for optimizing the compared reference source signal according to the IRGB signal; the reference source switching module is used for switching and selecting the reference source signal according to the optimal result, and the deviation rectifying module is used for synchronously optimizing the IRIGB signal according to the switched reference source signal.
6. The big Dipper satellite synchronous clock system of claim 3, wherein: the superheterodyne receiver comprises an oscillator and a voltage-controlled circuit, wherein the oscillator is connected with the signal processing unit, and the voltage-controlled circuit is connected with the operation unit.
7. The double Beidou satellite synchronous clock method is characterized by comprising the following steps:
s1: monitoring an input reference source signal;
s2: carrying out phase measurement on an input reference source signal, and transmitting measurement data to an arithmetic unit in real time;
s3: comparing the reference source signals after phase measurement,
s4: optimizing the compared reference source signal according to the IRGB signal;
s5: the reference source signal is selected according to the preference result,
s6: and carrying out synchronous optimization on the IRIGB signal according to the switched reference source signal.
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