CN114095113A - Device and method for generating two-type Z optimized binary complementary sequence pair signal - Google Patents
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Abstract
The invention belongs to the technical field of communication systems, and relates to a device and a method for generating a signal by a type II Z optimized binary complementary sequence; the device comprises a control circuit and a switch circuit; the input end of the switch circuit is connected with the code element 1 database, the code element-1 database and the binary symmetric Golay complementary sequence pair database; the output end of the switch circuit is connected with the shift register; the shift register is connected with a two-type Z optimized binary complementary sequence pair database; the control circuit controls the switch circuit to select a corresponding input end, and outputs the sequence segments in the input code element 1/-1 or/and binary symmetric Golay complementary sequence pair to the shift register for temporary storage, so as to form a type II Z optimized binary complementary sequence w and a type II Z optimized binary complementary sequence v which are inserted with odd code elements; the shift registers are merged and then output to a two-type Z optimized binary complementary sequence pair database; the two-type Z optimized binary complementary sequence pair obtained by the invention has adjustable sequence length and width of a zero correlation zone.
Description
Technical Field
The invention belongs to the technical field of communication systems, and particularly relates to a device and a method for generating a signal by using a type-II Z optimized binary complementary sequence of an insertion method.
Background
Have good correlationThe characteristic sequence is widely applied to the fields of computer science, digital communication, cryptography, radar technology and the like; sequences with good autocorrelation properties include maximal length sequences, Barker sequences, and Golay Complementary Pairs (GCPs), among others; wherein GCPs means that its Aperiodic Autocorrelation sum (AACSs) is zero at all non-zero time shifts. GCPs are widely used in radar, Inter-Symbol Interference (ISI), channel estimation, Orthogonal Frequency Division Multiplexing (OFDM) systems, and the like. Since the known binary GCPs are limited in length by 2α10β26γWherein, the alpha, the beta and the gamma are all nonnegative integers. Davis and Jedwab directly construct length of 2 based on standard generalized Boolean functionmThe GCPs of (1) are referred to as Golay-Davis-JedWeb (GDJ) complementary pairs.
Fan et al, 2007, propose Z-Complementary Pairs (ZCPs), GCPs being a special case of ZCPs, which are further divided into type I ZCPs and type II ZCPs. The type I ZCPs can be applied to a Quasi-Synchronous Code Division Multiple Access (QS-CDMA) system to reduce intersymbol interference and Multiple Access interference. Type II ZCPs can be used to suppress asynchronous interference, and in a broadband wireless communication system, ZCPs have a potential to suppress interference when minimum interference signal delay is very large, and in addition, in an Orthogonal Frequency Division Multiplexing (OFDM) system, reduction of Peak to Average Power Ratio (PAPR) has many influence factors, and ZCPs can reduce PAPR if Out-of-area Aperiodic Autocorrelation Sum (OZ-AACs) can be well controlled. ZCPs can be further divided into even-length and odd-length ZCPs according to length.
For Odd-length Binary ZCPs (OB-ZCPs, Odd-length Binary ZCPs) of arbitrary length N, regarding which the maximum width of zero-correlation region is (N +1)/2, Liu et al 2014 proposed that a length of 2 was obtained by inserting a deletion on a GDJ complementary pairmSystematic construction of optimal OB-ZCPs of. + -. 1. Adhikary et al in 2017 proposed that a length of 2 was obtained by inserting an element in GCPsα10β26γ+1 optimal OB-ZCPs. Adhikary et al, 2019, studiedIntrinsic properties of binary GCPs constructed by the Turing method and their use to construct length 2α10β26γ+1 optimal OB-ZCPs. In the same year Shen et al constructed a new binary Z-optimized OB-ZCPs by inserting 3 elements into the standard binary GDJ sequence. In 2020, Zeng et al insert an element into binary GCP with any length of N to obtain type II Z-optimized OB-ZCPs with the length of N + 1; zhi Gu et al construct type II Z-optimized OB-ZCPs of length 2N. + -.1 by horizontal ligation of pairs of sequences of different lengths. Wherein N is an arbitrary value. Tian et al proposed the construction of a length of 2 by inserting three elements in a complementary pair of GDJα10β26γ+3 type II Z-optimized OB-ZCPs. Wherein alpha is more than or equal to 1, beta is more than or equal to 0, and gamma is an integer more than or equal to 0.
However, these prior arts can not construct a two-type Z-optimized binary complementary sequence pair with all required lengths, and can not realize the width adjustment of the zero correlation zone, and the construction process is complicated and difficult.
Disclosure of Invention
Based on the problems in the prior art, it is an object of the present invention to provide a device and a method for generating a type-two Z-optimized binary complementary sequence pair signal, which can convert a known binary Golay complementary sequence pair into a type-two binary Z-optimized complementary sequence pair, wherein the ZCZ region of the obtained sequence has a width of
Wherein N is the sequence length.
In a first aspect of the present invention, the present invention provides a two-type Z optimized binary complementary sequence pair signal generation apparatus, comprising a control circuit and a switch circuit; the control circuit is connected with the switch circuit through a state gate of the switch circuit; the input end of the switch circuit is connected with a code element 1 database, a code element-1 database and a binary symmetric Golay complementary sequence pair database; the output end of the switch circuit is connected with a shift register; the shift register is connected with a two-type Z optimized binary complementary sequence pair database;
when the control circuit controls the switch circuit to enter an on state,controlling the switching circuit to select the corresponding input terminal and to combine the input symbols 1/-1 or/and the sequence segments (a, b) in the binary symmetric Golay complementary sequence pair (a, b)1,a2,b1,b2) Outputting the signals to a shift register for temporary storage, and forming a first type Z optimized binary complementary sequence w and a second type Z optimized binary complementary sequence v which are respectively inserted with odd code elements; the shift register outputs the combined first type Z optimized binary complementary sequence w and the second type Z optimized binary complementary sequence v to a type Z optimized binary complementary sequence pair database;
wherein a ═ a1,a2)；b＝(b1,b2)；a1Representing the first half sequence of the first sequence a; a is2Representing the second half of the first sequence a, b1Represents the first half sequence of the second sequence b; b2Represents the second half sequence of the second sequence b.
In a second aspect of the present invention, the present invention further provides a method for generating a type Z optimized binary complementary sequence pair signal, the method comprising:
taking the Golay complementary sequence pair with even length, which has the same sequence in the first half and opposite sequence in the second half, as a binary symmetric Golay complementary sequence pair (a, b) as a seed pair;
in the first half of the first sequence a1 Inserting symbol 1 or symbol-1 in the front, and the second half segment sequence a2Then inserting code element 1 or code element-1, outputting the first type Z optimized binary complementary sequence w;
in the first half of the second sequence b1Inserting symbol 1 or symbol-1 in the front, and the second half segment sequence b2Then inserting code element 1 or code element-1, and outputting a second type Z optimized binary complementary sequence v;
splicing the first type Z optimized binary complementary sequence w and the second type Z optimized binary complementary sequence v to output a type Z optimized binary complementary sequence pair signal (w, v);
wherein odd symbols are inserted in the first sequence a and odd symbols are inserted in the second sequence b.
The invention has the beneficial effects that:
the invention can generate the odd-length type-Z optimized binary complementary sequence pair reaching the maximum zero correlation zone width by arbitrarily selecting the binary symmetric Golay complementary sequence pair with the even length of N as the seed pair of the invention and adjusting the obtained type-Z optimized binary complementary sequence pair in the sequence length and the zero correlation zone width; the invention can be applied to signal processing, communication system and large-programming integrated circuit test, etc. The Z-complementary sequence has more flexible code element length and more sequence number compared with Golay complementary sequence pair, and is widely applied to orthogonal frequency division multiplexing systems, code division multiple access systems and the like. Compared to known results, the new sequences constructed produced a type II Z optimized binary complementary sequence pair of the same length, outperformed the known sequences in reducing peak-to-average envelope power ratio, and provided a greater diversity of sequence choices.
Drawings
FIG. 1 is a schematic circuit diagram of a two-type binary Z-optimized sequence pair signal generating apparatus in a communication system according to the present invention;
FIG. 2 is a schematic block diagram of a method for generating a type-two Z-optimized binary complementary sequence pair using the interpolation method according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. FIG. 1 is a schematic diagram of a circuit structure of a generation apparatus of a two-type binary Z-optimized sequence pair signal according to an embodiment of the present invention, as shown in FIG. 1, the generation apparatus includes a control circuit and a switch circuit; the control circuit is connected with the switch circuit through a state gate of the switch circuit; wherein R represents a switch circuit, when the switch circuit is arranged at a point D to represent that the switch circuit is in an off state, the switch circuit comprises an input end A, an input end B and an input end C, wherein the input end A is connected with a binary symmetric Golay complementary sequence pair database, the input end B is connected with a code element 1 database, the input end C is connected with a code element-1 database, the point A represents that the binary symmetric Golay complementary sequence pair database is connected with a shift register, the point B represents that the code element 1 database is connected with the shift register, and the point C represents that the code element-1 database is connected with the shift register; the output end of the switch circuit is connected with a shift register; the shift register is connected with a two-type Z optimized binary complementary sequence pair database.
In the embodiment of the present invention, each unit in the generating device at least includes the following functions:
the control circuit is used for controlling the states of all the devices and the insertion of sequences;
the binary symmetric Golay complementary sequence pair database for storing binary symmetric Golay complementary sequence pairs (a, b);
the code element 1 database is used for storing a database only containing code elements 1;
the code element-1 database is used for storing the database only containing the code element-1;
the switch circuit is used for controlling the connection of a code element 1 database, a code element-1 database, a binary symmetric Golay complementary sequence pair database and a shift register;
the shift register is used for realizing the temporary storage of the sequence after the functional level is inserted into the code element;
the two-type binary Z optimized complementary sequence pair database is used for storing the output sequence pairs (w, v).
In the embodiment of the invention, when the control circuit controls the switch circuit to enter the on state, the control circuit controls the switch circuit to select the corresponding input end and input the code 1/-1 or/and the sequence segment (a) in the binary symmetric Golay complementary sequence pair (a, b)1,a2,b1,b2) Outputting the signals to a shift register for temporary storage, and forming a first type Z optimized binary complementary sequence w and a second type Z optimized binary complementary sequence v which are respectively inserted with odd code elements; the shift register outputs the combined first type Z optimized binary complementary sequence w and the second type Z optimized binary complementary sequence v to a type Z optimized binary complementary sequence pair database;
wherein, a＝(a1,a2)；b＝(b1,b2)；a1Representing the first half sequence of the first sequence a; a is2Representing the second half of the first sequence a, b1Represents the first half sequence of the second sequence b; b2Represents the second half sequence of the second sequence b.
In particular, binary inserted symbols in the present invention, such as the sequence a, refer to symbols respectively inserted in the (1,1,1) sequences; in addition, the binary vector is designed by a sequence user according to needs and generated in a control circuit, and the specific value of the binary vector is designed according to actual needs.
In the embodiment of the invention, the control of the switch circuit to select the corresponding input end comprises the control of accessing a code element 1 database or a code element-1 database before accessing a binary symmetric Golay complementary sequence pair database; after the binary symmetric Golay complementary sequence pair database is controlled to be accessed, the code element database 1 or the code element-1 database is controlled to be accessed, in this embodiment, the code element database can be accessed before and after the binary symmetric Golay complementary sequence pair database is accessed, that is, the code elements can be inserted into the head and the tail of the binary symmetric Golay complementary sequence respectively to form a new sequence signal.
In a preferred embodiment of the present invention, between controlling access to the database of binary symmetric Golay complementary sequence pairs twice, access to the symbol 1 database or the symbol-1 database is also controlled. In this embodiment, a code element database may be accessed between two times of accessing the binary symmetric Golay complementary sequence pair database, that is, a code element may be inserted between the first half sequence and the second half sequence of the binary symmetric Golay complementary sequence, so as to form a new sequence signal.
In some embodiments, for convenience of illustration, the result (1, | a) is generated in the embodiment1||,1,||a21), the generation process of the first type Z optimized binary complementary sequence w is detailed to include:
the control circuit controls the switch circuit to be in an off state, and the zero clearing operation is carried out on the shift register;
the control circuit makes the code element 1 database connected with the shift register by controlling the switch circuit, and moves the one-bit code element 1 into the shift register;
the control circuit enables the binary symmetric Golay complementary sequence pair database to be connected with the shift register through controlling the switch circuit, and the code elements of the selected sequence a in the database are serially shifted into the shift register;
when the code element 1 is shifted to one half of the sequence a, the control circuit enables the code element 1 database to be connected with the shift register through controlling the switch circuit, and the one-bit code element 1 is shifted into the shift register;
the control circuit enables the binary symmetric Golay complementary sequence pair database to be connected with the shift register through controlling the switch circuit, and the rest half of the sequence a is shifted into the shift register;
the control circuit makes the code element 1 database connected with the shift register by controlling the switch circuit, and moves the one-bit code element 1 into the shift register to obtain the two-type binary Z optimized complementary sequence w;
the control circuit controls the switch circuit to be in an off state, and the control circuit controls the shift register to shift the generated two-type binary Z optimized complementary sequence w into the two-type binary Z optimized complementary sequence pair database for storage.
For the control process of the switching circuit, specifically:
the control circuit controls the switch R to be arranged at a point D, and then the shift register is cleared;
the switch R is arranged at the point B, and the control circuit controls the code element 1 database to move the one-bit code element 1 into the shift register;
the switch R is connected with the point A, and the control circuit controls the code elements of the selected sequence a in the binary symmetrical Golay complementary sequence pair to be serially shifted into the shift register until the front end of the half of the sequence a;
the switch R is arranged at a point B, and the control circuit controls the code element 1 database to move a bit code element 1 into the shift register;
the switch R is connected with the point A, and the control circuit controls the code elements of all the residual sequences a in the binary symmetrical Golay complementary sequence pair to be serially shifted into the shift register;
the switch R is arranged at the point B, the control circuit controls the code element 1 database to move the one-bit code element 1 into the shift register, and the generation of the two-type binary Z optimized complementary sequence w is finished;
the switch R is connected with the point D, and the control circuit controls the two-type binary Z optimized complementary sequence w generated by the shift register to be shifted into a two-type binary Z optimized complementary sequence pair database storage or other application circuits.
In some embodiments, the result (1, | b) is generated in the present embodiment1||,1,||b21), the generation process of the first type Z optimized binary complementary sequence v is detailed to include:
the control circuit controls the switch circuit to be in an off state and carries out zero clearing operation on the shift register;
the control circuit enables the code element 1 database to be connected with the shift register by controlling the switch circuit, and a bit of code element 1 is shifted into the shift register;
the control circuit enables the binary symmetric Golay complementary sequence pair database to be connected with the shift register through controlling the switch circuit, and serially shifts the code elements of the selected sequence b in the database into the shift register;
when shifting to half of the sequence b, the control circuit shifts the one-bit code element 1 into the shift register by controlling the switch circuit;
the control circuit enables the binary symmetric Golay complementary sequence pair database to be connected with the shift register through controlling the switch circuit, and the remaining half sequence b is shifted into the shift register;
the control circuit makes the code element-1 database connected with the shift register by controlling the switch circuit, and shifts one-bit code element-1 into the shift register to obtain a two-type binary Z optimized complementary sequence v;
the control circuit controls the switch circuit to be in an off state, and the control circuit controls the shift register to transfer the generated two-type binary Z optimized complementary sequence v into the two-type binary Z optimized complementary sequence pair database for storage.
For the control process of the switching circuit, specifically:
the control circuit controls the switch R to be arranged at a point D, and then the shift register is cleared;
the switch R is arranged at the point B, and the control circuit controls the code element 1 database to move the one-bit code element 1 into the shift register;
the switch R is connected with the point A, and the control circuit controls the code elements of the selected sequence b in the binary symmetrical Golay complementary sequence pair to be serially shifted into the shift register until the front end of the half of the sequence b;
the switch R is arranged at the point B, and the control circuit controls the code element 1 database to move the one-bit code element 1 into the shift register;
the switch R is connected with the point A, and the control circuit controls the code elements of all the remaining sequences b in the binary symmetrical Golay complementary sequence pair to be serially shifted into the shift register;
the switch R is arranged at the point C, the control circuit controls the code element-1 database to move one code element-1 into the shift register and stop, and the generation of the two-type binary Z optimized complementary sequence v is finished;
the switch R is connected with a point D, and the control circuit controls the two-type binary Z optimized complementary sequence v generated by the shift register to be shifted into a two-type binary Z optimized complementary sequence pair database storage or other application circuits.
The generating means may then continue to generate the desired pair of two-type binary Z-optimized complementary sequences, either off or on standby, as desired.
It is understood that, in the present invention, an odd number of symbols 1 or symbols-1 are inserted into the sequence head and sequence tail in each binary symmetric Golay complementary sequence, and of course, it is also possible to insert symbols 1 or symbols-1 into the middle of the sequence at the same time, as long as it is ensured that both the sequence head and the sequence tail are inserted with symbols, and the total number of inserted symbols is odd number, which shall be within the protection scope of the present invention, and the present invention does not exemplify this in detail.
In some embodiments, the control circuit may power all other units such as a switching circuit, a binary symmetric Golay complementary sequence pair database, a symbol 1 database, a symbol-1 database, a shift register, and a two-type Z optimized binary complementary sequence pair database operated by the power provided by the control circuit.
In other embodiments, the other units may also use an external power supply to ensure the normal operation of the units.
Fig. 2 is a method for generating a type two Z optimized binary complementary sequence pair signal according to an embodiment of the present invention, as shown in fig. 2, the method includes:
taking the Golay complementary sequence pair with even length, which has the same sequence in the first half and opposite sequence in the second half, as a binary symmetric Golay complementary sequence pair (a, b) as a seed pair;
in the first half of the first sequence a1Inserting symbol 1 or symbol-1 in the front, and the second half segment sequence a2Then inserting code element 1 or code element-1, outputting the first type Z optimized binary complementary sequence w;
in the first half of the second sequence b1Inserting symbol 1 or symbol-1 in the front, and the second half segment sequence b2Then inserting code element 1 or code element-1, and outputting a second type Z optimized binary complementary sequence v;
splicing the first type Z optimized binary complementary sequence w and the second type Z optimized binary complementary sequence v to output a type Z optimized binary complementary sequence pair signal (w, v);
wherein odd symbols are inserted in the first sequence a and odd symbols are inserted in the second sequence b.
In a preferred embodiment of the invention, the invention also provides for the first half of the sequence a of the first sequence a1And the second half sequence a2Inserting code element 1 or code element-1; in the first half of the second sequence b1And the second half sequence b2With symbol 1 or symbol-1 inserted in between.
In the embodiment of the present invention, the second type Z optimized binary complementary sequence w is at least expressed as (.. i.i.)1,||a1||,||a2||,i2,i3...); the second type Z optimized binary complementary sequence v is expressed as (.. j)1,||b1||,||b2||,j2,j3...), or the type I Z-optimized binary complement sequence w is expressed as (.. i.i.)1,i2,||a1||,||a2||,i3...); the second type Z optimized binary complementary sequence v is expressed as (.. j)1,j2,||b1||,||b2||,j3...); wherein，ik,jkE { ± 1}, k e {1,2,3},. denotes symbol 1 or symbol-1, if any.
This example shows that in the first half of the first sequence a, the sequence a1While the odd number of symbols are inserted previously, the sequence a needs to be in the second half of the first sequence a2And inserting even number of code elements to ensure that the number of the inserted code elements is odd number, so that the generated first type Z optimized binary complementary sequence w has odd length. Or, in the first half of the first sequence a1While even number of symbols are inserted before, the sequence a needs to be in the second half of the first sequence a2And inserting odd symbols to ensure that the number of the inserted symbols is odd, so that the generated first type Z optimized binary complementary sequence w has odd length.
Similarly, in the first half of the second sequence b, the sequence b1While the odd number of symbols are inserted previously, the sequence b needs to be in the second half of the second sequence b2And inserting even number of code elements to ensure that the number of the inserted code elements is odd number, so that the generated second type Z optimized binary complementary sequence v has odd length. Or, in the first half of the second sequence b1While an even number of symbols are inserted before, the sequence b needs to be in the second half of the second sequence b2Inserting odd number of code elements to ensure the number of the inserted code elements is odd number, so that the generated second type Z optimized binary complementary sequence v is odd length.
In a preferred embodiment of the invention, said type I Z-optimized binary complementary sequence w is represented as (.. i.i.)1,||a1||,i2...,||a2||,i3...); the second type Z optimized binary complementary sequence v is expressed as (.. j)1,||b1||,j2...,||b2||,j3...), wherein ik,jk∈{±1}，k∈{1,2,3}。
This example shows that in the first half of the first sequence a, the sequence a1While the odd number of symbols are inserted previously, the sequence a needs to be in the second half of the first sequence a2Inserting odd number of code elements and requiring the first half sequence a1And second half-sequence a2BetweenAnd inserting odd symbols to ensure that the number of the inserted symbols is odd, so that the generated first type Z optimized binary complementary sequence w has odd length.
Similarly, in the first half of the second sequence b, the sequence b1While the odd number of symbols are inserted previously, the sequence b needs to be in the second half of the second sequence b2Inserting odd number of code elements while requiring the first half sequence b1And the second half sequence b2Odd number of code elements are inserted between the first type Z optimized binary complementary sequence v and the second type Z optimized binary complementary sequence v is of odd length.
For ease of understanding, this embodiment takes a binary Golay optimized sequence when N-8 as a seed pair, which is expressed as:
let (a, b) be a symmetric binary Golay complementary sequence pair of length 8.
w＝(1,1-1,1,1,1,1,-1)；
v＝(1,1-1,1,-1,-1,-1,1)；
Let (i1, i2, i3, j1, j2, j3) — 1,1, -1, -1,1,1, we can get the type-Z optimized binary complementary sequence pair (w, v) with length of 11 according to the insertion method proposed in this patent.
w＝(-1,1,1-1,1,1,1,1,1,-1,-1)；
v＝(-1,1,1-1,1,1,-1,-1,-1,1,1)；
In conclusion, the simulation results are consistent with the proving formula, so that the invention is feasible.
It is understood that, in the embodiments of the present invention, the apparatus for generating a signal of type two Z-optimized binary complementary sequence pair and the method for generating a signal of type two Z-optimized binary complementary sequence pair all belong to the same concept of the present invention, and the corresponding features thereof can be cited mutually, which is not illustrated in the present invention.
In the invention, a Z-optimized OB-ZCPs with the maximum zero correlation zone, which is not limited by the number of binary GDJ complementary sequence pairs, has more flexible length and is constructedHas very important theoretical significance and practical value. The binary GDJ complementary sequence pair is a proper subset of the binary Golay complementary sequence pair, and compared with other methods, the method has more advantage in quantity by taking the binary symmetric Golay complementary sequence pair as a seed pair; the patent generates an odd length of N-2α10β26γ+3 type II Z-optimized complementary sequence pairs, not limited to the even form of the Golay sequence, with more lengths available for application choice; the sequences constructed by the invention have the maximum zero correlation zone width and form a Z optimized binary complementary sequence pair; on the basis of the construction of a partial insertion method, the invention provides complete supplement and perfection. The new sequence constructed by the invention can generate odd-length type II Z optimized binary complementary sequence pairs, can be widely applied to an orthogonal frequency division multiplexing system and a code division multiple access system, effectively reduces the peak-to-average envelope power ratio and the like, and provides more diverse sequence selections.
In the description of the present invention, it is to be understood that the terms "coaxial", "bottom", "one end", "top", "middle", "other end", "upper", "one side", "top", "inner", "outer", "front", "center", "both ends", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "disposed," "connected," "fixed," "rotated," and the like are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; the terms may be directly connected or indirectly connected through an intermediate, and may be communication between two elements or interaction relationship between two elements, unless otherwise specifically limited, and the specific meaning of the terms in the present invention will be understood by those skilled in the art according to specific situations.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (8)
1. A generation device of a two-type Z optimized binary complementary sequence pair signal is characterized by comprising a control circuit and a switch circuit; the control circuit is connected with the switch circuit through a state gate of the switch circuit; the input end of the switch circuit is connected with a code element 1 database, a code element-1 database and a binary symmetric Golay complementary sequence pair database; the output end of the switch circuit is connected with a shift register; the shift register is connected with a two-type Z optimized binary complementary sequence pair database;
when the control circuit controls the switch circuit to enter an on state, the control circuit controls the switch circuit to select a corresponding input end and inputs the input code 1/-1 or/and the sequence segment (a) in the binary symmetric Golay complementary sequence pair (a, b)1,a2,b1,b2) Outputting the binary sequence to a shift register for temporary storage, and forming a first type Z optimized binary complementary sequence w and a second type Z optimized binary complementary sequence v which are respectively inserted with odd code elements; the shift register outputs the combined first type Z optimized binary complementary sequence w and the second type Z optimized binary complementary sequence v to a type Z optimized binary complementary sequence pair database;
wherein a ═ a (a)1,a2)；b＝(b1,b2)；a1Representing the first half sequence of the first sequence a; a is2Representing the second half of the first sequence a, b1Represents the first half sequence of the second sequence b; b2Represents the second half sequence of the second sequence b.
2. The apparatus of claim 1, wherein the means for controlling the switching circuit to select the corresponding input comprises means for controlling access to a symbol-1 database or a symbol-1 database prior to access to a binary symmetric Golay complementary sequence pair database; after controlling access to the database of binary symmetric Golay complementary sequence pairs, controlling access to the symbol 1 database or the symbol-1 database.
3. The apparatus of claim 2, wherein the first type Z optimized binary complementary sequence w is expressed as a.i.i. sequence1,||a1||,||a2||,i2,i3...) and the second type Z-optimized binary complementary sequence v is expressed as (.. j)1,||b1||,||b2||,j2,j3...); or the first two type Z optimized binary complementary sequences w are expressed as (.. i.i)1,i2,||a1||,||a2||,i3...) and the second type Z-optimized binary complementary sequence v is expressed as (.. j)1,j2,||b1||,||b2||,j3...); wherein ik,jk∈{±1}，k∈{1,2,3}。
4. The apparatus of claim 2, wherein the means for controlling the switching circuit to select the corresponding input further comprises means for controlling access to a symbol-1 database or a symbol-1 database between two times of controlling access to the database of binary symmetric Golay complementary sequence pairs.
5. The apparatus of claim 4, wherein the first type Z optimized binary complementary sequence w is expressed as (.. i.i)1,||a1||,i2...,||a2||,i3...); the second type Z optimized binary complementary sequence v is expressed as (.. j)1,||b1||,j2...,||b2||,j3...), wherein ik,jk∈{±1}，k∈{1,2,3}。
6. The apparatus of claim 1, further comprising a control circuit for controlling the switch circuit to be in an off state and clearing the shift register before the switch circuit enters the on state.
7. A method for generating a type-Z optimized binary complementary sequence pair signal, the method comprising:
taking the Golay complementary sequence pair with even length, which has the same sequence in the first half and opposite sequence in the second half, as a binary symmetric Golay complementary sequence pair (a, b) as a seed pair;
in the first half of the first sequence a1Inserting symbol 1 or symbol-1 in the front, and the second half segment sequence a2Then inserting code element 1 or code element-1, outputting the first type Z optimized binary complementary sequence w;
sequence b in the first half of the second sequence b1Inserting symbol 1 or symbol-1 in the front, and the second half segment sequence b2Then inserting code element 1 or code element-1, and outputting a second type Z optimized binary complementary sequence v;
splicing the first type Z optimized binary complementary sequence w and the second type Z optimized binary complementary sequence v to output a type Z optimized binary complementary sequence pair signal (w, v);
wherein odd symbols are inserted in the first sequence a and odd symbols are inserted in the second sequence b.
8. The method of claim 7, further comprising generating the second type Z optimized binary complementary sequence pair signal in the first half of the first sequence a1And the second half sequence a2Inserting code element 1 or code element-1; in the first half of the second sequence b1And second half sequence b2With symbol 1 or symbol-1 inserted in between.
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