CN114093935A - Field effect transistor, storage and calculation integrated chip, circuit and equipment - Google Patents

Field effect transistor, storage and calculation integrated chip, circuit and equipment Download PDF

Info

Publication number
CN114093935A
CN114093935A CN202210065533.2A CN202210065533A CN114093935A CN 114093935 A CN114093935 A CN 114093935A CN 202210065533 A CN202210065533 A CN 202210065533A CN 114093935 A CN114093935 A CN 114093935A
Authority
CN
China
Prior art keywords
effect transistor
field effect
logic
oxygen vacancies
positively charged
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202210065533.2A
Other languages
Chinese (zh)
Other versions
CN114093935B (en
Inventor
刘欢
玉虓
韩根全
刘艳
金成吉
陈佳佳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhejiang Lab
Original Assignee
Zhejiang Lab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhejiang Lab filed Critical Zhejiang Lab
Priority to CN202210065533.2A priority Critical patent/CN114093935B/en
Publication of CN114093935A publication Critical patent/CN114093935A/en
Priority to JP2022577533A priority patent/JP2024509339A/en
Priority to PCT/CN2022/091334 priority patent/WO2023137927A1/en
Application granted granted Critical
Publication of CN114093935B publication Critical patent/CN114093935B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses a field effect transistor with a function of mutually converting logic characteristics and storage characteristics, a storage and calculation integrated chip, a circuit and equipment. The gate structure comprises a substrate, an insulating interface layer, a gate dielectric layer and a gate electrode from bottom to top; and a source electrode and a drain electrode are respectively arranged on two sides of the substrate, and the gate dielectric layer is provided with movable ions with positive charge oxygen vacancies. When a high-frequency pulse is applied to the gate electrode, the positively charged oxygen vacancies are in a trapped state, so that the field effect transistor has logic characteristics and can be used as a logic device; when a low-frequency pulse is applied to the gate electrode, the positively charged oxygen vacancies are in a de-trapped state, so that the field effect transistor has memory characteristics and can be used as a memory device. The invention can realize the mutual conversion between the logic characteristic and the storage characteristic and keep the stable state of a high-performance device, and can be used for a three-dimensional heterogeneous integrated chip integrating storage and calculation.

Description

Field effect transistor, storage and calculation integrated chip, circuit and equipment
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a field effect transistor with a function of mutual conversion between logic characteristics and storage characteristics, a storage-calculation integrated chip, a circuit and equipment.
Background
With the further development of moore's law, the feature size is continuously reduced, the integration level and the performance are continuously improved, and the power consumption problem caused by the feature size is increasingly serious. The traditional von Neumann structure has the problems of long delay time, limited bandwidth, large parasitic load on a memory bus and high power consumption of large data access. The monolithic three-dimensional integrated circuit combines a high-performance gate all-around logic transistor (GAA MOSFET) based on Back-End-Of-line (BEOL) and a ferroelectric memory, can realize low power consumption and high bandwidth signal transmission, has the advantages Of low manufacturing cost, small circuit area and high bandwidth interconnection, however, the performance Of the transistor based on the Back-End process and the three-dimensional integrated circuit is limited by a low thermal budget preparation technology.
Disclosure of Invention
In view of the above-described drawbacks of the prior art, an object of the present invention is to provide a field effect transistor having a function of mutually converting logic characteristics and memory characteristics.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a first aspect of embodiments of the present invention provides a field effect transistor having a function of switching between a logic device and a memory device, including: the gate structure comprises a substrate, an insulating interface layer, a gate dielectric layer, oxygen vacancies with positive charges, a gate electrode, a source and a drain; the insulating interface layer, the gate dielectric layer and the gate electrode are vertically distributed on the upper surface of the substrate from bottom to top; the source electrode and the drain electrode are respectively arranged on two sides of the upper surface of the substrate, and the insulating interface layer is arranged between the source electrode and the drain electrode;
the gate dielectric layer is internally provided with the positively charged oxygen vacancies, and the positively charged oxygen vacancies are movable ions, wherein the positively charged oxygen vacancies can be switched between a first state and a second state, so that the field effect transistor is correspondingly switched between a function used as a logic device and a function used as a storage device;
the first state is: the positively charged oxygen vacancies are trapped and neutralized by the interface of the insulating interfacial layer and/or the interface of the gate electrode;
the second state is: the positively charged oxygen vacancies are in a de-trapped state.
Optionally, when the gate electrode is applied with a high-frequency pulse, the positively charged oxygen vacancies are in the first state, so that the field effect transistor has logic characteristics and can be used as a logic device;
when the gate electrode is applied with a low-frequency pulse, the positively charged oxygen vacancies are in the second state, so that the field effect transistor has memory characteristics and can be used as a memory device.
Optionally, the frequency of the high frequency pulses is greater than or equal to 1 kHz; and/or
The frequency of the low frequency pulses is less than or equal to 10 Hz.
Optionally, the substrate is a semiconductor material, and the semiconductor material includes one of silicon Si, germanium Ge, silicon germanium SiGe, silicon on insulator SOI, or germanium on insulator GOI.
Optionally, the insulating interface layer comprises a silicon oxide material SiO2Silicon nitride material Si3N4SiON, GeO, SiON, GeO, SiON, GeO, SiON, GeO, SiON, GeO, SiON, GeO, SiON, GeO, SiON, GeO, SiON, GeO, SiON, GeO, SiON, GeO, or a material such a material2And alumina material Al2O3One kind of (1).
Optionally, the gate dielectric layer is an insulating oxide, and the insulating oxide includes hafnium oxide HfO2Zirconium oxide ZrO2Aluminum oxide Al2O3La, lanthanum oxide2O3Yttrium oxide Y2O3Titanium oxide TiO2Silicon oxide SiO2And germanium oxide GeO2One kind of (1).
Optionally, the gate electrode is a nitride metal comprising one of tantalum nitride TaN, titanium nitride TiN, molybdenum nitride MoN, and tungsten nitride WN.
A second aspect of the embodiments of the present invention provides a storage integrated chip, including a chip main body and the field effect transistor having a function of mutually converting a logic device and a memory device according to the first aspect, wherein the field effect transistor is disposed on the chip main body.
A third aspect of the embodiments of the present invention provides a saving and calculating integrated circuit, including a circuit board main body and the saving and calculating integrated chip of the second aspect, where the saving and calculating integrated chip is disposed on the circuit board main body.
A fourth aspect of the embodiments of the present invention provides a banking machine including a housing and the banking integrated circuit of the third aspect, wherein the banking integrated circuit is disposed on the housing.
The invention has the beneficial effects that: the invention provides a field effect transistor which has the function of interconversion between a logic device and a storage device, can realize the integral storage and calculation characteristic of a single transistor, is compatible with a silicon-based CMOS (complementary metal oxide semiconductor) process in the preparation process of the transistor, can greatly reduce leakage current and reduce power consumption due to low thermal budget, and thus realizes a high-density integral storage and calculation three-dimensional heterogeneous integrated chip.
Drawings
The invention is described in further detail below with reference to the figures and specific embodiments.
FIG. 1 is a schematic cross-sectional view of a field effect transistor having a function of mutually converting a logic characteristic and a memory characteristic according to the present invention;
FIG. 2 is a schematic view of a manufacturing process of a first embodiment of the present invention;
fig. 3 is a graph showing a transition of a field effect transistor having a function of mutually converting a logic characteristic and a memory characteristic into a memory characteristic in an initial state;
fig. 4 is a graph showing a transition from a memory characteristic to a logic characteristic of a field effect transistor having a function of converting a logic characteristic to a memory characteristic;
fig. 5 is a graph showing a transition from the logic characteristic to the memory characteristic of the field effect transistor having the function of mutually converting the logic characteristic and the memory characteristic.
In the above figures: 1. a substrate; 2. an insulating interface layer; 3. a gate dielectric layer; 4. a positively charged oxygen vacancy; 5. a gate electrode; 6. a source electrode; 7. and a drain electrode.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the invention, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present invention. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
The field effect transistor having a function of mutually converting logic characteristics and memory characteristics of the present invention will be described in detail with reference to examples. The features of the following examples and embodiments may be combined with each other without conflict.
Referring to fig. 1, an example of the present invention provides a field effect transistor having a function of interconverting logic characteristics and memory characteristics, which may include a substrate 1, an insulating interface layer 2, a gate dielectric layer 3, positively charged oxygen vacancies 4, a gate electrode 5, a source 6, and a drain 7. Wherein, the insulating interface layer 2, the gate dielectric layer 3 and the gate electrode 5 are distributed on the upper surface of the substrate 1 from bottom to top; the source electrode 6 and the drain electrode 7 are arranged on two sides of the upper surface of the substrate 1, and the insulating interface layer 2 is arranged between the source electrode 6 and the drain electrode 7.
In the embodiment of the invention, movable ions with positive charge oxygen vacancies 4 are arranged in the gate dielectric layer 2, specifically, the positive charge oxygen vacancies 4 are arranged in the gate dielectric layer 3, and the positive charge oxygen vacancies 4 are movable ions. Wherein the positively charged oxygen vacancies 4 are capable of switching between a first state and a second state such that the field effect transistor is correspondingly switched between a function for use as a logic device and a function for use as a memory device. The first state is: the positively charged oxygen vacancies 4 are trapped and neutralized by the interface of the insulating interfacial layer 2 and/or the interface of the gate electrode 5. The second state is: the positively charged oxygen vacancies 4 are in a de-trapped state.
According to the field effect transistor provided by the embodiment of the invention, the positively charged oxygen vacancy 4 with the movable ions is arranged in the gate dielectric layer 3, and the movable ions are regulated and controlled, so that the field effect transistor has the function of mutual conversion of logic characteristics and storage characteristics, the storage and calculation integrated characteristic of a single transistor can be realized, meanwhile, the preparation process of the transistor is compatible with a silicon-based CMOS (complementary metal oxide semiconductor) process, the amorphous gate dielectric is free from high-temperature annealing, the low thermal budget can greatly reduce leakage current, the power consumption is reduced, and a high-density storage and calculation integrated three-dimensional heterogeneous integrated chip is realized.
It is noted that in some embodiments, when the positively charged oxygen vacancies 4 are in the first state, the positively charged oxygen vacancies 4 are fully neutralized by the interfacial traps of the insulating interfacial layer 2; in some embodiments, when the positively charged oxygen vacancies 4 are in the first state, the positively charged oxygen vacancies 4 are fully neutralized by the interface traps of the gate electrode 5; in some embodiments, when the positively charged oxygen vacancies 4 are in the first state, a portion of the positively charged oxygen vacancies 4 are neutralized by the interface traps of the insulating interfacial layer 2 and another portion are neutralized by the interface traps of the gate electrode 5.
The manner in which the positively charged oxygen vacancies 4 are controlled to switch between the first state and the second state can include a variety of manners, for example, in some embodiments, the positively charged oxygen vacancies 4 are controlled to switch between the first state and the second state by varying the frequency magnitude of the pulse applied to the gate electrode 5, and specifically, the positively charged oxygen vacancies 4 are in the first state when the gate electrode 5 is applied with a high frequency pulse, so that the field effect transistor has logic characteristics and can be used as a logic device. When a low frequency pulse is applied to the gate electrode 5, the positively charged oxygen vacancies 4 are in the second state, so that the field effect transistor has memory characteristics and can be used as a memory device. In this embodiment, the frequency of the high frequency pulses is greater than or equal to 1kHz and/or the frequency of the low frequency pulses is less than or equal to 10 Hz. Illustratively, the frequency of the high frequency pulses may be selected to be 1kHz, 2kHz, 3kHz, 4kHz, 5kHz, 6kHz, 7kHz, 8kHz, 9kHz, 10kHz or other values greater than 1kHz, and/or the frequency of the low frequency pulses may be selected to be 1Hz, 2Hz, 3Hz, 4Hz, 5Hz, 6Hz, 7Hz, 8Hz, 9Hz, 10Hz or other values less than 10 Hz.
The materials of the substrate 1, the insulating interface layer 2, the gate dielectric layer 3 and the gate electrode 5 can be set as required.
The substrate 1 may be a semiconductor material, for example, the material of the substrate 1 may include one of silicon Si, germanium Ge, silicon germanium SiGe, silicon on insulator SOI, or germanium on insulator GOI; of course, the material of the substrate 1 may be other types of semiconductor materials.
The insulating interfacial layer 2 may comprise a silicon oxide material SiO2Silicon nitride material Si3N4SiON, GeO, SiON, GeO, SiON, GeO, SiON, GeO, SiON, GeO, SiON, GeO, SiON, GeO, SiON, GeO, SiON, GeO, SiON, GeO, SiON, GeO, or a material such a material2And alumina material Al2O3At least one of (1); of course, the material of the insulating interface layer 2 may be other types of materials.
The gate dielectric layer 3 may comprise an insulating oxide comprising oxygenHafnium oxide HfO2Zirconium oxide ZrO2Aluminum oxide Al2O3La, lanthanum oxide2O3Yttrium oxide Y2O3Titanium oxide TiO2Silicon oxide SiO2And germanium oxide GeO2One of (1); of course, the material of the gate dielectric layer 3 may be other types of materials.
The gate electrode 5 may include a nitride metal including one of tantalum nitride TaN, titanium nitride TiN, molybdenum nitride MoN, and tungsten nitride WN; of course, the gate electrode 5 may be made of other types of materials.
Next, several processes of forming a structure of a field effect transistor having a function of converting a logic characteristic and a memory characteristic to each other are described.
Example 1
Amorphous ZrO based on oxygen vacancies having a positive charge2The transistor of the gate dielectric has the function of interconversion between the logic device and the memory device, and referring to fig. 2, the manufacturing steps of the transistor are as follows;
step 1, selecting a substrate and cleaning.
In the embodiment, an n-type germanium sheet Ge is selected as a substrate 1, and the substrate is cleaned conventionally.
Step 2, depositing amorphous zirconia ZrO2A film as shown in fig. 2 (a).
Deposition of 3.5 nm zirconium oxide ZrO on a substrate 1 with a plasma enhanced atomic layer deposition PEALD apparatus2As the gate dielectric layer 3, the deposition process conditions are as follows: tetradimethylamino zirconium is used as a zirconium source of a precursor, water is used as an oxygen source of the precursor, and the deposition temperature is 250 ℃. Wherein the pulse time of the zirconium source and the water source is controlled to regulate the oxygen vacancy content so as to ensure that the zirconium oxide ZrO2The film contains positively charged oxygen vacancies 4. GeO will be formed during the growth process2As the insulating interface layer 2.
Step 3, adopting a radio frequency reaction magnetron sputtering device to perform reaction on the zirconium oxide ZrO2100 nm tantalum nitride TaN is deposited as the gate metal on the gate dielectric 2, as shown in (b) of fig. 2.
And 4, defining a grid electrode graph and a source-drain region.
Photoetching the surface of TaN to define a gate electrode pattern, etching to form a gate electrode 5 and a source/drain region, and BF2 +Ion implantation with an implantation energy of 30 KeV and an implantation dose of 1 × 1015 cm-2。
Step 5, performing photolithography on the surface of the structure shown in (c) in fig. 2 to define a region where metal nickel needs to be deposited, depositing Ni with a thickness of 20 nm, and performing a stripping process in an acetone solution to form a source electrode 6 and a drain electrode 7, as shown in (d) in fig. 2.
Step 6, the whole prepared device is processed at 400 oCAnd annealing and activating under the condition of 30s to prepare the field effect transistor.
Example 2
Based on amorphous Al with positively charged oxygen vacancies2O3The transistor of the gate dielectric has the function of mutual conversion between the logic device and the storage device, and the manufacturing steps of the transistor are as follows;
step 1, selecting a substrate and cleaning.
In the embodiment, an n-type germanium sheet Ge is selected as a substrate 1, and the substrate is cleaned conventionally.
Step 2, depositing amorphous Al2O3A film.
Deposition of 5 nm of aluminum oxide Al on a substrate 1 with a plasma enhanced atomic layer deposition PEALD apparatus2O3As the gate dielectric layer 3, the deposition process conditions are as follows: trimethylaluminum is used as an aluminum source of a precursor, water is used as an oxygen source of the precursor, and the deposition temperature is 300 ℃. Wherein, the pulse time of the aluminum source and the water source is controlled to regulate and control the content of oxygen vacancy, so that the aluminum oxide Al is obtained2The O film contains positively charged oxygen vacancies. GeO will be formed during the growth process2As the insulating interface layer 2.
Step 3, adopting radio frequency reaction magnetron sputtering equipment to perform reaction on the alumina Al2O3100 nm titanium nitride TiN is deposited on the gate dielectric 3 to be used as gate metal.
And 4, defining a gate electrode graph and a source-drain region.
Firstly, photoetching and defining gate electrode pattern on the surface of titanium nitride TiNEtching to form gate electrode 5 and source/drain region, and BF2 +Ion implantation with an implantation energy of 30 KeV and an implantation dose of 1 × 1015 cm-2。
And 5, defining an area needing to be deposited with metal nickel by utilizing photoetching, depositing nickel Ni with the thickness of 20 nm, and putting the nickel Ni into an acetone solution for stripping treatment to form a source electrode 6 and a drain electrode 7.
Step 6, the whole manufactured device is processed at 400 oCAnd annealing and activating under the condition of 30s to prepare the field effect transistor.
Example 3
Amorphous La based on oxygen vacancies with positive charge2O3The transistor of the gate dielectric has the function of mutual conversion between the logic device and the storage device, and the manufacturing steps of the transistor are as follows;
step 1, selecting a substrate and cleaning.
In this embodiment, an n-type silicon wafer Si is selected as the substrate 1, and the substrate is conventionally cleaned.
And 2, photoetching and defining a source-drain region, and performing ion implantation.
P ions are implanted into the source and drain regions with the dosage of 1 × 1015 cm-2Activation condition is 1000oC, 1 minute.
Step 2, depositing amorphous lanthanum oxide La2O3A film.
Deposition of 15 nm lanthanum oxide La on a substrate 1 with plasma enhanced atomic layer deposition PEALD apparatus2O3As the gate dielectric layer 3, the deposition process conditions are as follows: using La (iPrCp)3As a precursor lanthanum source, water is used as a precursor oxygen source, and the deposition temperature is 150 DEGoC. Wherein, the pulse time of the lanthanum source and the water source is controlled to regulate and control the content of oxygen vacancy, so that the lanthanum oxide La is2O3The film contains positively charged oxygen vacancies. SiO will be formed in the process of growing simultaneously2As the insulating interface layer 2.
Step 3, adopting radio frequency reaction magnetron sputtering equipment to be arranged in La2O3100 nm titanium nitride TiN is deposited on the gate dielectric 2 to be used as gate metal. And then at 400 oC ，Annealing treatment after metallization was performed for 30 seconds.
And 4, defining a gate electrode pattern.
And photoetching the surface of the titanium nitride TiN to define a gate electrode pattern.
And 5, defining a region needing to deposit metal Al by utilizing photoetching, depositing Al with the thickness of 20 nm, and putting the Al into an acetone solution for stripping treatment to form a source electrode 6 and a drain electrode 7.
Step 6, the whole manufactured device is processed at 400 oCAnd annealing and activating under the condition of 30s to prepare the field effect transistor.
In the embodiment of the invention, when the oxygen vacancy with positive charge is in a trapped state, the field effect transistor shows a logic characteristic, and after a certain low-frequency pulse (the frequency is 1Hz-100 Hz) is applied to the gate electrode 5, the oxygen vacancy is in a de-trapped state, and a device showing the logic characteristic can be converted into a storage device.
In the embodiment of the present invention, when the positively charged oxygen vacancy is in a detrapping state, the field effect transistor exhibits a memory characteristic, and after a certain high frequency pulse (frequency of 1kHz or more) is applied to the gate electrode 5, the oxygen vacancy is in a trapped state, and a device exhibiting the memory characteristic can be converted into a logic device. The field effect transistor can thereby realize a function of converting the logic characteristic and the memory characteristic to each other.
Example 4: testing the interchange performance of logic characteristic and memory characteristic of field effect transistor
When the transistor obtained in example 1 was tested, the field effect transistor having positively charged oxygen vacancies exhibited the memory characteristics, the transfer characteristics thereof are shown in FIG. 3, and after a 1kHz high frequency pulse was applied to the gate electrode, the transfer characteristics thereof are shown in FIG. 4, and since the positively charged oxygen vacancies were neutralized by interface traps, the device exhibited almost zero hysteresis and had the logic characteristics. On the basis of this device exhibiting logic characteristics, a 10Hz low frequency pulse is applied to the gate electrode, and the transfer characteristics thereof are shown in fig. 5, and since the positively charged oxygen vacancies are in a detrapping state, the device exhibits upward-returning ferroelectric-like hysteresis, having memory characteristics. Both the logic characteristics and the memory characteristics of the device can be stable.
It should be noted that the embodiment of the present invention further provides a chip with a storage function, where the chip with a storage function may include a chip main body and the field effect transistor with a function of interconversion between a logic device and a memory device in the foregoing embodiment, where the field effect transistor is disposed on the chip main body.
The integrated storage and calculation chip can be a three-dimensional heterogeneous integrated storage and calculation chip or other types of integrated storage and calculation chips.
The embodiment of the invention also provides a storage and calculation integrated circuit, which can comprise a circuit board main body and the storage and calculation integrated chip in the embodiment, wherein the storage and calculation integrated chip is arranged on the circuit board main body.
The embodiment of the present invention further provides a storage and computation integrated device, which may include a housing and the storage and computation integrated circuit in the above embodiment, where the storage and computation integrated circuit is disposed on the housing.
The foregoing description is only two specific examples of the present invention and is not intended to limit the present invention in any way, and it will be apparent to those skilled in the art that various modifications and variations in form and detail can be made without departing from the principle and structure of the invention after understanding the present disclosure and principles, but such modifications and variations are within the scope of the appended claims.

Claims (10)

1. A field effect transistor having a function of mutually converting a logic characteristic and a memory characteristic, comprising: the transistor comprises a substrate (1), an insulating interface layer (2), a gate dielectric layer (3), positively charged oxygen vacancies (4), a gate electrode (5), a source electrode (6) and a drain electrode (7); the insulating interface layer (2), the gate dielectric layer (3) and the gate electrode (5) are vertically distributed on the upper surface of the substrate (1) from bottom to top; the source electrode (6) and the drain electrode (7) are respectively arranged on two sides of the upper surface of the substrate (1), and the insulating interface layer (2) is arranged between the source electrode (6) and the drain electrode (7);
the gate dielectric layer (3) is internally provided with the positively charged oxygen vacancies (4), the positively charged oxygen vacancies (4) are mobile ions, wherein the positively charged oxygen vacancies (4) are switchable between a first state and a second state, so that the field effect transistor is correspondingly switched between a function of being used as a logic device and a function of being used as a memory device;
the first state is: the positively charged oxygen vacancies (4) are trapped and neutralized by the interface of the insulating interfacial layer (2) and/or the interface of the gate electrode (5);
the second state is: the positively charged oxygen vacancies (4) are in a de-trapped state.
2. The field effect transistor having a function of interconversion between logic characteristics and memory characteristics as claimed in claim 1, wherein said positively charged oxygen vacancies (4) are in said first state when said gate electrode (5) is applied with a high frequency pulse, so that said field effect transistor has logic characteristics and can be used as a logic device;
when the gate electrode (5) is applied with a low frequency pulse, the positively charged oxygen vacancies (4) are in the second state, so that the field effect transistor has memory characteristics and can be used as a memory device.
3. The field effect transistor having a function of interconversion between logic characteristics and memory characteristics as claimed in claim 2, wherein a frequency of the high-frequency pulse is greater than or equal to 1 kHz; and/or
The frequency of the low frequency pulses is less than or equal to 10 Hz.
4. The FET having a function of interconversion between logic characteristics and memory characteristics as claimed in claim 1, wherein said insulating interface layer (2) comprises a silicon oxide material SiO2Silicon nitride material Si3N4SiON, Ge oxide, and SiON materialsMaterial GeO2And alumina material Al2O3One kind of (1).
5. The field effect transistor having a function of interconversion between logic characteristics and memory characteristics as claimed in claim 1, wherein said substrate (1) is a semiconductor material; the gate dielectric layer (3) is an insulating oxide; the gate electrode (5) is a nitride metal.
6. The FET of claim 5, wherein the semiconductor material comprises one of Si, Ge, SiGe, SOI or GOI.
7. The field effect transistor having a function of mutually converting logic characteristics and memory characteristics as defined in claim 5, wherein said insulating oxide comprises hafnium oxide (HfO)2Zirconium oxide ZrO2Aluminum oxide Al2O3La, lanthanum oxide2O3Yttrium oxide Y2O3Titanium oxide TiO2Silicon oxide SiO2And germanium oxide GeO2One of (1); the nitride metal comprises one of tantalum nitride TaN, titanium nitride TiN, molybdenum nitride MoN and tungsten nitride WN.
8. A memory-integrated chip comprising a chip body and the field-effect transistor having a function of mutually converting a logic characteristic and a memory characteristic according to any one of claims 1 to 7, wherein the field-effect transistor is provided on the chip body.
9. A keep-alive circuit comprising a circuit board body and the keep-alive chip of claim 8, wherein the keep-alive chip is disposed on the circuit board body.
10. A banking apparatus comprising a housing and the banking circuit of claim 9, wherein the banking circuit is disposed on the housing.
CN202210065533.2A 2022-01-20 2022-01-20 Field effect transistor, storage and calculation integrated chip, circuit and equipment Active CN114093935B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202210065533.2A CN114093935B (en) 2022-01-20 2022-01-20 Field effect transistor, storage and calculation integrated chip, circuit and equipment
JP2022577533A JP2024509339A (en) 2022-01-20 2022-05-07 Field effect transistors, compute-in memory chips, circuits and equipment
PCT/CN2022/091334 WO2023137927A1 (en) 2022-01-20 2022-05-07 Field effect transistor, compute-in-memory chip, circuit, and device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210065533.2A CN114093935B (en) 2022-01-20 2022-01-20 Field effect transistor, storage and calculation integrated chip, circuit and equipment

Publications (2)

Publication Number Publication Date
CN114093935A true CN114093935A (en) 2022-02-25
CN114093935B CN114093935B (en) 2022-05-13

Family

ID=80308856

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210065533.2A Active CN114093935B (en) 2022-01-20 2022-01-20 Field effect transistor, storage and calculation integrated chip, circuit and equipment

Country Status (3)

Country Link
JP (1) JP2024509339A (en)
CN (1) CN114093935B (en)
WO (1) WO2023137927A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114639729A (en) * 2022-05-17 2022-06-17 之江实验室 Field effect transistor, low-power consumption CMOS integrated chip, circuit and equipment
CN115113846A (en) * 2022-08-31 2022-09-27 之江实验室 Full adder circuit and multi-bit full adder
CN115425965A (en) * 2022-11-03 2022-12-02 之江实验室 Reconfigurable logic gate circuit and control method thereof
CN116190426A (en) * 2023-04-23 2023-05-30 之江实验室 Nanosheet transistor and reconstruction and preparation method thereof
WO2023137927A1 (en) * 2022-01-20 2023-07-27 之江实验室 Field effect transistor, compute-in-memory chip, circuit, and device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1941415A (en) * 2005-09-01 2007-04-04 台湾积体电路制造股份有限公司 Semiconductor element
CN101226882A (en) * 2006-12-12 2008-07-23 旺宏电子股份有限公司 Methods for manufacturing memory and logic devices using the same process without the need for additional masks
KR20100010805A (en) * 2008-07-23 2010-02-02 주식회사 하이닉스반도체 Charge trap type non-volatile memory device and method for fabricating the same
US20160056246A1 (en) * 2014-08-22 2016-02-25 SK Hynix Inc. Electronic device
US20180122491A1 (en) * 2016-10-28 2018-05-03 International Business Machines Corporation Three terminal fuse structure created by oxygen vacancy traps in hafnium-based oxides
CN109920848A (en) * 2019-03-18 2019-06-21 西安电子科技大学 ZrO without boundary layer2Based antiferroelectric memory
CN113782607A (en) * 2021-08-25 2021-12-10 中国科学院微电子研究所 Ferroelectric field effect transistor, preparation method thereof and ferroelectric memory device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6258651B1 (en) * 1999-12-21 2001-07-10 United Microelectronics Corp. Method for forming an embedded memory and a logic circuit on a single substrate
CN114093935B (en) * 2022-01-20 2022-05-13 之江实验室 Field effect transistor, storage and calculation integrated chip, circuit and equipment

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1941415A (en) * 2005-09-01 2007-04-04 台湾积体电路制造股份有限公司 Semiconductor element
CN101226882A (en) * 2006-12-12 2008-07-23 旺宏电子股份有限公司 Methods for manufacturing memory and logic devices using the same process without the need for additional masks
KR20100010805A (en) * 2008-07-23 2010-02-02 주식회사 하이닉스반도체 Charge trap type non-volatile memory device and method for fabricating the same
US20160056246A1 (en) * 2014-08-22 2016-02-25 SK Hynix Inc. Electronic device
US20180122491A1 (en) * 2016-10-28 2018-05-03 International Business Machines Corporation Three terminal fuse structure created by oxygen vacancy traps in hafnium-based oxides
CN109920848A (en) * 2019-03-18 2019-06-21 西安电子科技大学 ZrO without boundary layer2Based antiferroelectric memory
CN113782607A (en) * 2021-08-25 2021-12-10 中国科学院微电子研究所 Ferroelectric field effect transistor, preparation method thereof and ferroelectric memory device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Y. PENG ET AL.: "Non-Volatile Field-Effect Transistors Enabled by Oxygen Vacancy-Related Dipoles for Memory and Synapse Applications", 《IEEE TRANSACTIONS ON ELECTRON DEVICES》 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023137927A1 (en) * 2022-01-20 2023-07-27 之江实验室 Field effect transistor, compute-in-memory chip, circuit, and device
CN114639729A (en) * 2022-05-17 2022-06-17 之江实验室 Field effect transistor, low-power consumption CMOS integrated chip, circuit and equipment
CN115113846A (en) * 2022-08-31 2022-09-27 之江实验室 Full adder circuit and multi-bit full adder
CN115425965A (en) * 2022-11-03 2022-12-02 之江实验室 Reconfigurable logic gate circuit and control method thereof
CN115425965B (en) * 2022-11-03 2023-02-17 之江实验室 Reconfigurable logic gate circuit and control method thereof
CN116190426A (en) * 2023-04-23 2023-05-30 之江实验室 Nanosheet transistor and reconstruction and preparation method thereof

Also Published As

Publication number Publication date
JP2024509339A (en) 2024-03-01
CN114093935B (en) 2022-05-13
WO2023137927A1 (en) 2023-07-27

Similar Documents

Publication Publication Date Title
CN114093935B (en) Field effect transistor, storage and calculation integrated chip, circuit and equipment
TWI298929B (en) Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure
TWI250639B (en) Self-aligned planar double-gate process by amorphization
CN112038406B (en) Two-dimensional material double-gate memory integrated device with ferroelectric medium and preparation method thereof
TWI260730B (en) Semiconductor device substrate with embedded capacitor
CN101213666A (en) A semiconductor device including a vertical decoupling capacitor
US11837661B2 (en) Sidewall spacer structure to increase switching performance of ferroelectric memory device
JPH04176167A (en) Manufacture of semiconductor memory device
SG183452A1 (en) Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures
JP3664467B2 (en) Manufacturing method of single transistor ferroelectric memory cell using chemical mechanical polishing
TW202042347A (en) Ferroelectric memory device, integrated chip, and method for forming ferroelectric memory device
US9236384B2 (en) Semiconductor memory device and method for accessing the same
CN109904162A (en) A kind of ferroelectric storage unit and its manufacturing method
WO2021037335A1 (en) A negative quantum capacitance field effect transistor
US7276765B2 (en) Buried transistors for silicon on insulator technology
TW202040754A (en) Method of forming the integrated chip
CN114664940A (en) Movable ion film, ferroelectric field effect transistor, capacitor and preparation method
CN109698165A (en) Semiconductor device and the method for gate structure is provided for its multiple components
CN115996578A (en) Semiconductor device and method for manufacturing the same
CN114639729B (en) Field effect transistor, low-power consumption CMOS integrated chip, circuit and equipment
JP3916049B2 (en) Method for manufacturing ferroelectric memory transistor
CN114551599A (en) Ferroelectric transistor device with reconfigurable logic and memory functions and preparation method thereof
CN111900149A (en) Capacitor and preparation method thereof
CN115763480A (en) Low-power-consumption CMOS circuit based on ultra-high mobility field effect transistor
CN116722862A (en) NOT/NOR/NAND logic gate reconfigurable circuit, memory integrated chip and equipment

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant