CN114093820A - Method for preparing active region structure, semiconductor structure and semiconductor memory - Google Patents
Method for preparing active region structure, semiconductor structure and semiconductor memory Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 107
- 238000000034 method Methods 0.000 title claims abstract description 100
- 238000005530 etching Methods 0.000 claims abstract description 132
- 230000004888 barrier function Effects 0.000 claims abstract description 131
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000000151 deposition Methods 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 238000005520 cutting process Methods 0.000 claims description 10
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- 238000010586 diagram Methods 0.000 description 23
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- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000003384 imaging method Methods 0.000 description 3
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- 239000003990 capacitor Substances 0.000 description 2
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
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- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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Abstract
本申请提供了一种有源区结构的制备方法、半导体结构和半导体存储器，所述方法包括：提供衬底；在衬底表面形成初始半导体结构；初始半导体结构包括有源线；在初始半导体结构上沉积第一阻挡层；刻蚀第一阻挡层，形成沿第一方向延伸的第一沟槽；刻蚀第一阻挡层，形成沿第二方向延伸的第二沟槽；第一沟槽与第二沟槽交叠区域形成刻蚀孔，刻蚀孔的深度大于第一沟槽与第二沟槽的深度；以刻蚀孔为掩膜，刻蚀有源线，形成分立的有源区掩膜。本申请能够提高有源区的局部关键尺寸均匀性，改善半导体器件的电性能。
The present application provides a method for preparing an active region structure, a semiconductor structure and a semiconductor memory, the method comprising: providing a substrate; forming an initial semiconductor structure on the surface of the substrate; the initial semiconductor structure includes active lines; depositing a first barrier layer on top; etching the first barrier layer to form a first trench extending along the first direction; etching the first barrier layer to form a second trench extending along the second direction; the first trench and An etching hole is formed in the overlapping area of the second trench, and the depth of the etching hole is greater than that of the first trench and the second trench; the active line is etched using the etching hole as a mask to form discrete active regions mask. The present application can improve the local critical dimension uniformity of the active region and improve the electrical performance of the semiconductor device.
Description
Technical Field
The present disclosure relates to the field of semiconductor processes, and in particular, to a method for manufacturing an active region structure, a semiconductor structure, and a semiconductor memory.
Background
With the continuous development of semiconductor technology, the feature size of semiconductor devices in integrated circuits, including the Critical Dimension (CD) of active regions, is continuously shrinking.
It is often difficult to uniformly distribute active regions with smaller Critical dimensions, and thus, the Local Critical Dimension Uniformity (LCDU) is too low to adversely affect the electrical performance of the semiconductor device.
Disclosure of Invention
The embodiments of the present application are intended to provide a method for manufacturing an active region structure, a semiconductor structure, and a semiconductor memory, which can improve an LCDU of the active region, thereby improving electrical performance of a semiconductor device.
The technical scheme of the application is realized as follows:
the embodiment of the application provides a preparation method of an active region structure, which comprises the following steps:
providing a substrate;
forming an initial semiconductor structure on the surface of the substrate; the initial semiconductor structure comprises an active line;
depositing a first barrier layer on the initial semiconductor structure;
etching the first barrier layer to form a first groove extending along a first direction;
etching the first barrier layer to form a second groove extending along a second direction; forming an etching hole in an overlapped area of the first groove and the second groove, wherein the depth of the etching hole is greater than that of the first groove and the second groove;
and etching the active line by taking the etching hole as a mask to form a discrete active area mask.
The embodiment of the present application further provides a semiconductor structure, which includes an active region structure; the active region structure is prepared by the preparation method in the scheme.
The embodiment of the application also provides a semiconductor memory, which comprises the semiconductor structure in the scheme.
Therefore, the embodiment of the application provides a preparation method of an active region structure, a semiconductor structure and a semiconductor memory, and an initial semiconductor structure comprising an active line can be formed on the surface of a substrate; then, depositing a first barrier layer on the initial semiconductor structure; then, etching the first barrier layer, and sequentially forming a first groove extending along the first direction and a second groove extending along the second direction, wherein an etching hole is formed in an overlapped area of the first groove and the second groove, and the depth of the etching hole is greater than that of the first groove and the second groove; and then, etching the active line by taking the etching hole as a mask to form a discrete active area mask. Due to the diffraction effect of light, the precision of a Mask (Mask) is limited, and the active region LCDU formed by the traditional process is lower. According to the embodiment of the application, the active area mask is formed through a new process method, so that the structural problem caused by unclear photomask imaging in the traditional process is avoided, the LCDU of the active area can be improved, and the electrical property of a semiconductor device is improved.
Drawings
Fig. 1 is a first flowchart of a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 2A is a first schematic view illustrating a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 2B is a second schematic diagram illustrating a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 3 is a third schematic view illustrating a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 4A is a fourth schematic view illustrating a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 4B is a fifth schematic view illustrating a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 5A is a sixth schematic view of a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 5B is a seventh schematic diagram illustrating a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 6A is an eighth schematic view illustrating a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 6B is a ninth schematic view illustrating a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 7 is a second flowchart of a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 8A is a schematic diagram ten illustrating a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 8B is an eleventh schematic view illustrating a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 9A is a twelfth schematic view of a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 9B is a thirteenth schematic diagram illustrating a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 10A is a fourteenth schematic diagram illustrating a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 10B is a schematic diagram fifteen illustrating a method for fabricating an active region structure according to an embodiment of the present application;
fig. 11A is a sixteenth schematic diagram illustrating a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 11B is a seventeenth schematic diagram illustrating a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 12A is a schematic diagram eighteen of a method for manufacturing an active region structure according to an embodiment of the present disclosure;
fig. 12B is a nineteen schematic diagram illustrating a method for manufacturing an active region structure according to an embodiment of the present application;
fig. 13A is a schematic view of a twenty-first embodiment of a method for fabricating an active region structure;
fig. 13B is a twenty-first schematic diagram of a method for manufacturing an active region structure according to an embodiment of the present disclosure;
fig. 14 is a third flowchart of a method for manufacturing an active region structure according to an embodiment of the present disclosure;
fig. 15A is a twenty-two schematic diagram illustrating a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 15B is a schematic diagram of twenty-three illustrating a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 16A is a schematic twenty-four of a method for fabricating an active region structure according to an embodiment of the present application;
fig. 16B is a schematic diagram of twenty-five illustrating a method for manufacturing an active region structure according to an embodiment of the present disclosure;
fig. 17A is a twenty-sixth schematic view of a method for manufacturing an active region structure according to an embodiment of the present disclosure;
fig. 17B is a twenty-seventh schematic diagram of a method for manufacturing an active region structure according to an embodiment of the present application;
fig. 18A is a schematic diagram of a twenty-eighth method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 18B is a twenty-ninth schematic view of a method for manufacturing an active region structure according to an embodiment of the present disclosure;
fig. 19A is a schematic diagram thirty illustrating a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 19B is a thirty-one schematic diagram of a method for fabricating an active region structure according to an embodiment of the present application;
fig. 20A is a thirty-two schematic diagram of a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 20B is a schematic thirty-three illustration showing a method for fabricating an active region structure according to an embodiment of the present application;
fig. 21 is a fourth flowchart of a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 22A is a schematic thirty-four of a method for fabricating an active region structure according to an embodiment of the present application;
fig. 22B is a schematic thirty-five view illustrating a method for fabricating an active region structure according to an embodiment of the present application;
fig. 23A is a thirty-six schematic diagram of a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 23B is a thirty-seventh schematic diagram illustrating a method for fabricating an active region structure according to an embodiment of the present disclosure;
fig. 24A is a schematic view thirty-eight of a method for fabricating an active region structure according to an embodiment of the present application;
fig. 24B is a thirty-nine schematic diagram of a method for fabricating an active region structure according to an embodiment of the present application;
fig. 25 is a schematic structural diagram of a semiconductor memory according to an embodiment of the present application.
Detailed Description
In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions of the present application are further described in detail with reference to the drawings and the embodiments, the described embodiments should not be considered as limiting the present application, and all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present application.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.
Where a similar description of "first/second" appears in the specification, and the description below is added where the terms "first/second/third" are used merely to distinguish between similar objects and do not denote a particular order or importance to the objects, it will be appreciated that "first/second/third" may, where permissible, be interchanged in a particular order or sequence to enable embodiments of the application described herein to be practiced in other than the order shown or described herein.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the application.
Dynamic Random Access Memory (DRAM) is a semiconductor element commonly used in electronic devices such as computers, and is composed of a plurality of Memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected with a word line, the source of the transistor is electrically connected with a bit line, and the drain of the transistor is electrically connected with the capacitor.
In a semiconductor device such as a DRAM, a plurality of active regions are arranged in an array. However, with the shrinking of the structure size of the semiconductor device, especially in the process of manufacturing the DRAM with the critical dimension smaller than 15nm, the size of the active region becomes smaller, and the traditional scheme of the dual Lithography pattern (LELE) has a certain limitation, and cannot meet the requirement of the manufacturing process.
Fig. 1 is a schematic flow chart of an alternative method for manufacturing an active region structure according to an embodiment of the present application, which will be described with reference to the steps shown in fig. 1.
S101, forming an initial semiconductor structure on the surface of a substrate; the initial semiconductor structure includes an active line.
In an embodiment of the present application, a semiconductor device may form an initial semiconductor structure on a surface of a substrate, wherein the initial semiconductor structure includes an active line. Fig. 2A and 2B illustrate an initial semiconductor structure, front-view and top-view respectively, as shown in fig. 2A and 2B, on a substrate 10, a plurality of active lines 101 are formed in a parallel arrangement. Wherein the material of the substrate may be monocrystalline silicon, and the material of the active line 101 may be polycrystalline silicon.
In the embodiment of the present application, the semiconductor device may first form the initial mandrels with wider intervals through a photolithography process, and the initial mask layer extends along the extending direction of the active lines in fig. 2B; then, forming initial side walls on two sides of the initial mandrel; and finally, etching to form the active line 101 by taking the initial side wall as a mask. Because the initial side walls are formed in the interval areas of the initial mandrels, and the space between the initial side walls is smaller than that between the initial mandrels, the size of the active lines formed by etching is smaller than that of the initial mandrels, namely, the active lines with smaller sizes are formed by using the photomask with larger sizes.
It should be noted that, since the width and the pitch of the active lines 101 formed in the embodiment of the present application are very small, it is difficult to ensure the LCDU of the finally formed active region by using the conventional scheme.
And S102, depositing a first barrier layer on the initial semiconductor structure.
In embodiments of the present application, a semiconductor device may deposit a first barrier layer on an initial semiconductor structure in preparation for a subsequent process. It should be noted that the barrier layer is used to form a pattern (pattern) that is transferred downward as needed, and to protect the region that does not need to be etched during etching.
Fig. 3 illustrates a front cross-sectional view of a first barrier layer, as shown in fig. 3, a first barrier layer 20 is deposited on the substrate 10 and covers the active line 101. The first barrier layer 20 may include a first silicon oxynitride (SiON) layer 201 and a first spin-on hard mask (SOH) layer 202, among others.
S103, etching the first barrier layer to form a first groove extending along the first direction.
In an embodiment of the present application, a semiconductor device may be etched on a first barrier layer to form a first trench extending in a first direction. Fig. 4A and 4B illustrate a first trench, which is a front sectional view and a top view, respectively, as shown in fig. 4A and 4B, a first trench 2011 is formed on the first silicon oxynitride layer 201, and the depth of the first trench 2011 is smaller than the thickness of the first silicon oxynitride layer 201; the first direction D1 along which the first trench 2011 extends is shown in fig. 4B, i.e., the direction of the oblique lines on the silicon oxynitride layer 201 in fig. 4B.
In the embodiment of the present application, the semiconductor apparatus may first form the first mandrels with wider intervals by a photolithography process, as shown in fig. 9A and 9B, the first mandrels 401 extend along the first direction D1. Then, first side walls may be formed on both sides of the first mandrel, as shown in fig. 11A and 11B, the first side walls 403 cover both sides of the first mandrel 401, and the first side walls 403 also extend along the first direction D1. Finally, the first sidewall is used as a mask to etch and form a first trench 2011. Since the first sidewalls 403 are formed in the spaced areas of the first mandrels 401, and the spacing between the first mandrels 401 is smaller than that between the first mandrels 401, the size of the first trenches 2011 formed by etching is smaller than that of the first mandrels 401, that is, the first trenches with smaller size are formed by using a photomask with larger size.
S104, etching the first barrier layer to form a second groove extending along a second direction; and an etching hole is formed in the overlapped area of the first groove and the second groove, and the depth of the etching hole is greater than that of the first groove and the second groove.
In the embodiment of the application, the semiconductor device may etch and form the second trench extending along the second direction on the first barrier layer. And an etching hole is formed in the overlapped area of the first groove and the second groove, and the depth of the etching hole is greater than that of the first groove and the second groove. Fig. 5A and 5B illustrate a second trench and an etch hole, respectively in front cross-section and top view, as shown in fig. 5A and 5B, a second trench 2012 is formed in the first silicon oxynitride layer 201. The first trench 2011 extends along the first direction D1, the second trench 2012 extends along the second direction D2, and the overlapping region of the first trench 2011 and the second trench 2012 forms a diamond-shaped etching hole 2013 (i.e., a dark portion in fig. 5B). The depth of the etching hole 2013 is greater than the depth of the first trench 2011 and the depth of the second trench 2012.
In the embodiment of the present application, the semiconductor apparatus may first form the second mandrels with wider intervals through a photolithography process, as shown in fig. 16A and 16B, and the second mandrels 701 extend in the second direction D2. Then, second side walls may be formed on both sides of the second mandrel, as shown in fig. 18A and 18B, the second side walls 703 cover both sides of the second mandrel 701, and the second side walls 703 also extend along the second direction D2. And finally, etching to form a second groove 2012 by taking the second side wall as a mask. Since the second side walls 703 are formed in the spaced areas of the second mandrels 701, and the spacing between the second side walls is smaller than that between the second mandrels 701, the size of the second trenches 2012 formed by etching is smaller than that of the second mandrels 701, that is, the second trenches with smaller size are formed by using a photomask with larger size.
And S105, etching the active line by taking the etching hole as a mask to form a discrete active area mask.
In the embodiment of the application, the semiconductor device can etch the active line by taking the etching hole as a mask to form a discrete active area mask. It should be noted that etching is performed using a certain structure as a mask, that is, the pattern of the structure is transferred to the structure below the structure.
In the embodiment of the application, the position of the etching hole corresponds to a cutting point on the active line. Because the etching hole is sunken downwards, and the sunken depth is greater than other areas, therefore, in the etching, the cutting point on the active line can be etched first, and other areas on the active line are protected by the covered mask, so that the active line can be cut off at the cutting point, and a discrete active area mask is formed.
Fig. 6A and 6B illustrate a discrete active area mask, front cross-sectional view and top view, respectively, in conjunction with fig. 2A, 2B, 6A, and 6B, the active line 101 of fig. 2A and 2B, forming the discrete active area mask 102 of fig. 6A and 6B after each cut point 103 of fig. 6B is cut.
It can be understood that, in the embodiment of the present application, a plurality of active lines arranged in parallel are formed first; then, depositing a first barrier layer on the active line, and respectively etching the surface of the first barrier layer to form a first groove and a second groove so as to form an etching hole; finally, the active lines are cut into separate active area masks along the positions of the etching holes. Therefore, the active region is formed by the novel process method, the structural problem caused by unclear photomask imaging in the traditional process is avoided, the LCDU of the active region can be improved, and the electrical property of the semiconductor device is improved.
In some embodiments of the present application, S103 shown in fig. 1 may be implemented by S201 to S204 shown in fig. 7, and will be described with reference to each step.
S201, depositing a second barrier layer and a third barrier layer on the first barrier layer in sequence.
In an embodiment of the present application, a semiconductor device may sequentially deposit a second barrier layer and a third barrier layer on a first barrier layer. It should be noted that the barrier layer is used to form a pattern transferred downward as required, and to protect an area not required to be etched during etching. As shown in fig. 8A, a second barrier layer 30 and a third barrier layer 40 are sequentially deposited on the first barrier layer 20. The materials of the second barrier layer 30 and the third barrier layer 40 may include: SiON and SOH.
S202, etching the third barrier layer to form a first mandrel extending along the first direction; the first mandrels are arranged at intervals.
In an embodiment of the application, the semiconductor device may etch the third barrier layer to form first mandrels extending along the first direction, wherein the first mandrels are arranged at intervals.
In the embodiment of the present application, as shown in fig. 8A and 8B, the semiconductor apparatus may first form the first mask 50 on the third barrier layer 40 through a photolithography process, and the shape of the first mask 50 is characterized by the first etching pattern extending along the first direction D1. Then, the semiconductor apparatus may etch the third barrier layer 40 along the first etch pattern to form the first mandrel 401 shown in fig. 9A and 9B. The first mandrels 401 extend in the first direction D1 and are spaced apart.
And S203, forming a first side wall by covering the side surface of the first mandrel.
In the embodiment of the application, the semiconductor device may cover the side surface of the first mandrel to form the first sidewall.
In the embodiment, as shown in fig. 10A and 10B, the semiconductor device may first deposit a first hard mask Layer 402 by using an AL D (Atomic Layer Deposition) process to cover the second barrier Layer 30 and the first mandrel 401. Then, the semiconductor apparatus may etch back the first hard mask layer 402, removing the top of the first hard mask layer 402 until the first mandrel 401 is exposed, leaving the side portions of the first hard mask layer 402 as first sidewalls 403, as shown in fig. 11A and 11B. The first side walls 403 also extend in the first direction D1.
And S204, etching by taking the first side wall as a mask, removing the second barrier layer, and etching the first barrier layer to form a first groove extending along the first direction.
In the embodiment of the application, the semiconductor device can be etched by using the first side wall as a mask, the second barrier layer is removed, and the first barrier layer is etched to form the first groove extending along the first direction.
In the embodiment of the present application, referring to fig. 11A and 11B, a first mandrel 401 remains in the middle of the first sidewall 403. The semiconductor device may first perform etching using an etching rate with a high selectivity ratio to remove the remaining first mandrels 401 in the middle of the first sidewalls 403, where the high selectivity ratio means that the etching rate of the material of the first mandrels 401 is much greater than that of other materials, and the obtained structure is as shown in fig. 12A and 12B. Then, referring to fig. 12A and 13A, the semiconductor device can etch the second barrier layer 30 using the first sidewall 403 as a mask, thereby forming the first intermediate structure 301 shown in fig. 13A. As shown in fig. 13B, the first intermediate structure 301 extends in the first direction D1 as does the first side wall 403. Then, referring to fig. 13A and 4A, the semiconductor apparatus can etch the first barrier layer 20 using the first intermediate structure 301 as a mask, remove the first intermediate structure 301, and etch the first trench 201 in fig. 4A on the surface of the first barrier layer 20.
It is understood that, in the embodiment of the present application, after the second barrier layer 30 and the third barrier layer 40 are deposited, the semiconductor device first forms the first mask 50 through a photolithography process, and forms the first mandrel 401 by etching along the first mask 50; then, a first sidewall 403 is formed covering the side of the first mandrel 401; finally, the first sidewall 403 is used as a mask to etch and form a first trench 2011. Since the first sidewalls 403 are formed in the spaced regions of the first mandrels 401, the spacing therebetween is smaller than the spacing between the first mandrels 401. Therefore, the width of the first trench 2011 formed by using the first sidewall 403 as a mask is smaller than the distance between the first mandrels 401. Thus, even if the photolithography process limits the achievable critical dimension, the first trench 2011 having a smaller critical dimension can be formed by the first mandrel 401, extending the process dimension limit achievable by the semiconductor device.
In some embodiments of the present application, S202 shown in fig. 7 may be implemented by S2021 to S2022, and will be described with reference to each step.
S2021, forming a first mask on the third blocking layer; the first mask includes a first etch pattern extending in a first direction.
In the embodiment of the application, the semiconductor device may first form a first mask on the third barrier layer; wherein the first mask may be obtained by a lithographic process comprising a first etch pattern extending in a first direction. Fig. 8A and 8B illustrate the first mask, front cross-sectional view and top view, respectively, as shown in fig. 8A and 8B, with the first mask 50 formed on the third barrier layer 40, and the first etch pattern of the first mask 50 extending in the first direction D1.
S2022, etching the third barrier layer along the first etching pattern to form a first mandrel extending along the first direction.
In the embodiment of the present application, after the semiconductor device forms the first mask 50, the third barrier layer 40 may be etched along the first etching pattern to form the first mandrel 401 shown in fig. 9A and 9B; the first mandrels 401 also extend in the first direction D1 and are spaced apart.
In some embodiments of the present application, S203 shown in fig. 7 may be implemented by S2031 to S2032, which will be described with reference to the steps.
S2031, depositing a first hard mask layer; the first hard mask layer covers the second barrier layer and the first mandrel.
In the embodiment of the present application, as shown in fig. 10A and 10B, the semiconductor device may first deposit a first hard mask layer 402 by using an ALD process to cover the second barrier layer 30 and the first mandrel 401.
S2032, etching back the first hard mask layer, removing the top of the first hard mask layer until the first mandrel is exposed, and reserving the side part of the first hard mask layer as a first side wall.
In the embodiment of the present application, after the semiconductor device deposits the first hard mask layer 402, the first hard mask layer 402 may be etched back, the top of the first hard mask layer 402 is removed until the first mandrel 401 is exposed, and the side portion of the first hard mask layer 402 is remained as the first sidewall 403, as shown in fig. 11A and 11B.
In some embodiments of the present application, S204 shown in fig. 7 may be implemented by S2041 to S2043, which will be described in conjunction with the respective steps.
S2041, removing the first mandrel in the middle of the first side wall.
In the embodiment of the present application, referring to fig. 11A and 11B, a first mandrel 401 is left in the middle of the first sidewall 403. The semiconductor device may first perform etching using an etching rate with a high selectivity ratio, and remove the remaining first mandrels 401 in the middle of the first sidewalls 403, so that the resulting structure is as shown in fig. 12A and 12B.
S2042, etching the second barrier layer by taking the first side wall as a mask to form a first intermediate structure.
In the embodiment of the present application, referring to fig. 12A and 13A, after removing the remaining first mandrel 401 in the middle of the first sidewall 403, the semiconductor device may etch the second barrier layer 30 by using the first sidewall 403 as a mask, so as to form the first intermediate structure 301 shown in fig. 13A. As shown in fig. 13B, the first intermediate structure 301 extends in a first direction D1.
S2043, with the first intermediate structure as a mask, etching the first barrier layer to form a first trench extending along the first direction.
In the embodiment of the present application, with reference to fig. 13A and fig. 4A, after the semiconductor device forms the first intermediate structure 301 shown in fig. 13A, the first barrier layer 20 may be etched using the first intermediate structure 301 as a mask to form the first trench 201 shown in fig. 4A; the first trenches 201 extend in a first direction D1.
In some embodiments of the present application, S104 shown in fig. 1 may be implemented by S301 to S304 shown in fig. 14, which will be described in conjunction with the respective steps.
S301, sequentially depositing a fourth barrier layer and a fifth barrier layer on the first barrier layer; the fourth barrier layer covers the first trench.
In an embodiment of the present application, after forming the first trench, the semiconductor device may sequentially deposit a fourth barrier layer and a fifth barrier layer on the first barrier layer. It should be noted that the barrier layer is used to form a pattern transferred downward as required, and to protect an area not required to be etched during etching. As shown in fig. 15A, a fourth barrier layer 60 and a fifth barrier layer 70 are sequentially deposited on the first barrier layer 20, and the fourth barrier layer 60 covers the first trench 2011. The materials of the fourth barrier layer 60 and the fifth barrier layer 70 include: SiON and SOH.
S302, etching the fifth barrier layer to form a second mandrel extending along the second direction; the second mandrels are arranged at intervals.
In this embodiment, the semiconductor device may etch the fifth barrier layer to form second mandrels extending along the second direction, wherein the second mandrels are spaced apart from each other.
In the embodiment of the present application, as shown in fig. 15A and 15B, the semiconductor apparatus may first form the second mask 80 on the fifth barrier layer 70 through a photolithography process, and the shape of the second mask 80 is characterized by the second etching pattern extending along the second direction D2. Then, the semiconductor apparatus may etch the fifth barrier layer 70 along the second etch pattern to form a second mandrel 701 shown in fig. 16A and 16B; the second mandrels 701 extend in the second direction D2 and are spaced apart.
And S303, covering the side surface of the second mandrel to form a second side wall.
In the embodiment of the present application, the semiconductor device may cover a side surface of the second mandrel to form the second sidewall.
In the embodiment of the present application, as shown in fig. 17A and 17B, the semiconductor device may first deposit a second hard mask layer 702 by using an AL D process to cover the fourth barrier layer 60 and the second mandrel 701. Then, the semiconductor apparatus may etch back the second hard mask layer 702, removing the top of the second hard mask layer 702 until the second mandrel 701 is exposed, leaving the side portions of the second hard mask layer 702 as second sidewalls 703, as shown in fig. 18A and 18B. The second side wall 703 also extends in the second direction D2.
And S304, etching is carried out by taking the second side wall as a mask, the fourth barrier layer is removed, and the first barrier layer is etched to form a second groove extending along the second direction.
In the embodiment of the application, the semiconductor device can be etched by using the second side wall as a mask, the fourth barrier layer is removed, and the first barrier layer is etched to form the second groove extending along the second direction.
In the embodiment of the present application, referring to fig. 18A and 18B, a second mandrel 701 remains in the middle of the second sidewall 703. The semiconductor device may first remove the remaining second mandrel 701 in the middle of the second sidewall 703, and the resulting structure is shown in fig. 19A and 19B. Then, referring to fig. 19A and 20A, the semiconductor device can etch the fourth barrier layer 60 using the second sidewall 703 as a mask to form a second intermediate structure 601 as shown in fig. 20A. As shown in fig. 20B, the second intermediate structure 601 extends in the second direction D2 as the second side wall 703. Then, referring to fig. 20A and 5A, the semiconductor apparatus can etch the first barrier layer 20 using the second intermediate structure 601 as a mask, remove the second intermediate structure 601, and etch the second trench 2012 in fig. 5A on the surface of the first barrier layer 20. An etching hole 2013 (i.e., a dark portion in fig. 5B) is formed in an overlapping region of the first trench 2011 and the second trench 2012.
Note that by adjusting the etching rate ratio according to the materials of the first barrier layer 20 and the fourth barrier layer 60, the depth of the etching hole 2013 can be made larger than the depths of the first trench 2011 and the second trench 2012.
It is understood that, in the embodiment of the present application, after the fourth barrier layer 60 and the fifth barrier layer 70 are deposited, the semiconductor device first forms the second mask 80 through a photolithography process, and forms the second mandrel 701 by etching along the second mask 80; then, a second sidewall 703 is formed covering the side of the second mandrel 701; finally, the second sidewall 703 is used as a mask to etch and form a second trench 2012, thereby forming an etching hole 2013. Since the second sidewalls 703 are formed in the spacing regions of the second mandrels 701, the spacing therebetween is smaller than the spacing between the second mandrels 701. Therefore, the width of the second trench 2012 formed by using the second sidewall 703 as a mask is smaller than the distance between the second mandrels 701. In this way, even if the photolithography process limits the achievable critical dimension, the second trench 2012 with a smaller critical dimension can be formed by the second mandrel 701, and then the etching hole 2013 meeting the critical dimension requirement is formed, so as to cut off the active line precisely.
In some embodiments of the present application, S302 shown in fig. 14 may be implemented by S3021 to S3022, which will be described in conjunction with the respective steps.
And S3021, forming a second mask on the fifth barrier layer, wherein the second mask comprises a second etching pattern extending along the second direction.
In the embodiment of the present application, as shown in fig. 15A and 15B, the semiconductor device may first form the second mask 80 on the fifth barrier layer 70 through a photolithography process, and the shape of the second mask 80 is characterized by the second etching pattern extending along the second direction D2.
And S3022, etching the fifth barrier layer along the second etching pattern to form a second mandrel extending along the second direction.
In the embodiment of the present application, after the second mask 80 is formed, the semiconductor apparatus may etch the fifth barrier layer 70 along the second etch pattern to form the second mandrel 701 shown in fig. 16A and 16B; the second mandrels 701 extend in the second direction D2 and are spaced apart.
In some embodiments of the present application, S303 shown in fig. 14 may be implemented by S3031 to S3032, which will be described in conjunction with each step.
S3031, depositing a second hard mask layer; the second hard mask layer covers the fourth barrier layer and the second mandrel.
In the embodiment of the present application, as shown in fig. 17A and 17B, the semiconductor device may first deposit a second hard mask layer 702 by using an ALD process to cover the fourth barrier layer 60 and the second mandrel 701.
S3032, back etching is carried out on the second hard mask layer, the top of the second hard mask layer is removed until the second mandrel is exposed, and the side part of the second hard mask layer is reserved as a second side wall.
In the embodiment of the present application, after depositing the second hard mask layer 702, the semiconductor device may etch back the second hard mask layer 702, remove the top of the second hard mask layer 702 until exposing the second mandrel 701, and leave the side of the second hard mask layer 702 as the second sidewall 703, as shown in fig. 18A and 18B. The second side wall 703 also extends in the second direction D2.
In some embodiments of the present application, S304 illustrated in fig. 14 may be implemented by S3041 to S3043, which will be described with reference to each step.
S3041, removing the second mandrel in the middle of the second sidewall.
In this embodiment of the application, the semiconductor device may first remove the remaining second mandrel 701 in the middle of the second sidewall 703, and the obtained structure is as shown in fig. 19A and 19B.
S3042, etching the fourth barrier layer with the second sidewall as a mask to form a second intermediate structure.
In the embodiment of the present application, after removing the second mandrel 701 remaining in the middle of the second sidewall 703, the semiconductor device may etch the fourth barrier layer 60 using the second sidewall 703 as a mask to form the second intermediate structure 601 shown in fig. 20A and 20B, where the second intermediate structure 601 extends along the second direction D2 as the second sidewall 703.
S3043, etching the first barrier layer with the second intermediate structure as a mask to form a second trench extending along the second direction.
In this embodiment, with reference to fig. 20A and fig. 5A, after forming the second intermediate structure 601, the semiconductor device may etch the first barrier layer 20 by using the second intermediate structure 601 as a mask until the second trench 2012 in fig. 5A is etched on the surface of the first barrier layer 20; the second grooves 2012 extend in the second direction D2. An etching hole 2013 (i.e., a dark portion in fig. 5B) is formed in an overlapping region of the first trench 2011 and the second trench 2012.
In some embodiments of the present application, S105 shown in fig. 1 may be implemented by S1051 to S1502 shown in fig. 21, which will be described in conjunction with the steps.
S1051, etching by taking the etching hole as a mask until a cutting point on the active line; the cut-off point corresponds to the projected location of the etch hole.
In the embodiment of the present application, as shown in fig. 22A and 22B, the semiconductor device may perform etching by using a higher etching selectivity of the first spin-on hard mask 202 than that of the first silicon oxynitride 201, that is, an etching rate of a material of the first spin-on hard mask 202 is greater than that of a material of the first silicon oxynitride 201, so as to penetrate through the first spin-on hard mask 202 only at a projection position corresponding to the etching hole 2013 until a cut-off point on the active line 101. The other regions on the active line 101 are still covered with the first spin-on hard mask 202 and the first silicon oxynitride 201 and protected from the subsequent etching.
And S1052, etching the cutting point, cutting the active line, and forming a discrete active area mask.
In the embodiment of the present application, as shown in fig. 23A and 23B, the semiconductor device may replace the active line 101 with a higher etching selectivity than the first spin-on hard mask 202 for etching, that is, the etching rate of the material of the active line 101 is greater than the etching rate of the material of the first spin-on hard mask 202, so as to cut off the active line 101 at the cut-off point 103. Then, high selectivity etching is performed on the first spin-on hard mask 202, that is, the etching rate of the material of the first spin-on hard mask 202 is much higher than that of other materials, and the remaining first spin-on hard mask 202 is removed, so as to form the active area mask 102 shown in fig. 6A and 6B.
It can be understood that the active line can be accurately cut off at the cut-off point by selecting different etching rate ratios to etch with the etching hole as a mask, and the remaining first blocking layer is removed without damaging other regions on the active line, thereby improving the LCDU of the formed active region mask.
In some embodiments of the present application, S106 may be further included after S105 shown in fig. 1, and will be described in conjunction with various steps.
And S106, etching the substrate along the active area mask to form an active area.
In an embodiment of the present application, after forming the active area mask, the semiconductor device may etch the substrate along the active area mask, as shown in fig. 24A and 24B, and transfer the pattern of the active area mask onto the substrate 10 to form the discrete active areas 104.
It can be understood that the active area mask obtained by the manufacturing method provided by the foregoing embodiment has higher LCDU, and the LCDU of the active area etched along the active area mask is also more excellent.
The embodiment of the present application further provides a semiconductor structure 80, where the semiconductor structure 80 includes an active region structure prepared by the preparation method provided in the foregoing embodiment, so as to avoid a structural problem caused by unclear photomask imaging in a conventional process, and an LCDU is higher.
The embodiment of the present application further provides a semiconductor memory 90, as shown in fig. 25, the semiconductor memory 90 at least includes a semiconductor structure 80.
In some embodiments of the present application, the semiconductor memory 90 shown in fig. 25 includes at least a dynamic random access memory DRAM.
It should be noted that, in the present application, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments. The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to obtain new method embodiments. Features disclosed in several of the product embodiments provided in the present application may be combined in any combination to yield new product embodiments without conflict. The features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily, without conflict, to arrive at new method embodiments or apparatus embodiments.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (15)
1. A method for preparing an active region structure, the method comprising:
providing a substrate;
forming an initial semiconductor structure on the surface of the substrate; the initial semiconductor structure comprises an active line;
depositing a first barrier layer on the initial semiconductor structure;
etching the first barrier layer to form a first groove extending along a first direction;
etching the first barrier layer to form a second groove extending along a second direction; forming an etching hole in an overlapped area of the first groove and the second groove, wherein the depth of the etching hole is greater than that of the first groove and the second groove;
and etching the active line by taking the etching hole as a mask to form a discrete active area mask.
2. The method of claim 1, wherein the etching the first barrier layer to form a first trench extending in a first direction comprises:
depositing a second barrier layer and a third barrier layer on the first barrier layer in sequence;
etching the third barrier layer to form a first mandrel extending along the first direction; the first mandrels are arranged at intervals;
covering the side surface of the first mandrel to form a first side wall;
and etching by taking the first side walls as masks, removing the second barrier layer, and etching the first barrier layer to form the first groove extending along the first direction.
3. The method of claim 2, wherein the etching the third barrier layer to form a first mandrel extending along the first direction comprises:
forming a first mask on the third barrier layer; the first mask comprises a first etching pattern extending along the first direction;
and etching the third barrier layer along the first etching pattern to form the first mandrel extending along the first direction.
4. The method according to claim 2, wherein the forming a first sidewall covering the side surface of the first mandrel comprises:
depositing a first hard mask layer; the first hard mask layer covers the second barrier layer and the first mandrel;
and carrying out back etching on the first hard mask layer, removing the top of the first hard mask layer until the first mandrel is exposed, and reserving the side part of the first hard mask layer as the first side wall.
5. The method according to claim 2, wherein the etching with the first sidewall as a mask to remove the second barrier layer and etch the first barrier layer to form the first trench extending along the first direction includes:
removing the first mandrel in the middle of the first sidewall;
etching the second barrier layer by taking the first side wall as a mask to form a first intermediate structure;
and etching the first barrier layer by taking the first intermediate structure as a mask to form the first groove extending along the first direction.
6. The method of claim 1, wherein the etching the first barrier layer to form a second trench extending in a second direction comprises:
depositing a fourth barrier layer and a fifth barrier layer on the first barrier layer in sequence; the fourth barrier layer covers the first trench;
etching the fifth barrier layer to form a second mandrel extending along the second direction; the second mandrels are arranged at intervals;
covering the side surface of the second mandrel to form a second side wall;
and etching by taking the second side wall as a mask, removing the fourth barrier layer, and etching the first barrier layer to form the second groove extending along the second direction.
7. The method of claim 6, wherein the etching the fifth barrier layer to form a second mandrel extending along the second direction comprises:
forming a second mask on the fifth barrier layer, wherein the second mask comprises a second etching pattern extending along the second direction;
and etching the fifth barrier layer along the second etching pattern to form the second mandrel extending along the second direction.
8. The method according to claim 6, wherein forming a second sidewall covering the side surface of the second mandrel comprises:
depositing a second hard mask layer; the second hard mask layer covers the fourth barrier layer and the second mandrel;
and carrying out back etching on the second hard mask layer, removing the top of the second hard mask layer until the second mandrel is exposed, and reserving the side part of the second hard mask layer as the second side wall.
9. The method according to claim 6, wherein the etching with the second sidewall as a mask to remove the fourth barrier layer and etch the first barrier layer to form the second trench extending along the second direction includes:
removing said second mandrel intermediate said second sidewalls;
etching the fourth barrier layer by taking the second side wall as a mask to form a second intermediate structure;
and etching the first barrier layer by taking the second intermediate structure as a mask to form the second groove extending along the second direction.
10. The method for preparing the semiconductor device according to claim 1, wherein the step of etching the active lines by using the etching holes as masks to form a discrete active region mask comprises the steps of:
etching by taking the etching hole as a mask until a cutting point on the active line; the cutting point corresponds to the projection position of the etching hole;
and etching the cutting point, and cutting the active line to form the discrete active area mask.
11. The method of claim 1, wherein after etching the active lines using the etching holes as masks to form discrete active region masks, the method further comprises:
and etching the substrate along the active area mask to form an active area.
12. The production method according to any one of claims 1 to 11,
the shape of the etching hole is a rhombus.
13. A semiconductor structure, wherein the semiconductor structure comprises an active region structure;
the active region structure is prepared by the preparation method of any one of claims 1 to 12.
14. A semiconductor memory comprising the semiconductor structure of claim 13.
15. The semiconductor memory according to claim 14, characterized in that the semiconductor memory comprises at least a dynamic random access memory DRAM.
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| PCT/CN2022/072444 WO2023070959A1 (en) | 2021-11-01 | 2022-01-18 | Method for preparing active region structure, and semiconductor structure and semiconductor memory |
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