CN114079463A - Channel mismatch calibration method based on low-frequency reference clock and circuit thereof - Google Patents

Channel mismatch calibration method based on low-frequency reference clock and circuit thereof Download PDF

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CN114079463A
CN114079463A CN202010809080.0A CN202010809080A CN114079463A CN 114079463 A CN114079463 A CN 114079463A CN 202010809080 A CN202010809080 A CN 202010809080A CN 114079463 A CN114079463 A CN 114079463A
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reference clock
frequency reference
low
sampling
clock signal
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王浩南
葛云龙
蔡敏卿
钟英权
李承哲
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Hangzhou Jiyiwei Semiconductor Co ltd
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Hangzhou Jiyiwei Semiconductor Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1028—Calibration at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error

Abstract

The application discloses a channel mismatch calibration method and a circuit thereof in a time interleaving system based on a low-frequency reference clock, wherein the method comprises the following steps: generating a multipath sampling clock and a low-frequency reference clock signal, wherein the frequency of the low-frequency reference clock signal is lower than that of the multipath sampling clock; sampling the low frequency reference clock signal at a sampling rate, wherein a ratio between a frequency of the low frequency reference clock signal and the sampling rate is set to be a prime number relative to a number of the multiplexed sampling clocks; performing analog-to-digital conversion on the sampled low-frequency reference clock signal, comparing the voltage value of the sampled signal with a threshold voltage, judging whether a digital signal corresponding to the voltage value is an edge signal, and outputting an edge detection value; and respectively calibrating the phases of the multi-path sampling clocks according to the edge signals and the edge detection values.

Description

Channel mismatch calibration method based on low-frequency reference clock and circuit thereof
Technical Field
The present invention relates to the field of integrated circuit technology, and in particular, to a channel mismatch calibration method and circuit in a time interleaving system based on a low frequency reference clock.
Background
Time-interleaved (TI) analog-to-digital converters (ADCs) have been widely adopted in high-speed communication systems to achieve accurate data recovery with reasonable power consumption. The TI structure exploits the power efficient sub-ADCs by relaxing the operating speed of each channel, while their inherent channel mismatch (offset, gain and skew) errors limit the overall ADC performance. Furthermore, as the ADC conversion speed reaches above 50GHz, even in the most advanced process technologies, it is not possible to drive a single-phase high-frequency clock source as the sampling clock for each channel ADC. Therefore, recent ultra-high speed ADCs generate sampling phases from multiple master clock sources with different phases (i.e., differential phase or quadrature phase clock sources), which introduces significant skew errors in the TI ADCs.
Various calibration algorithms have been developed in a background or foreground manner to address channel mismatches. In the background approach, the channel ADC output is compensated by using an additional reference channel or expected input statistics. Reference channel based techniques may ensure higher calibration performance but may result in additional hardware complexity associated with the reference channel. On the other hand, when calibration relies on input statistics, ADC performance may be affected by characteristics of the input signal such as frequency, amplitude, distortion, etc., which are difficult to predict in many applications. As a result, although the background approach can adapt the operation of the ADC to variations in process, voltage, and temperature (PVT) without interrupting the data conversion, it is not very popular in the industry.
On the other hand, foreground methods employing known reference signals and dedicated time slots may provide flexibility and robustness in error detection and compensation. Despite the long history, a full foreground method for calibrating a TIADC has not been established, particularly when dealing with skew errors. Recently, an intuitive solution is published in "T.Miki," A2-GS/s 8-bit Time-Interleaved SAR ADC for Millimeter-Wave Pulsed radio base and SoC, "IEEE J.solid-State circuits. This approach uses a full-rate reference clock to detect skew errors between sub-lanes. Gain and offset errors can be corrected by applying a dc input using a separate program. Since the master clock is used as a reference, it can provide built-in test functions. However, for conversion speeds in excess of 50GS/s, CMOS process technology cannot withstand full rate clocking, and thus is difficult to directly apply to future high speed TI ADCs. In addition, the maximum slope detection proposed in "T.Miki," A2-GS/s 8-bit Time-Interleaved SAR ADC for Millimeter-Wave Pulsed RadarBaseband SoC, "IEEE J.solid-State circuits," is susceptible to jitter and reference clock rise/fall times.
Disclosure of Invention
The invention aims to provide a channel mismatch calibration method based on a low-frequency reference clock and a circuit thereof, which loose the speed requirement of a TI structure on a clock source and can be widely applied to an ultra-high-speed TI ADC.
The application discloses channel mismatch calibration circuit based on low frequency reference clock includes:
the clock generating circuit is used for generating a low-frequency reference clock signal and a multi-path sampling clock, and the frequency of the low-frequency reference clock signal is lower than that of the multi-path sampling clock;
the sampling circuits respectively receive the low-frequency reference clock signal and one of the multiple sampling clocks, and respectively sample the low-frequency reference clock signal at a sampling rate, wherein the ratio of the frequency of the low-frequency reference clock signal to the sampling rate is set as a prime number relative to the number of the multiple sampling clocks;
each sampling circuit is correspondingly connected with one or more sub-ADC circuits respectively and outputs sampling signals to the one or more sub-ADC circuits which are connected, the one or more sub-ADC circuits which are connected carry out analog-to-digital conversion on the sampled low-frequency reference clock signals, the voltage value of the sampled signals is compared with the threshold voltage to judge whether the digital signals corresponding to the voltage value are edge signals, and meanwhile edge detection values are output;
and the plurality of skew calibration circuits are respectively connected to the one or more connected sub-ADC circuits and used for receiving the converted digital signals and respectively calibrating the phases of the multi-path sampling clock according to the edge signals and the edge detection values.
In a preferred embodiment, the method further comprises the following steps: and the perturbation injection circuit is connected with the clock generation circuit and is used for adding pseudo-random noise into the low-frequency reference clock signal.
In a preferred example, when the voltage value of the sampled low-frequency reference clock signal is within a threshold range Vth-Vth, the edge detection value is 0, when the voltage value of the low-frequency reference clock signal is greater than the threshold Vth, the edge detection value is 1, and when the voltage value of the low-frequency reference clock signal is less than the threshold-Vth, the edge detection value is-1; the channel mismatch calibration circuit further comprises: the threshold voltage adjusting circuit is connected with the plurality of sub ADC circuits and receives the edge detection values, and when the edge detection values are-1 and 1 in sequence, the threshold voltage is increased; and when the edge detection value is 0 and 0 in sequence, reducing the threshold voltage.
In a preferred embodiment, the method further comprises the following steps: and the reference clock adjusting circuit is used for receiving the edge signals of the plurality of sub ADC circuits, sequentially calculating the absolute value of each edge signal in a plurality of clock period ranges of the low-frequency reference clock signal, selecting the largest one of the absolute values, and adjusting the phase of the low-frequency reference clock signal until the absolute value reaches the minimum value.
In a preferred embodiment, the number of the multi-sampling clocks is 2nThe ratio between the frequency of the low frequency reference clock signal and the sampling rate is set to an arbitrary odd number.
In a preferred embodiment, the method further comprises the following steps: and the plurality of gain calibration circuits are respectively connected with one sub-ADC circuit and adjust the gain according to the digital signals output by the sub-ADC circuit.
In a preferred embodiment, the method further comprises the following steps: and the offset calibration circuits are respectively connected with one sub-ADC circuit and adjust the offset according to the digital signals output by the sub-ADC circuit.
The application also discloses a channel mismatch calibration method based on the low-frequency reference clock, which comprises the following steps:
generating a multipath sampling clock and a low-frequency reference clock signal, wherein the frequency of the low-frequency reference clock signal is lower than that of the multipath sampling clock;
sampling the low frequency reference clock signal at a sampling rate, wherein a ratio between a frequency of the low frequency reference clock signal and the sampling rate is set to be a prime number relative to a number of the multiplexed sampling clocks;
performing analog-to-digital conversion on the sampled low-frequency reference clock signal, comparing the voltage value of the sampled signal with a threshold voltage, judging whether a digital signal corresponding to the voltage value is an edge signal, and outputting an edge detection value;
and respectively calibrating the phases of the multi-path sampling clocks according to the edge signals and the edge detection values.
In a preferred embodiment, pseudo random noise is added to the low frequency reference clock signal.
In a preferred example, when the voltage value of the sampled low-frequency reference clock signal is within a threshold range Vth-Vth, the edge detection value is 0, when the voltage value of the low-frequency reference clock signal is greater than the threshold Vth, the edge detection value is 1, and when the voltage value of the low-frequency reference clock signal is less than the threshold-Vth, the edge detection value is-1; when the edge detection values are-1 and 1 in sequence, increasing the threshold voltage; and when the edge detection value is 0 and 0 in sequence, reducing the threshold voltage.
In a preferred embodiment, the absolute values of the edge signals of the plurality of sub-ADC circuits within a range of several clock cycles of the low-frequency reference clock signal are calculated, and the largest one of the absolute values is selected; adjusting the phase of the low frequency reference clock signal until the absolute value reaches a minimum value.
The application also discloses a channel mismatch calibration circuit based on low frequency reference clock, includes:
the clock generating circuit is used for generating a low-frequency reference clock signal and a multi-path sampling clock, and the frequency of the low-frequency reference clock signal is lower than that of the multi-path sampling clock;
the sub-DAC circuits are used for receiving the multi-path sampling clock and performing digital-to-analog conversion to output analog signals;
the ADC circuit is used for receiving the analog signal and the low-frequency reference clock signal, sampling the analog signal at a sampling rate, performing analog-to-digital conversion, comparing a voltage value of the sampled signal with a threshold voltage to judge whether a digital signal corresponding to the voltage value is an edge signal or not, and outputting an edge detection value, wherein the ratio between the frequency of the low-frequency reference clock signal and the sampling rate is set as a prime number relative to the number of the multi-path sampling clock;
and the skew calibration circuits are used for respectively calibrating the phases of the multi-path sampling clocks according to the edge signals and the edge detection values.
The proposed scheme uses a reference clock much lower than the ADC sampling frequency while compensating for offset, gain and skew mismatches. The low frequency reference clock allows TI ADCs beyond 50GHz to be calibrated using multiple low speed clock sources. For skew calibration, the edge detection method adaptively trains the edge window to enhance flexibility and robustness in implementation. The essence of this method is that it greatly relaxes the speed requirements of the TI structure on the clock source, making it widely applicable in ultra-high speed TI ADCs. The 80GS/s 8-bit time-interleaved pipelined SAR ADC design verifies the effectiveness of the proposed technique. The behavior simulation result shows that the SNDR can be improved by 22dB on average by the method.
Drawings
Non-limiting and non-exhaustive embodiments of the present application are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.
Fig. 1 shows a circuit diagram of a low frequency reference clock based channel mismatch calibration circuit in an embodiment of the present application.
Fig. 2 shows a schematic diagram of a time-interleaved DAC framework in an embodiment of the present application.
Fig. 3 shows a basic schematic diagram of edge calibration in an embodiment of the present application.
Fig. 4 shows a schematic diagram of a threshold voltage adaptation process in an embodiment of the present application.
Fig. 5 shows a schematic diagram of injecting pseudo random noise in edge calibration in one embodiment of the present application.
FIG. 6 shows a schematic diagram of reference clock calibration in one embodiment of the present application.
FIG. 7 shows a flow chart of a reference clock calibration method in one embodiment of the present application.
FIG. 8 shows a schematic of the FFT before and after calibration in an embodiment of the present application.
FIG. 9 shows a schematic representation of Monte Carlo simulations before and after calibration in an embodiment of the present application.
FIG. 10 is a flow chart illustrating a method for calibrating channel mismatch based on a low frequency reference clock according to an embodiment of the present application.
Fig. 11 shows a circuit diagram of a low frequency reference clock based channel mismatch calibration circuit in another embodiment of the present application.
Detailed Description
Various aspects and examples of the present application will now be described. The following description provides specific details for a thorough understanding and enabling description of these examples. However, it will be understood by those skilled in the art that the present application may be practiced without many of these details.
Additionally, some well-known structures or functions may not be shown or described in detail to facilitate brevity and avoid unnecessarily obscuring the relevant description.
The terminology used in the description presented below is intended to be interpreted in its broadest reasonable manner, even though it is being used in conjunction with a detailed description of certain specific examples of the application. Certain terms may even be emphasized below, however, any term that is intended to be interpreted in any restricted manner will be explicitly and specifically defined in this detailed description section.
Part of innovation of the invention is that:
according to the invention, channel mismatch is calibrated based on a low-frequency reference clock, firstly, a plurality of paths of sampling clocks and a low-frequency reference clock signal are generated, the plurality of paths of sampling clocks sample the low-frequency reference clock signal at a sampling rate, the ratio between the frequency of the low-frequency reference clock signal and the sampling rate is set as a prime number relative to the number of the plurality of paths of sampling clocks, the voltage value of the sampled signal is compared with a threshold voltage to judge whether a digital signal corresponding to the voltage value is an edge signal, and the plurality of paths of sampling clocks are respectively calibrated according to the edge signal, so that skew calibration is realized.
The present invention uses a low frequency reference clock as an input to compensate for gain, misalignment and skew errors in a single process. The lower frequency reference clock not only reduces the complexity and power consumption required for high speed calibration, but also enables TI ADC operation using a multi-phase low frequency clock source instead of a single high speed clock source. Ensuring sufficient tuning range of the skew control circuit with small jitter becomes another design challenge when the sampling clock rate reaches tens of GHz. In the proposed algorithm, the reference clock skew calibration is used as a coarse version of the skew calibration, greatly relaxing the tuning range requirements in each sub-ADC clock path. In addition, in order to realize flexibility and robustness, an edge window adaptive method is introduced in the skew error detection. Finally, a pseudo-random noise (PN) signal is injected through the reference clock path, which may speed up convergence time and reduce the bandwidth requirements of the reference clock path.
Example one
Fig. 1 shows a schematic structural diagram of a calibration circuit, which includes a clock generation circuit 10, a plurality of sampling circuits 20, a plurality of SUB-ADC (SUB-ADC) circuits 30, and a plurality of skew calibration circuits 40.
The clock generation circuit 10 is configured to generate a low-frequency reference clock signal (reference clock) and a multiple sampling clock (sampling clock), for example, n sampling clocks, corresponding to the number of multiple sampling circuits, the low-frequency reference clock signal having a lower frequency than the multiple sampling clocks.
The sampling circuits 20 respectively receive one of the low-frequency reference clock signal and the multiple sampling clocks, and respectively sample the low-frequency reference clock signal at a sampling rate, wherein a ratio between a frequency of the low-frequency reference clock signal and the sampling rate is set to be a prime number relative to the number of the multiple sampling clocks. In one embodiment, the number of the multi-sampling clocks is 2nE.g., 4, 16, 64, etc., the ratio between the frequency of the low frequency reference clock signal and the sampling rate is set to any odd number, e.g., 9, 27, etc.
In the plurality of sub-ADC circuits 30, each of the sampling circuits 20 is correspondingly connected to one or more sub-ADC circuits 30 respectively and outputs a sampling signal to the one or more connected sub-ADC circuits 30, the one or more connected sub-ADC circuits 30 perform analog-to-digital conversion on the sampled low-frequency reference clock signal (i.e., the sampled voltage Vi), and compare the voltage value Vi of the sampled signal with the threshold voltage Vth to determine whether the digital signal dch (i) corresponding to the voltage value is the edge signal hedge (i), and simultaneously output the edge detection value sch (i). Where i represents the corresponding number of channels. In the example of fig. 1, one sampling circuit is connected to one sub-ADC circuit, and it should be understood that one sampling circuit may be connected to a plurality of sub-ADC circuits, for example, 2, 4, etc.
A plurality of skew (skew) calibration circuits 41 are respectively connected to the one or more sub-ADC circuits 20, and are configured to receive the converted digital signals dch (i) and respectively calibrate the phases of the multi-sampling clocks according to the edge signals hedge (i) and the edge detection values sch (i).
In one embodiment, the calibration circuit further includes a plurality of gain calibration circuits 41, each connected to one of the sub-ADC circuits 30 and adjusting a gain according to the digital signal dch (i) output from the sub-ADC circuit 30.
In one embodiment, the calibration circuit further includes a plurality of offset (offset) calibration circuits, each connected to one of the sub-ADC circuits 30 and adjusting an offset according to the digital signal dch (i) output from the sub-ADC circuit.
It should be noted that when one sampling circuit is connected to a plurality of sub-ADC circuits, the plurality of sub-ADC circuits are commonly connected to the same skew calibration circuit, and each sub-ADC circuit has a gain calibration circuit and an offset calibration circuit.
In one embodiment, the calibration circuit further comprises a perturbation injection circuit 50 connected to the clock generation circuit 10 and configured to add pseudo-random noise (PN) to the low frequency reference clock signal. It should be appreciated that the injection of pseudo random noise may be performed using any known or future known injection technique.
In one embodiment, the edge detection value sch (i) is 0 when the voltage value of the sampled low frequency reference clock signal is within a threshold range Vth-Vth, 1 when the voltage value of the low frequency reference clock signal is greater than a threshold value Vth, and-1 when the voltage value of the low frequency reference clock signal is less than a threshold value-Vth; the channel mismatch calibration circuit further comprises a threshold voltage adjusting circuit (not shown in the figure), which is connected with the plurality of sub-ADC circuits and receives the edge detection value Sch (i), and when the edge detection value Sch (i) is-1 and 1 in sequence, the threshold voltage Vth is increased; when the edge detection value sch (i) is 0, 0 in sequence, the threshold voltage Vth is decreased.
In one embodiment, the calibration circuit further includes a reference clock adjusting circuit (not shown) for adjusting the phase of the reference clock, wherein the reference clock is adjusted to minimize the adjustment range of the clock skew in the ADC sampling circuit. The specific implementation method is to obtain edge signals Dedge (i) of each channel, sequentially calculate absolute values of the edge signals Dedge (i) of the low-frequency reference clock signal within a plurality of clock periods, and select a maximum absolute value MAX (ABS [ Dedge (i) ]) from the absolute values, that is, MAX (ABS [ Dedge (i)) ] as an evaluation standard for the relative sampling clock position of the reference clock. The phase settings of the reference clocks are searched by scanning all the phase settings of the reference clocks or by using a bisection method until the phase setting of the smallest one of all the evaluation criteria MAX (ABS [ hedge (i) ]) is found. It should be noted that when the phase adjustment of the reference clock is performed, it should be ensured that one or more edge signals dedge (i) are sampled by each channel, and the reliability of the phase adjustment is ensured.
FIG. 2 shows a block diagram of an 80GS/s TI ADC with digital calibration functionality. The TI ADC includes M identical sub-ADC circuits 205, typically implemented in a Successive Approximation Register (SAR) or pipeline (pipeline) architecture. An analog Multiplexer (MUX)203 placed at the front end selects an input between an external analog signal and a low frequency reference clock. The reference clock is generated by a Phase Locked Loop (PLL)202 from one of the master clock sources of the clock generator 201. The ratio between the reference clock and the sampling rate is set to be a relatively prime number of the number of sampling circuits so that each sampling circuit has an opportunity to sample an edge of the reference clock. Following the analog MUX, the input signal is sampled and buffered to drive multiple sub-ADC circuits (in this case, 4 sub-ADCs per sampling circuit). The sampling clock is generated from a plurality of clock sources external to the clock generator 201 that should have uniform intervals of uniform sampling delay between successive clock phases. In other words, the proposed TI ADC architecture may use a 4-phase 20GHz clock source to achieve 80GHz sampling instead of a single 80GHz high speed clock. To ensure overall ADC performance, a 2.96GHz reference clock (1/27 at full rate sampling frequency) may be used to compensate for the sampling skew error. Avoiding full rate clocking, the ADC design can be greatly simplified and save a lot of power and area. Moreover, the number of the skew control modules (i.e., skew calibration circuits) in the digital calibration circuit 206 is equal to the number of the first-stage sampling circuits, the trimming amount Dt in fig. 2 represents the trimming result of the sampling clock of each skew calibration circuit, and the offset and the gain error are respectively adjusted for each sub-ADC channel, i.e., the number of the gain and offset calibration circuits is equal to the number of the sub-ADC channels.
The phase difference between successive sampling clocks should remain uniform. Therefore, a full rate clock would be the first choice for skew calibration to provide an accurate sampling time reference. However, when the conversion rate is higher than several tens of GS/s, the generation of the full-rate clock significantly increases power consumption and limits the conversion speed of the TI ADC. The invention uses a low frequency reference clock as a reference signal for skew calibration to increase ADC speed and alleviate design challenges in high speed clock circuits.
When the full rate clock is divided by the relative prime number (K) by the number of sampling circuits (N) and used as the sampling circuit inputs, each sampling circuit statistically sees the same input with some delay. Conversely, if the sampling intervals between the sampling clocks are uniform, then in every K x N samples, all sampling circuits will obtain the same analog value from the reference clock. In particular, when using a clock rising or falling edge as a reference point, the difference in sample values can be used as a measure of skew detection.
As shown in fig. 2 and 3, a divided-by-9 reference clock is used to calibrate a TI ADC having four sampling circuits. Clock Q1 samples the falling edge of the reference clock at the third sample point. After 9 samples have passed, clock Q2 samples the falling edge, and so on. Thus, all four sampling clocks alternately sample one clock edge in every nine samples, and the sampled data provides phase information for each clock. Skew errors can be eliminated by adjusting the delay of each sampling clock until all sub-ADCs output the same data. To make it more versatile, each sampling circuit finds its own time window in every K x N for skew calibration.
Assuming Dedge (i) as the delay control code of the ith sampling clock path, the control code is modified by the gradient descent method as follows:
Dskew(i),n+1＝Dskew(i),u-u*Dedge(i)
wherein u is determined by a gear-shifting method to balance convergence speed and accuracy, Dskew(i),nIs the nth output of the ith skew calibration circuit, Dskew(i),n+1Is the (n +1) th output of the ith skew calibration circuit.
One of the key points of the proposed skew calibration circuit is how to identify valid edge samples from the ADC output of the sequence. From the inherent characteristics of the reference clock frequency, it is possible that we can pick out the edge sample from the first edge sample. However, in practice, the first edge sample is not as obvious due to the uncertainty of the reference clock delay to the sampling point. Furthermore, depending on the slope of the reference clock, all sampling circuits may miss transition samples (steep slope), or multiple sampling circuits may sample the reference clock during the transition (slow slope).
To simplify the implementation, the present invention proposes the concept of a threshold-based edge window in edge detection. In this method, as shown in fig. 3, the edge detection value sch (i) of the TI ADC output of the sequence is further quantized to 1.5 bits (i.e., -1, 0, 1) by two threshold voltages Vth and-Vth. The data pattern filter identifies a transition pattern [ -1, 0, 1] (up mode) or [1, 0, -1] (down mode) from the output. It is confirmed that the output corresponding to the re-quantized code 0 is regarded as the edge position, and the edge detection value sch (i) of this output is used for the skew correction.
Obviously, the function of this method now depends on the choice of threshold voltage. The threshold voltage is now adjusted by monitoring the ADC output. Once the [ -1, 1] data pattern is observed, the threshold voltage with respect to the edge slope is considered too small, thus increasing Vth. In contrast, when multiple 0 s are observed, Vth is decreased as shown in fig. 4. Therefore, threshold adaptation greatly relaxes the reference clock requirements and makes the calibration algorithm less sensitive to the properties of the reference clock under this PVT variation.
Another method of determining the edge position is to search for the maximum output code change Δ V (═ Dch (i +1) -Dch (i)) and consider as an edge sample one of the two samples whose absolute value is small. Setting this position as the starting point, the next edge can be found after N samples of channel number mod (N, M) + i.
When the slope of the input reference clock is slow, the converted skew error cannot be well distinguished to an amplitude, which is less than the LSB of the sub-ADC, due to quantization noise. To alleviate this fundamental limitation of skew calibration performance, pseudo-random noise (PN) is injected into the reference clock path as shown in fig. 5. The PN signal randomizes the input data and mitigates bias convergence caused by quantization noise. This circuit is implemented by controlling the delay of the reference clock path with the PN pattern, i.e. the pseudo random noise generator 501 controls the delay line 502 of the reference clock. The data applied to the adjustable delay line may be a single bit or multiple bits. The multi-bit PN code can introduce more different inputs into the sampling circuit and further improve the calibration accuracy based on the same quantization noise.
One of the common problems with skew calibration is the trade-off between power consumption and adjustment range in the skew control circuit. In principle, the skew control range, which is determined by the slope of the sampling clock edge, will also have a large impact on jitter performance, and therefore a larger tuning range will result in a larger power consumption to maintain a similar level of jitter performance. On the other hand, when the reference clock path and the sampling clock path have skew errors, each skew control circuit needs a wide tuning range to align the sampling points with the transition points of the reference clock.
In fig. 6, all edge samples from the sampling circuit are wrapped in one reference clock falling edge to show its variation. Initially, edge sampling may be far from the optimal edge position, which may saturate some skew control codes to one side, but still not reach the edge center. Reference clock skew calibration moves the edges to the optimal skew calibration window by adjusting the delay of the reference clock path.
As shown in fig. 7, the reference clock skew calibration uses a similar method to the skew calibration and has edge detection and threshold voltage Vth adaptation functions. The phase adjustment step is larger than the phase adjustment step of the skew control step in the sampling clock path, considering that the skew between the reference clock path and the sampling clock path is large. The goal of the calibration is to center the edges as close as possible to all the sampled edges, i.e., find the minimum value of MAX (ABS [ hedge (i) ]). The simplest approach is to test all valid reference clock skew control codes Dref _ skew one after the other and take the minimum of the evaluation criteria MAX (ABS [ edge (i) ]) as the best reference skew control code. This brute force search method can result in a long calibration time. Another approach is to perform a binary search, each round of search being halved, the search direction being defined by the satisfaction of the criterion MAX (ABS [ hedge (i)).
Gain and offset errors come primarily from the flat portion of the reference clock that is not used for skew calibration. These errors can be corrected by driving the statistics of each sub-ADC output to a single target. Both gain and detuning calibrations use a data-based gradient descent method, as follows:
Dost(i),n+1＝Dost(i),n-u*(Dch(i)-DTO)
Dgain(i),n+1＝Dgain(i),n-u*(abs(Dch(i))-DTG)
similar to the skew calibration, the update step u is dynamically modified by a gear-shifting method to balance convergence speed and accuracy. Dost(i),nIs the nth output of the ith offset calibration circuit, Dost(i),n+1Is the (n +1) th output of the ith offset calibration circuit, DTOIs a target for misalignment calibration, Dgain(i),nIs the nth output of the ith gain calibration circuit, Dgain(i),n+1Is the (n +1) th output of the ith gain calibration circuit, DTGIs a detuning calibration target. And, calibration target D of sub-ADC outputTO、DTGMay be configured as a constant or average value of the ADC output.
Table 1 summarizes the error residuals. The proposed calibration scheme is able to correct gain, offset and skew errors to the limits of the analog circuit adjustment steps.
TABLE-TI ADC Pre-and post-calibration error comparison
Figure BDA0002630259600000131
Fig. 8 shows the FFT spectrum before and after calibration, and it is clear that the spurs caused by misalignment errors are significantly attenuated after calibration. Monte carlo simulations of over 500 tests were performed. Fig. 9 shows that on average the proposed calibration scheme improves ENOB (effective bit) by 3.65 bits, in other words by 22 dB.
Example two
An embodiment of the present application discloses a channel mismatch calibration method based on a low-frequency reference clock, and fig. 10 shows a flowchart of the channel mismatch calibration method, where the method includes:
1001, generating a multi-path sampling clock and a low-frequency reference clock signal, wherein the frequency of the low-frequency reference clock signal is lower than that of the multi-path sampling clock;
step 1002, sampling the low frequency reference clock signal at a sampling rate, wherein a ratio between a frequency of the low frequency reference clock signal and the sampling rate is set as a prime number relative to a number of the multiple sampling clocks;
step 1003, performing analog-to-digital conversion on the sampled low-frequency reference clock signal, comparing the voltage value of the sampled signal with a threshold voltage, judging whether the digital signal corresponding to the voltage value is an edge signal, and outputting an edge detection value;
and 1004, respectively calibrating the phases of the multi-path sampling clocks according to the edge signals and the edge detection values.
In a preferred embodiment, pseudo random noise is added to the low frequency reference clock signal.
In a preferred example, when the voltage value of the sampled low-frequency reference clock signal is within a threshold range Vth-Vth, the edge detection value is 0, when the voltage value of the low-frequency reference clock signal is greater than the threshold Vth, the edge detection value is 1, and when the voltage value of the low-frequency reference clock signal is less than the threshold-Vth, the edge detection value is-1; when the edge detection values are-1 and 1 in sequence, increasing the threshold voltage; and when the edge detection value is 0 and 0 in sequence, reducing the threshold voltage.
In a preferred embodiment, the absolute values of the edge signals of the plurality of sub-ADC circuits within a range of several clock cycles of the low-frequency reference clock signal are calculated, and the largest one of the absolute values is selected; adjusting the phase of the low frequency reference clock signal until the absolute value reaches a minimum value.
EXAMPLE III
The third embodiment of the present application discloses a channel mismatch calibration circuit based on a low-frequency reference clock, which is different from the first embodiment, and is applicable to a TI DAC circuit. The calibration circuit includes a clock generation circuit, a plurality of sub-DAC circuits, an ADC circuit, and a plurality of skew calibration circuits. The clock generation circuit is used for generating a low-frequency reference clock signal and a multi-path sampling clock, and the frequency of the low-frequency reference clock signal is lower than that of the multi-path sampling clock. And the plurality of sub DAC circuits are used for receiving the multi-path sampling clock and performing digital-to-analog conversion to output analog signals. The ADC circuit is used for receiving the analog signal and the low-frequency reference clock signal, sampling the analog signal at a sampling rate, performing analog-to-digital conversion, comparing a voltage value of the sampled signal with a threshold voltage to judge whether a digital signal corresponding to the voltage value is an edge signal, and outputting an edge detection value, wherein the ratio between the frequency of the low-frequency reference clock signal and the sampling rate is set as a prime number relative to the number of the multi-path sampling clock. And the plurality of skew calibration circuits are used for respectively calibrating the phases of the multi-path sampling clocks according to the edge signals and the edge detection values.
Fig. 11 shows a block diagram of a TI DAC with digital calibration functionality. Like time-interleaved ADCs, skew variations between sub-DAC channels also introduce the same distortion in the final DAC output. To eliminate this error, an additional low speed auxiliary ADC may be added to sample the DAC output and convert it to a digital signal. The ADC may be implemented using different architectures such as SAR, pipeline or flash memory, etc. The ADC output may be fed to the same skew calibration module as in the first embodiment described above to correct for skew errors. To facilitate edge detection in a time interleaved DAC architecture, the digital inputs of the sub-DAC channels should be programmed to generate full range edges. Also, each subchannel should be able to generate rising and falling edge transitions in a random manner (PRBS pattern) or in a rotational manner (fixed pattern). The sampling clock of the ADC is set to fs/K, and K is a prime number of M. In this arrangement, the auxiliary ADC samples the edges generated from the sub-DAC channels in turn, and the skew calibration engine will correct the skew error by forcing the edges to zero.
The reference clock calibration scheme proposed by the present invention for a time-interleaved ADC may also be implemented here. With the digitally controlled delay line block shown in fig. 11, the phase of the ADC sampling clock can be adjusted to mitigate the tuning range requirements of the skew control for each sub-DAC channel. Additionally, pseudo random noise may be injected to further enhance skew calibration performance.
It is noted that, in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, same element in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that a certain action is executed according to a certain element, it means that the action is executed according to at least the element, and two cases are included: performing the action based only on the element, and performing the action based on the element and other elements. The expression of a plurality of, a plurality of and the like includes 2, 2 and more than 2, more than 2 and more than 2.
All documents mentioned in this specification are to be considered as being incorporated in their entirety into the disclosure of the present application so as to be subject to modification as necessary. It should be understood that the above description is only a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of the present disclosure should be included in the scope of protection of one or more embodiments of the present disclosure.
In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

Claims (12)

1. A low frequency reference clock based channel mismatch calibration circuit, comprising:
the clock generating circuit is used for generating a low-frequency reference clock signal and a multi-path sampling clock, and the frequency of the low-frequency reference clock signal is lower than that of the multi-path sampling clock;
the sampling circuits respectively receive the low-frequency reference clock signal and one of the multiple sampling clocks, and respectively sample the low-frequency reference clock signal at a sampling rate, wherein the ratio of the frequency of the low-frequency reference clock signal to the sampling rate is set as a prime number relative to the number of the multiple sampling clocks;
each sampling circuit is correspondingly connected with one or more sub-ADC circuits respectively and outputs sampling signals to the one or more sub-ADC circuits which are connected, the one or more sub-ADC circuits which are connected carry out analog-to-digital conversion on the sampled low-frequency reference clock signals, the voltage value of the sampled signals is compared with the threshold voltage to judge whether the digital signals corresponding to the voltage value are edge signals, and meanwhile edge detection values are output;
and the plurality of skew calibration circuits are respectively connected to the one or more connected sub-ADC circuits and used for receiving the converted digital signals and respectively calibrating the phases of the multi-path sampling clock according to the edge signals and the edge detection values.
2. The low frequency reference clock based channel mismatch calibration circuit of claim 1, further comprising: and the perturbation injection circuit is connected with the clock generation circuit and is used for adding pseudo-random noise into the low-frequency reference clock signal.
3. The low frequency reference clock based channel mismatch calibration circuit according to claim 1, wherein the edge detection value is 0 when the voltage value of the sampled low frequency reference clock signal is within a threshold range Vth-Vth, 1 when the voltage value of the low frequency reference clock signal is greater than a threshold Vth, and-1 when the voltage value of the low frequency reference clock signal is less than the threshold-Vth; the channel mismatch calibration circuit further comprises: the threshold voltage adjusting circuit is connected with the plurality of sub ADC circuits and receives the edge detection values, and when the edge detection values are-1 and 1 in sequence, the threshold voltage is increased; and when the edge detection value is 0 and 0 in sequence, reducing the threshold voltage.
4. The low frequency reference clock based channel mismatch calibration circuit of claim 1, further comprising: and the reference clock adjusting circuit is used for receiving the edge signals of the plurality of sub ADC circuits, sequentially calculating the absolute value of each edge signal in a plurality of clock period ranges of the low-frequency reference clock signal, selecting the largest one of the absolute values, and adjusting the phase of the low-frequency reference clock signal until the absolute value reaches the minimum value.
5. The low frequency reference clock based channel mismatch calibration circuit of claim 1, wherein the number of said plurality of sampling clocks is 2nThe ratio between the frequency of the low frequency reference clock signal and the sampling rate is set to an arbitrary odd number.
6. The low frequency reference clock based channel mismatch calibration circuit of claim 1, further comprising: and the plurality of gain calibration circuits are respectively connected with one sub-ADC circuit and adjust the gain according to the digital signals output by the sub-ADC circuit.
7. The low frequency reference clock based channel mismatch calibration circuit of claim 1, further comprising: and the offset calibration circuits are respectively connected with one sub-ADC circuit and adjust the offset according to the digital signals output by the sub-ADC circuit.
8. A channel mismatch calibration method based on a low-frequency reference clock is characterized by comprising the following steps:
generating a multipath sampling clock and a low-frequency reference clock signal, wherein the frequency of the low-frequency reference clock signal is lower than that of the multipath sampling clock;
sampling the low frequency reference clock signal at a sampling rate, wherein a ratio between a frequency of the low frequency reference clock signal and the sampling rate is set to be a prime number relative to a number of the multiplexed sampling clocks;
performing analog-to-digital conversion on the sampled low-frequency reference clock signal, comparing the voltage value of the sampled signal with a threshold voltage, judging whether a digital signal corresponding to the voltage value is an edge signal, and outputting an edge detection value;
and respectively calibrating the phases of the multi-path sampling clocks according to the edge signals and the edge detection values.
9. The method of claim 8, wherein pseudo-random noise is added to the low frequency reference clock signal.
10. The low frequency reference clock based channel mismatch calibration method according to claim 8, wherein the edge detection value is 0 when the voltage value of the sampled low frequency reference clock signal is within a threshold range Vth-Vth, 1 when the voltage value of the low frequency reference clock signal is greater than a threshold Vth, and-1 when the voltage value of the low frequency reference clock signal is less than the threshold-Vth; when the edge detection values are-1 and 1 in sequence, increasing the threshold voltage; and when the edge detection value is 0 and 0 in sequence, reducing the threshold voltage.
11. The channel mismatch calibration method based on the low frequency reference clock according to claim 8, wherein the absolute values of the edge signals of the sub-ADC circuits within a plurality of clock cycles of the low frequency reference clock signal are calculated, and the largest one of the absolute values is selected; adjusting the phase of the low frequency reference clock signal until the absolute value reaches a minimum value.
12. A low frequency reference clock based channel mismatch calibration circuit, comprising:
the clock generating circuit is used for generating a low-frequency reference clock signal and a multi-path sampling clock, and the frequency of the low-frequency reference clock signal is lower than that of the multi-path sampling clock;
the sub-DAC circuits are used for receiving the multi-path sampling clock and performing digital-to-analog conversion to output analog signals;
the ADC circuit is used for receiving the analog signal and the low-frequency reference clock signal, sampling the analog signal at a sampling rate, performing analog-to-digital conversion, comparing a voltage value of the sampled signal with a threshold voltage to judge whether a digital signal corresponding to the voltage value is an edge signal or not, and outputting an edge detection value, wherein the ratio between the frequency of the low-frequency reference clock signal and the sampling rate is set as a prime number relative to the number of the multi-path sampling clock;
and the skew calibration circuits are used for respectively calibrating the phases of the multi-path sampling clocks according to the edge signals and the edge detection values.
CN202010809080.0A 2020-08-12 2020-08-12 Channel mismatch calibration method based on low-frequency reference clock and circuit thereof Pending CN114079463A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115314045A (en) * 2022-10-08 2022-11-08 深圳市好盈科技有限公司 Method, system, device and medium for adaptive calibration of finger output interval
CN115425972A (en) * 2022-08-31 2022-12-02 集益威半导体(上海)有限公司 Error calibration circuit of high-speed cascade analog-to-digital converter circuit
CN116488650A (en) * 2023-03-28 2023-07-25 江苏谷泰微电子有限公司 Time skew error detection method for time domain interleaving analog-to-digital converter

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115425972A (en) * 2022-08-31 2022-12-02 集益威半导体(上海)有限公司 Error calibration circuit of high-speed cascade analog-to-digital converter circuit
CN115314045A (en) * 2022-10-08 2022-11-08 深圳市好盈科技有限公司 Method, system, device and medium for adaptive calibration of finger output interval
CN116488650A (en) * 2023-03-28 2023-07-25 江苏谷泰微电子有限公司 Time skew error detection method for time domain interleaving analog-to-digital converter

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