CN114079460B

CN114079460B - Broadband locking circuit and adjusting method based on same

Info

Publication number: CN114079460B
Application number: CN202210056385.8A
Authority: CN
Inventors: 田进峰; 程煜烽; 徐亮; 陈亚楠; 李彦; 吕柱; 王立鑫
Original assignee: Everpro Technologies Wuhan Co Ltd
Current assignee: Everpro Technologies Wuhan Co Ltd
Priority date: 2022-01-18
Filing date: 2022-01-18
Publication date: 2022-04-26
Anticipated expiration: 2042-01-18
Also published as: CN114079460A

Abstract

The invention relates to a broadband locking circuit, comprising: a voltage controlled oscillator configured to output a clock signal under the action of an analog voltage control signal and a digital band control signal of the voltage controlled oscillator; a signal conditioning circuit coupled to the voltage controlled oscillator and configured to cyclically: receiving a high-speed signal input continuously and a clock signal output by the voltage-controlled oscillator; and regulating and controlling the analog voltage control signal and the digital frequency band control signal according to the comparison result of the high-speed signal and the clock signal until the high-speed signal is locked to be matched with the clock signal. By the technical scheme, the multi-standard compatibility of the whole circuit can be effectively improved, high-efficiency and accurate signal locking processing is realized, and the usability of the circuit is improved. In addition, the invention also provides an adjusting method based on the broadband locking circuit.

Description

Broadband locking circuit and adjusting method based on same

Technical Field

The present invention relates generally to the field of circuit design. More particularly, the present invention relates to a wide band locking circuit and an adjustment method based on the wide band locking circuit.

Background

In order to increase the data transmission capability, the transmission rate of data is required to be increased. The ongoing development of standards and industries has made the data rate requirements vary from product to product and standard to standard. For example, the multi-standard of 24-28 Gbps is widely distributed in high-speed transmission application, and the circuit is required to have high bandwidth compatibility. Meanwhile, data transmitted at high speed inevitably suffers various losses in the medium, so that the data quality is worse and worse, and even completely destroyed. Based on this, a clock data recovery circuit is usually inserted in the data transmission path to help save and recover data, completing transmission over long distances.

At present, the application of adapting to the broadband rate is a requirement for the development of the current clock data recovery circuit technology. Adapting to broadband applications faces a problem of finding the exact frequency from a broadband clock source. In this regard, the related art mainly relates to two solutions. For example, the first mode is implemented based mainly on the relationship between the number of edges of the input random data and the data rate data transmission rate being relatively fixed for a long statistical time. Specifically, the Counter counts the number of rising edges in a certain time, then the highest bit of the Counter represents a harmonic frequency of the data transmission rate, and the frequency is compared with a frequency division frequency of a current Digital-Controlled Oscillator (DCO) to determine the speed of the current DCO frequency. In short, the number of edges is counted for a long time, and then the magnitude of the two statistics is compared to determine the DCO frequency.

In the first way, in the edge counting process, firstly, the number of counted edges is related to the Data Pattern (Data Pattern). The difference in data pattern at the same data rate results in a difference in the number of edges counted by the calculator, and thus is mapped as an error in frequency. Secondly, the frequency accuracy depends on the statistical duration of the counter, and the longer the statistical duration is, the smaller the frequency error is, so that the locking time is too long, and the actual requirement cannot be met.

For another example, the second approach mainly involves counting the number of E/L with a calculator in a time when the difference between the clock rates of the input data and the numerically controlled oscillator is equal to one cycle. Wherein, E represents the precedence relationship between the clock edge and the data edge, and L represents that the clock edge lags the data edge. The number of E/L counted reflects the speed of phase change, i.e. frequency error, caused by the rate difference. If the statistic value of the counter is smaller, the current rate error is larger, and if the statistic value of the counter is larger, the current rate error is smaller. Thus, frequency lock may be considered when the count of the counter exceeds a certain threshold. The method overcomes the influence of the data mode on the error to a certain extent, but also has the problems that the frequency error is influenced by misjudgment of the statistical result of E/L caused by data jitter, the frequency error is too large due to false locking of fractional harmonics (for example, the data rate is equal to two thirds of the frequency), so that a later phase locking loop cannot be converged, the locking speed is low due to the fact that gradual scanning is required to be started from the lowest frequency, and the like. Therefore, the locking processing effect of the prior art on signals is not ideal, and the actual requirements cannot be met.

Disclosure of Invention

To solve at least the above technical problems described in the background section, the present invention provides a wideband locking circuit. By using the scheme of the invention, the multi-standard compatibility of the whole circuit can be effectively improved, and the high-efficiency and accurate signal locking processing is realized, so that the usability of the circuit is improved. In view of this, the present invention provides solutions in the following aspects.

A first aspect of the present invention provides a broadband locking circuit, including: a voltage controlled oscillator configured to output a clock signal under the action of an analog voltage control signal and a digital band control signal of the voltage controlled oscillator; a signal conditioning circuit coupled to the voltage controlled oscillator and configured to cyclically: receiving a high-speed signal input continuously and a clock signal output by the voltage-controlled oscillator; and regulating and controlling the analog voltage control signal and the digital frequency band control signal according to the comparison result of the high-speed signal and the clock signal until the high-speed signal is locked to be matched with the clock signal.

In one embodiment, wherein the signal conditioning circuit comprises a frequency detector, a phase detector, a first voltage-to-current conversion module, a second voltage-to-current conversion module, an analog loop filter, and an analog-to-digital converter; wherein the voltage controlled oscillator, the frequency detector, the first voltage-to-current conversion module, the analog loop filter, and the analog-to-digital converter form a frequency locked loop to achieve frequency locking of the high speed signal and the clock signal; and wherein the voltage controlled oscillator, the phase detector, the second voltage to current conversion module, the analog loop filter, and the analog-to-digital converter form a phase locked loop to achieve phase locking of the high speed signal and the clock signal.

In one embodiment, the frequency detector is configured to determine a turning frequency band code of the digital frequency band control signal according to the comparison result, and to filter an optimal frequency band code satisfying a predetermined condition with reference to the turning frequency band code, and the first voltage-to-current conversion module is connected to the frequency detector and configured to regulate and control the analog voltage control signal under the control of the frequency detector.

In one embodiment, wherein the frequency detector comprises: and the identification bit generating circuit comprises a buffer, a filter and a comparator which are sequentially connected, wherein the identification bit generating circuit is configured to process a target signal representing the comparison result and output an adjustment identification bit so as to determine the turning frequency band code of the digital frequency band control signal based on the adjustment identification bit.

In one embodiment, wherein the frequency detector further comprises: a lock detection circuit, which comprises a not gate, a first delayer, a nand gate, a second delayer, a nor gate and a counter, wherein an input end of the not gate and an input end of the first delayer are respectively used as input ends of the lock detection circuit, an output end of the not gate and an output end of the first delayer are respectively connected to an input end of the nand gate, an output end of the nand gate is connected to one input end of the nor gate and an input end of the second delayer, an output end of the second delayer is connected to the other input end of the nor gate, and an output end of the nor gate is connected to the counter and is used as an output end of the lock detection circuit; wherein the lock detection circuit is configured to: processing the high-speed signal and the clock signal acquired by the input end of the clock signal to obtain a locking identification signal; outputting the locking identification signal through an output end of the locking identification signal; and counting the number of rising edges of the locking identification signal in a preset time period through the counter.

A second aspect of the present invention provides an adjusting method based on the foregoing broadband locking circuit, including: determining a turning frequency band code of the digital frequency band control signal based on the adjustment identification bit; and performing a regulation operation on the digital band control signal by taking the turning frequency band code as a reference so as to screen out an optimal frequency band code from a frequency band code set containing the turning frequency band code.

In one embodiment, wherein performing the conditioning operation on the digital band control signals to filter out an optimal frequency band code comprises: assigning any frequency band code in the frequency band code set to the digital frequency band control signal in each regulation process of the digital frequency band control signal; sequentially starting the first voltage-to-current conversion module and the second voltage-to-current conversion module to work; counting the number of rising edges of the locking identification signal and the voltage value of the analog voltage control signal in a preset time; and determining the frequency band code corresponding to the digital frequency band control signal as an optimal frequency band code in response to the statistical result meeting a preset condition.

In one embodiment, wherein sequentially activating the first voltage-to-current conversion module and the second voltage-to-current conversion module comprises: gradually adjusting the current control bit related to the first voltage-to-current conversion module from high to low and gradually adjusting the current control bit related to the second voltage-to-current conversion module from high to low to high until the first voltage-to-current conversion module is completely closed and the frequency locked loop is opened and the second voltage-to-current conversion module is completely opened and the phase locked loop is established; or after the first voltage-to-current conversion module is closed, the second voltage-to-current conversion module is started; or reducing the current of the first voltage-to-current conversion module to the minimum gear, and then starting the second voltage-to-current conversion module.

In one embodiment, wherein determining the turning frequency band code of the digital band control signal based on the adjustment identification bits comprises: selecting a middle frequency band code in a plurality of frequency band codes as a reference frequency band code of the digital frequency band control signal; and circularly adjusting up or down the reference frequency band code according to the output result of the adjustment identification bit to screen the maximum frequency band code which enables the adjustment identification bit to output the appointed result, and determining the maximum frequency band code as the turning frequency band code.

By utilizing the scheme provided by the invention, the clock signal output by the voltage-controlled oscillator can be regulated and controlled by utilizing the analog voltage control signal and the digital frequency band control signal, and the analog voltage control signal and the digital frequency band control signal are regulated and controlled according to the comparison result of the input high-speed signal and the clock signal based on the signal regulating circuit so as to form the cyclic regulation on the clock signal until the locking of the high-speed signal and the clock signal is realized. The whole locking process has no excessive limitation on signal frequency bands, the multi-standard compatibility of the whole circuit can be effectively improved, and meanwhile, efficient and accurate signal locking processing is realized, so that the usability of the circuit is improved.

The invention also provides an adjusting method based on the broadband locking circuit, which combines an adjusting identification bit generated by an identification bit generating circuit in the broadband locking circuit and a locking identification signal generated by a locking detection circuit to accurately position a correct frequency band from a plurality of narrow frequency bands divided by the broadband to capture the correct frequency and phase of the signal under the correct frequency band, thereby realizing the accurate locking of the signal. In addition, in some embodiments of the present invention, the voltage-to-current conversion modules located in the frequency locked loop and the phase locked loop may be sequentially started in the adjustment process, so as to realize a smooth transition from the frequency locked loop to the phase locked loop, thereby effectively avoiding mutual interference between the two loops.

Drawings

The above and other objects, features and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar or corresponding parts and in which:

figure 1 is a schematic diagram illustrating a broadband locking circuit according to one embodiment of the present invention;

fig. 2 is a schematic diagram illustrating a broadband locking circuit according to another embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating an identification bit generation circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram illustrating a lock detection circuit according to an embodiment of the present invention;

FIG. 5 is a comparison diagram illustrating various signals that have been sample processed in accordance with an embodiment of the present invention; and

fig. 6 is a flow chart illustrating a wideband locking circuit based adjustment method according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making creative efforts based on the embodiments of the present invention, belong to the protection scope of the present invention.

It should be understood that the terms "first", "second", "third" and "fourth", etc. in the claims, the description and the drawings of the present invention are used for distinguishing different objects and are not used for describing a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification and claims of this application, the singular form of "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this specification refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.

As used in this specification and claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

The following detailed description of embodiments of the invention refers to the accompanying drawings.

Fig. 1 is a schematic diagram illustrating a wideband locking circuit 100 according to one embodiment of the invention. It should be noted that the wideband locking circuit 100 can be applied to a circuit requiring signal locking, such as a clock data recovery circuit. The clock data recovery circuit is a key module in high-speed data transmission, and can find out the clock frequency corresponding to the data rate in order to normally lock and sample data, and then adjust the phase to align the clock sampling edge to the middle of the data. A wideband locking circuit 100 may be employed in this process to lock the clock frequency corresponding to the data rate.

As shown in fig. 1, the wideband locking circuit 100 may include a voltage controlled oscillator 101 and a signal conditioning circuit 102. Wherein the voltage controlled oscillator 101 may be configured to output the clock signal under the influence of the analog voltage control signal and the digital band control signal of the voltage controlled oscillator 101. The voltage-controlled oscillator 101 is an oscillating circuit having a corresponding relationship between an output frequency and an input control voltage, and has the advantages of good frequency stability, high control sensitivity, wide frequency modulation range, and a linear relationship between a frequency offset and a control voltage. Wherein the frequency band of the voltage controlled oscillator 101 may be divided into several frequency bands and selected by a digital band control signal. Therefore, the bandwidth of each frequency band is relatively narrow, and the output clock signal can be accurately regulated and controlled through the analog voltage control signal and the digital frequency band control signal under each narrow frequency band.

And the signal conditioning circuit 102 is connected to the voltage controlled oscillator 101 and may be configured to cyclically perform the following operations: receiving a high-speed signal input continuously and a clock signal output by the voltage-controlled oscillator 101; and regulating and controlling the analog voltage control signal and the digital frequency band control signal according to the comparison result of the high-speed signal and the clock signal until the high-speed signal is locked to be matched with the clock signal. Therefore, the clock signal output by the voltage-controlled oscillator 101 can be regulated by the analog voltage control signal and the digital band control signal, and the analog voltage control signal and the digital band control signal are regulated by the signal regulating circuit 102 according to the comparison result of the input high-speed signal and the clock signal to form a cyclic regulation on the clock signal until the high-speed signal and the clock signal are locked (i.e., the frequency and the phase of the high-speed signal are determined to be matched with the frequency and the phase of the clock signal). The whole locking process has no excessive limitation on signal frequency bands, the multi-standard compatibility of the whole circuit can be effectively improved, and meanwhile, efficient and accurate signal locking processing is realized, so that the usability of the circuit is improved.

Fig. 2 is a schematic diagram illustrating a wideband locking circuit 200 according to another embodiment of the present invention. It should be noted that wideband locking circuit 200 may be understood as one possible exemplary application of wideband locking circuit 100 in fig. 1. Therefore, the same applies to the following description in connection with fig. 1.

As shown in fig. 2, the wideband locking circuit 200 may include a voltage controlled oscillator 201 (i.e., VCO in fig. 2) and a signal conditioning circuit. Specifically, the signal conditioning circuit may include a frequency detector 202 (i.e., FD in fig. 2), a phase detector 203 (i.e., PD in fig. 2), a first voltage-to-current conversion module 204 (i.e., FLL-V2I in fig. 2), a second voltage-to-current conversion module 205 (i.e., PLL-V2I in fig. 2), an Analog Loop Filter 206 (i.e., Analog Loop Filter in fig. 2), and an Analog-to-digital converter 207 (i.e., ADC in fig. 2). The voltage-controlled oscillator 201, the frequency detector 202, the first voltage-to-current conversion module 204, the analog loop filter 206, and the analog-to-digital converter 207 form a frequency locked loop to achieve frequency locking of the high-speed signal and the clock signal. Wherein the voltage controlled oscillator 201, the phase detector 203, the second voltage to current conversion block 205, the analog loop filter 206, and the analog-to-digital converter 207 form a phase locked loop to achieve phase locking of the high speed signal and the clock signal. Therefore, the signal adjusting circuit and the voltage-controlled oscillator 201 are matched to form a frequency locking loop and a phase locking loop, so that signal locking processing is realized in an analog mode, the problems of noise and the like can be avoided, and the performance of the whole circuit is effectively improved.

Further, in some embodiments, the frequency detector 202 may be specifically configured to determine a turning frequency band code of the digital band control signal according to the comparison result, and filter an optimal frequency band code satisfying a predetermined condition based on the turning frequency band code. Here, the passband code is understood to be a code of a frequency band corresponding to a frequency transition. The first voltage-to-current conversion module 204 is connected to the frequency detector 202, and may be configured to regulate the analog voltage control signal under the control of the frequency detector 202. Specifically, the frequency detector 202 may output a corresponding regulation signal, which is processed by the first voltage-to-current conversion module 204 to regulate the analog voltage control signal.

In some embodiments, the determination of the kink band code may be assisted by an identification bit generation circuit. Fig. 3 shows a schematic diagram of one possible exemplary circuit of the identification bit generation circuit. Specifically, as shown in fig. 3, the identification bit generation circuit 300 may include a buffer 301, a filter 302, and a comparator 303 connected in sequence. The flag bit generation circuit 300 is configured to process a target signal representing the comparison result and output an adjustment flag bit, so as to determine the passband code of the digital band control signal based on the adjustment flag bit. Specifically, the technical principle of the Frequency Detector 202 in fig. 2 is derived from an improved manner of Digital quadrature-Frequency Detector (DQFD) technology. Based on this, FD _ DO generated inside the frequency detector 202 (i.e. the aforementioned target signal) is related to the frequency error and processed by the buffer 301, the filter 302 and the comparator 303 to output the adjustment flag FD _ FREQUEST [1:0 ].

Specifically, if the frequency error is large, the FD-DO cannot indicate the specific frequency error level, and is a pulse signal that is continuously switched between high and low levels and the high and low levels are continuously inverted. The signal DO _ LP is then generated after filtering by the filter 302. The DO _ LP is a mid-level signal that is above the low threshold VTH _ L and below the high threshold VTH _ H, and the output FD _ FREQUEST [1:0] of the comparator 303 is '01'. If the frequency error is small and the clock frequency is higher than the rate of the high speed signal, FD-DO is a signal that occasionally appears as a low pulse and is high most of the time. In this case, DO LP is a high signal after filtering, which is higher than the low threshold VTH _ L and also higher than the high threshold VTH _ H. Thus, the output FD _ FREQSTAT [1:0] of comparator 303 is '00'. If the frequency error is small and the clock frequency is lower than the rate of the height signal, FD-DO is a signal that occasionally has high pulses and is low most of the time. Now DO LP after filtering is a low signal that is lower than the low threshold VTH _ L and lower than the high threshold VTH _ H. Thus, the output FD _ FREQSTAT [1:0] of comparator 303 is '11'.

Further, in some embodiments, the frequency detector 202 in fig. 2 further comprises lock detection circuitry configured to: processing the high-speed signal and the clock signal collected by the input end of the locking device to obtain a locking identification signal; outputting the locking identification signal through an output end of the locking identification signal; and counting the number of rising edges of the locking identification signal in a preset time period through a counter.

Fig. 4 shows a schematic diagram of one possible exemplary circuit of the lock detection circuit 400. In addition, for easier understanding of the circuit principle, a sampling circuit is also shown in fig. 4. Specifically, as shown in fig. 4, the lock detection circuit 400 may include an not gate 401, a first delayer 402, a nand gate 403, a second delayer 404, a nor gate 405, and a counter 406. The input of the not gate 401 and the input of the first delay 402 are respectively used as the input of the lock detection circuit 400, the output of the not gate 401 and the output of the first delay 402 are respectively connected to the input of the nand gate 403, the output of the nand gate 403 is connected to one input of the nor gate 405 and the input of the second delay 404, the output of the second delay 404 is connected to the other input of the nor gate 405, and the output of the nor gate 405 is connected to the counter 406 and is used as the output of the lock detection circuit 400. And the sampling circuit may include a first buffer 407, a second buffer 408, a third buffer 409, a fourth buffer 410, a first edge flip-flop 411, and a second edge flip-flop 412.

In practical applications, the frequency detector receives the high-speed signal (DATA _ P/DATA _ N), and the high-speed signal is buffered by the multi-stage buffers (407-410) to obtain D1P/D1N, DIP/DIN and D2P/D2N. Buffering the signal not only enhances the driving ability, but also generates the necessary delay. Next, the clock signals CLKP/CLKN, D1P/D1N are respectively collected by the first edge flip-flop 411, and the clock signals CLKP/CLKN and D2P/D2N are respectively collected by the second edge flip-flop 412. Wherein the first edge flip-flop 411 outputs Q1 according to the sampling results of CLKP/CLKN and D1P/D1N, and the second edge flip-flop 412 outputs Q2 according to the sampling results of CLKP/CLKN and D2P/D2N. Q1 and Q2 are input to the LOCK detection circuit 400 for processing, respectively, to output a LOCK flag signal LOCK _ flag. In addition, when CLKP/CLKN and DIP/DIN are locked by phase detector PD, the output signal DOP/DON of phase detector PD is aligned with the phase and frequency of the clock signal.

Fig. 5 is a comparative diagram illustrating respective signals subjected to sampling processing according to an embodiment of the present invention. Specifically, as shown in fig. 5, the edges of the signals D1P and D2P correspond to the low and high level positions of the signal CLKP, respectively. Ideally, when the edge flip-flop DFF (411 and 412 in fig. 4) is used for sampling in the LOCK state without jitter, the state of the corresponding output (Q1, Q2) is (0, 1), and the result is processed by the LOCK detection circuit (400 in fig. 4) to obtain that LOCK _ flag is at a fixed low level. After sampling with edge flip-flops DFF in the locked state at small jitter, the state of the corresponding output (Q1, Q2) jumps between (0, 1), (0, 0) and (1, 1). After the three states are processed by the LOCK detection circuit, it can be obtained that LOCK _ flag is a fixed low level. The state of the corresponding output (Q1, Q2) jumps between (0, 0) and (1, 1) after sampling with the edge flip-flop DFF in the locked state at higher jitter. Due to the data sampling sequence, the Q1 is changed to high level before the Q2, so that a transient state (1, 0) exists in the middle, and the state can cause the LOCK _ FLAGN to be high if not processed, and false alarm is generated. To this end, the lock detection circuit generates the LOD signal by delaying the DELAY signal by the LO signal for this condition, and then subjecting the two signals to NOR processing, wherein the effect of the transient state (1, 0) is eliminated as long as the DELAY time is greater than the time that this state occurs. Thus, LOCK _ flag in this state is also a fixed low, as shown in fig. 5, eliminating erroneous high pulses.

In the phase-out-of-lock state, the phases of CLKP and D1P and D2P are not fixed, and the edges are not always aligned. Thus, the states of the DFF sampled results (Q1, Q2) are (0, 0), (0, 1), (1, 1), and (1, 0) occurring randomly. The (1, 0) state is maintained until the next sample when it occurs, which is longer in duration than the DELAY time. At this time, the (1, 0) state is reflected as a high pulse of LOCK _ FLAGN, and this pulse is accumulated by the count of the pulse COUNTER COUNTER and reflected in the LOCK _ CNT [9:0] signal.

The operation of the entire wideband locking circuit will be described with reference to fig. 6. Fig. 6 is a block diagram illustrating a wideband locking circuit based adjustment method 600 according to an embodiment of the present invention. It should be noted that the adjusting method 600 may be implemented according to the wideband locking circuit described in fig. 2 to 5. Therefore, the description above in connection with fig. 2 to 5 also applies hereinafter.

As shown in fig. 6, at step 601, the turning frequency band code of the digital band control signal can be determined based on the aforementioned adjustment flag. As described above, the adjustment flag can be generated by the flag generation circuit described above. The specific identifier generation process may refer to the related description in fig. 3, and is not described herein again.

Specifically, in some embodiments, the frequency band of the voltage-controlled oscillator may be divided into a plurality of frequency bands, and an intermediate frequency band code of the plurality of frequency band codes may be selected as a reference frequency band code of the digital band control signal. And then circularly adjusting up or down the reference frequency band code according to the output result of the adjustment identification bit to screen the maximum frequency band code which enables the adjustment identification bit to output the appointed result, and determining the maximum frequency band code as the turning frequency band code.

For example, in an initial state where the entire circuit is turned off, an analog voltage control signal (hereinafter abbreviated VCO-VCTL) of a voltage controlled oscillator (hereinafter abbreviated VCO) may be reset to a fixed intermediate voltage VMID, and a digital band control signal (hereinafter abbreviated VCO _ DCTL) may be reset to an intermediate frequency band code. When the high-speed signal is input, the external detection circuit controls the opening circuit to recover the clock to relock the data through an output Flag bit (such as E-idle Flag). Wherein, it is ensured that the output Flag of the E-idle is always low after the circuit starts to work, i.e. it means that the data input state continues. If the interruption of the transmission data occurs or the E-idle Flag is high, the circuit needs to return to the initial state and perform the initialization process again.

The circuit is then turned on to resume the clock to relock the data. First, the passband code of VCO DCTL needs to be determined. To determine the frequency band corresponding to the frequency break, the VCO and FD need to be turned on and VCO-VCTL is fixed at a certain voltage (e.g., the intermediate voltage VMID, which may be temperature dependent) by the FLL _ V2I module. Thus, the frequency of the output clock CLKP/CLKN of the VCO represents the frequency of the current band. Then, wait VCO _ READY to go high or wait for a period of time (e.g., 5 us).

Then, VCO _ DCTL starts to regulate and control from the intermediate frequency band code, waits for a period of time (for example, 5us or waits for the clock data recovery circuit to give a FLAG) after the VCO _ DCTL is set, then records the output FLAG bits FD _ FREQUEST [1:0] of the frequency detector FD, and regulates and controls VCO _ DCTL accordingly. Specifically, if the result of FD _ FREQSTAT [1:0] is '01', it means that the band cannot be judged high or low. At this time, VCO _ DCTL is controlled to increase/decrease one frequency band to judge again until FD _ FREQUEST [1:0] output is equal to '11' or '00'. If the result of FD _ FREQSTAT [1:0] is '11', it indicates that the frequency band is low. At this time, the VCO _ DCTL needs to be regulated and controlled to add a Code and then judge until the result of FD _ FREQSTAT [1:0] becomes '00', and at this time, the Code of the maximum VCO _ DCTL with the result of FD _ FREQSTAT [1:0] as '11' is selected as the turning frequency band Code. If the result of FD _ FREQSTAT [1:0] is '00', this band is indicated to be high in frequency. At this time, VCO _ DCTL needs to be controlled to reduce one code and then judgment is made until the result of FD _ FREQSTAT [1:0] becomes '11', and at this time, the code of the maximum VCO _ DCTL with the result of FD _ FREQSTAT [1:0] as '11' is selected as the breakover frequency band code.

In addition, if the result of FD _ FREQSTAT [1:0] is '10', indicating that the circuit is in an abnormal state, the circuit may be checked several times at regular intervals in order to ensure the credibility of the result. For example, it can be checked three times in 1us, and if the three times are consistent, the results are reported to the upper control logic and the control circuit returns to the initial state. In addition, the FD _ FREQSTAT [1:0] result is also '10' if the circuit is in an initial state or has completed the locking process, but no response is required to this result. If no turning frequency band code meeting the condition is found, a flag bit is output to inform, and the current processing flow is exited.

After the determination of the turning frequency band code is completed, in step S602, a tuning operation on the digital band control signal may be performed based on the turning frequency band code to screen out an optimal frequency band code from a frequency band code set including the turning frequency band code.

Specifically, in some embodiments, any frequency band code of the set of frequency band codes may be assigned to the digital band control signal (i.e., VCO _ DCTL) during each adjustment of the digital band control signal. Next, the first voltage-to-current conversion module (i.e., the FLL-V2I module described above) and the second voltage-to-current conversion module (i.e., the PLL-V2I module described above) may be sequentially enabled. Then, the number of rising edges of the locking identification signal (i.e., the aforementioned signal LOCK _ flag) and the voltage value of the analog voltage control signal (i.e., the aforementioned VCO _ VCTL) are counted for a predetermined time, and in response to the counted result satisfying a predetermined condition, the frequency band code corresponding to the digital frequency band control signal is determined to be the optimal frequency band code.

In some embodiments, after determining the passband codes of the VCO _ DCTL, the VCO _ DCTL may generate the set of frequency codes based on the passband codes. For example, the turning frequency band Code can be used as the center to select the peripheral 5-level Code for searching the optimal frequency band Code. Specifically, the frequency detector FD and the phase detector PD may be turned on to start locking from the VCO _ DCTL = breakover band Code setting.

At this time, in order to ensure a smooth transition from the FLL loop to the PLL loop, in some embodiments, the current control bits FLLV2I _ IBSEL [9:0] of the FLL _ V2I block are gradually changed from high to low, and the current control bits PLLV2I _ IBSEL [9:0] of the PLL _ V2I block are gradually changed from high to low to high. Until the FLL _ V2I module is fully closed and the Frequency Locked Loop (FLL) is open, the PLL _ V2I module gradually fully opens while the Phase Locked Loop (PLL) is established. In other embodiments, PLL _ V2I may be turned on after the FLL _ V2I module is turned off. Specifically, the V2I current of the FLL may be stepped down until it is turned off before the V2I of the PLL is opened, avoiding the problem of both loops working together. In still other embodiments, the V2I of the FLL is reduced to the minimum current level and then the PLL V2I is controlled to open again, thereby increasing the lock time window of the PLL while avoiding interference between the two loops to some extent.

Then, after the FD outputs the current control bits FLLV2I _ IBSEL [9] to FLL _ V2I module all become 0 and wait for 5uS, the LOCK detection circuit and analog-to-digital conversion module (ADC) in FD is activated to count the number of rising edges of LOCK _ FLAGN in a certain time and check the voltage value of VCTL.

The VCO _ DCTL may sequentially try in 5 candidate frequency band codes in the frequency band code set, and perform the above process in a loop until all candidate frequency band codes are tried or the optimal frequency band code is screened out. Wherein the screened optimal frequency band code satisfies that the number of rising edges of LOCK _ FLAGN reaches a threshold value and the deviation of the result of the ADC module (e.g., VCTL _ ADCOUT [5:0 ]) from the intermediate voltage VMID is minimum. If the circuit is locked because the proper optimal frequency band code is not found, a flag bit is output to inform and the current processing flow is exited.

Further, in some embodiments, after VCO _ DCTL is set to the optimal frequency band code and the circuit is relocked, the lock state may be repeatedly detected by the lock detection circuit in the FD. If the circuit keeps locking, the rising edge number of the LOCK _ FLAGN within 1uS can be continuously counted in real time to judge the current state. If the jump circuit is again out-of-lock due to a sudden change in the external input data rate or other conditions, a flag bit may be output to inform the upper layer logic circuit. According to the state of the identification bit, the upper layer logic circuit can restart the whole clock recovery and data locking process after being reset automatically or manually.

Based on the above, the scheme of the invention ensures that the frequency search can smoothly obtain the correct frequency result, and simultaneously, the switching from the Frequency Locked Loop (FLL) to the Phase Locked Loop (PLL) is completed, and whether the Phase Locked Loop (PLL) is correctly locked at the working point can be synchronously detected. In addition, the multi-standard compatibility of the whole circuit is improved, the locking range of the frequency locking loop FLL is greatly expanded, and therefore the usability of the circuit is improved.

While various embodiments of the present invention have been shown and described herein, it will be obvious to those skilled in the art that such embodiments are provided by way of example only. Numerous modifications, changes, and substitutions will occur to those skilled in the art without departing from the spirit and scope of the present invention. It should be understood that various alternatives to the embodiments of the invention described herein may be employed in practicing the invention. It is intended that the following claims define the scope of the invention and that the module compositions, equivalents, or alternatives falling within the scope of these claims be covered thereby.

Claims

1. A broadband locking circuit, comprising:

a voltage controlled oscillator configured to output a clock signal under the action of an analog voltage control signal and a digital band control signal of the voltage controlled oscillator;

a signal conditioning circuit coupled to the voltage controlled oscillator and configured to cyclically:

receiving a high-speed signal input continuously and a clock signal output by the voltage-controlled oscillator; and

regulating and controlling the analog voltage control signal and the digital frequency band control signal according to the comparison result of the high-speed signal and the clock signal until the high-speed signal is locked to be matched with the clock signal;

wherein the signal conditioning circuit includes a frequency locked loop that achieves frequency locking of the high-speed signal and the clock signal and a phase locked loop that achieves phase locking of the high-speed signal and the clock signal, wherein the frequency locking loop comprises a frequency detector configured to determine a turning frequency band code of the digital band control signal according to the comparison result, and to screen an optimal frequency band code satisfying a preset condition with the turning frequency band code as a reference, wherein the voltage controlled oscillator comprises a plurality of frequency band codes, selects a middle frequency band code of the plurality of frequency band codes as a reference frequency band code of the digital frequency band control signal, and adjusts the reference frequency band code according to an output result of the adjustment flag, selecting the maximum frequency band code which enables the adjustment identification bit to output the appointed result as a turning frequency band code; and screening out an optimal frequency band code from a frequency band code set containing the turning frequency band codes, wherein the optimal frequency band code meets the preset conditions that the number of rising edges of the locking identification signal reaches a threshold value and the deviation between the result of the analog-to-digital converter and the intermediate voltage is minimum.

2. The wideband locking circuit of claim 1, wherein said signal conditioning circuit comprises a frequency detector, a phase detector, a first voltage-to-current conversion module, a second voltage-to-current conversion module, an analog loop filter, and an analog-to-digital converter;

wherein the voltage controlled oscillator, the frequency detector, the first voltage-to-current conversion module, the analog loop filter, and the analog-to-digital converter form the frequency locked loop; and

wherein the voltage controlled oscillator, the phase detector, the second voltage to current conversion module, the analog loop filter, and the analog-to-digital converter form the phase locked loop.

3. The wideband locking circuit of claim 1, wherein said frequency detector comprises:

and the identification bit generating circuit comprises a buffer, a filter and a comparator which are sequentially connected, wherein the identification bit generating circuit is configured to process a target signal representing the comparison result and output the adjustment identification bit so as to determine the turning frequency band code of the digital frequency band control signal based on the adjustment identification bit.

4. The wideband locking circuit of claim 2, wherein said frequency detector further comprises:

a lock detection circuit, which comprises a not gate, a first delayer, a nand gate, a second delayer, a nor gate and a counter, wherein an input end of the not gate and an input end of the first delayer are respectively used as input ends of the lock detection circuit, an output end of the not gate and an output end of the first delayer are respectively connected to an input end of the nand gate, an output end of the nand gate is connected to one input end of the nor gate and an input end of the second delayer, an output end of the second delayer is connected to the other input end of the nor gate, and an output end of the nor gate is connected to the counter and is used as an output end of the lock detection circuit;

wherein the lock detection circuit is configured to:

processing the high-speed signal and the clock signal acquired by the input end of the clock signal to obtain a locking identification signal;

outputting the locking identification signal through an output end of the locking identification signal; and

counting the number of rising edges of the lock identification signal within a predetermined period of time by the counter.

5. An adjusting method based on the broadband locking circuit according to claim 4, comprising:

determining a turning frequency band code of the digital frequency band control signal based on the adjustment identification bit; and

and performing regulation and control operation on the digital frequency band control signal by taking the turning frequency band code as a reference so as to screen out an optimal frequency band code from a frequency band code set containing the turning frequency band code.

6. The method of adjusting of claim 5, wherein performing the conditioning operation on the digital band control signals to filter out an optimal frequency band code comprises:

assigning any frequency band code in the frequency band code set to the digital frequency band control signal in each regulation process of the digital frequency band control signal;

sequentially starting the first voltage-to-current conversion module and the second voltage-to-current conversion module to work;

counting the number of rising edges of the locking identification signal and the voltage value of the analog voltage control signal in a preset time; and

and determining the frequency band code corresponding to the digital frequency band control signal as an optimal frequency band code in response to the statistical result meeting a preset condition.

7. The method of claim 6, wherein sequentially activating the first voltage-to-current conversion module and the second voltage-to-current conversion module comprises:

gradually adjusting the current control bit related to the first voltage-to-current conversion module from high to low and gradually adjusting the current control bit related to the second voltage-to-current conversion module from high to low to high until the first voltage-to-current conversion module is completely closed and the frequency locked loop is opened and the second voltage-to-current conversion module is completely opened and the phase locked loop is established; or

After the first voltage-to-current conversion module is closed, the second voltage-to-current conversion module is started; or

And reducing the current of the first voltage-to-current conversion module to a minimum gear, and then starting the second voltage-to-current conversion module.

8. The adjustment method according to any one of claims 5 to 7, wherein determining the passband code of the digital band control signal based on the adjustment flag comprises:

selecting a middle frequency band code in a plurality of frequency band codes as a reference frequency band code of the digital frequency band control signal; and

and circularly adjusting up or down the reference frequency band code according to the output result of the adjustment identification bit to screen the maximum frequency band code which enables the adjustment identification bit to output the appointed result, and determining the maximum frequency band code as the turning frequency band code.