CN114079381B

CN114079381B - Flyback power conversion circuit and active clamping buffer thereof

Info

Publication number: CN114079381B
Application number: CN202010835787.9A
Authority: CN
Inventors: 林梓诚
Original assignee: Richtek Technology Corp
Current assignee: Richtek Technology Corp
Priority date: 2020-08-19
Filing date: 2020-08-19
Publication date: 2023-06-27
Anticipated expiration: 2040-08-19
Also published as: CN114079381A

Abstract

A flyback power conversion circuit and an active clamp buffer thereof. The flyback power conversion circuit comprises a power transformer, a primary side control circuit, a secondary side control circuit and an active clamping buffer. The active clamping buffer comprises a buffer switch and a control signal generating circuit. The control signal generating circuit is used for controlling the buffer switch to be conducted in a flexible switching period in a non-conducting period of the primary side switch in a switching period of the switching signal, so that the primary side switch can realize flexible switching. The starting time point of the flexible switching period is determined according to the current threshold value, so that the secondary side current is not lower than the current threshold value at the starting time point, and the secondary side control circuit keeps the synchronous rectification switch on at the starting time point. The secondary side control circuit does not conduct the synchronous rectification switch when the secondary side current is lower than the current threshold value.

Description

Flyback power conversion circuit and active clamping buffer thereof

Technical Field

The present invention relates to a flyback power conversion circuit, and more particularly to a flyback power conversion circuit for flexibly switching a primary side switch. The invention also relates to an active clamping buffer of the flyback power conversion circuit.

Background

Fig. 1A and 1B disclose a prior art flyback power conversion circuit (flyback power conversion circuit 1) with active clamping. The flyback power conversion circuit 1 is configured to convert an input voltage VI into an output voltage VO, and includes a transformer 10, a primary side switch S1, a snubber switch S2, and a snubber capacitor Cr. As shown in fig. 1A, the primary switch S1 operates according to the primary switch control signal S1C to switch the primary winding W1 in the transformer 10 to convert the input power to the output power. The input power supply includes an input voltage VI and an input current IIN, and the output power supply includes an output voltage VO and an output current IOUT. The secondary winding W2 generates an output voltage VO and an output current IOUT at an output node OUT for supplying an output power to the load circuit 40. When the primary switch S1 is turned on, electric energy is stored in the primary winding W1; when the primary switch S1 is not turned on, the electric energy stored in the primary winding W1 is transferred from the primary winding W1 to the secondary winding W2, and the output voltage VO is generated at the output node OUT.

The buffer switch S2 and the buffer capacitor Cr form an active clamp branch. Referring to fig. 1B, signal waveforms of the primary switch control signal S1C and the buffer control signal S2C are shown. As shown in fig. 1B, the active clamping branch is turned on (when the primary switch control signal S1C is at a low level) when the primary switch S1 is not turned on (when the buffer control signal S2C is at a high level), so that the energy stored in the leakage inductance Lr of the primary winding W1 when the primary switch S1 is turned on (when the primary switch control signal S1C is at a high level) can be discharged and stored in the buffer capacitor Cr through the active clamping branch, so as to avoid the damage to circuit elements due to the excessively high pulse voltage caused by the switching of the primary switch S1. In addition, before the primary switch S1 is turned on, the parasitic capacitor Coss of the primary switch S1 can be discharged by the energy stored in the snubber capacitor Cr, so that the primary switch S1 is flexibly switched when turned on, and in the prior art, the switching of the primary switch S1 and the snubber switch S2 is substantially opposite to each other, as shown in fig. 1B.

The excitation inductance Lm is an ideal inductance in the primary winding W1, that is, an inductance excluding the leakage inductance Lr, and the excitation current Im is a current flowing through the excitation inductance Lm. The primary current IP is a current flowing through the primary winding (including the excitation inductance Lm and the leakage inductance Lr). The ratio of the number of turns of the primary winding W1 to the secondary winding W2 is n:1. the voltage across VDS of the primary side switch is the voltage difference between the drain terminal and the source terminal of the primary side switch S1.

The disadvantage of the prior art shown in fig. 1A and 1B is that, since the dead time Td (dead time) between the conduction of the snubber switch S2 and the primary switch S1 is generally a fixed time, the conduction time of the primary switch S1 may not fall at the time point of zero voltage switching (i.e. the time point when the parasitic capacitor Coss is discharged), and may lead or delay, a cyclic resonance is formed between the exciting inductor Lm and the snubber capacitor Cr, which causes power loss.

For further related prior art, see US5570278, CN101572490B and US9954456.

Compared with the prior art, the buffer switch S2 can be adjusted to correspond to the starting time and the ending time of conduction in the flexible switching period, so that the primary side switch S1 can realize the buffering effect in the buffering period and realize the flexible switching in the flexible switching period, thereby reducing the power loss and improving the power conversion efficiency.

In addition, compared with the prior art shown in fig. 1A and 1B, the present invention adjusts the starting point and the ending point of the flexible switching period according to the current threshold related to the non-conducting secondary side synchronous rectification switch, so as to reduce the output current IOUT, and the power loss caused when the primary side switch S1 is non-conducting.

In view of the above, the present invention provides a flyback power conversion circuit and an active clamp buffer thereof, which can reduce the power loss caused by the output current and improve the power conversion efficiency while avoiding damaging the circuit element by using the buffer capacitor.

Disclosure of Invention

In one aspect, the present invention provides a flyback power conversion circuit for converting an input voltage to generate an output voltage, the flyback power conversion circuit comprising: a power transformer electrically coupled between the input voltage and the output voltage; a primary side control circuit for generating a switching signal to control a primary side switch to switch a primary side winding of the power transformer, wherein the primary side winding is coupled to the input voltage; a secondary side control circuit for controlling a synchronous rectification switch connected in series with the secondary side winding according to a secondary side current flowing through the secondary side winding of the power transformer, wherein the secondary side control circuit does not conduct the synchronous rectification switch when the secondary side current is lower than a current threshold; and an active clamping buffer, comprising a buffer switch and a control signal generating circuit, wherein the control signal generating circuit is used for controlling the buffer switch to be conducted during a flexible switching period in a non-conducting period of the primary side switch in a switching period of the switching signal so as to realize flexible switching of the primary side switch; the buffer switch is connected in series with a buffer capacitor and then connected in parallel with the primary winding; the power transformer senses magnetism when the primary side switch is conducted, and transmits energy obtained when the primary side switch is conducted to the output voltage when the primary side switch is turned to be non-conducting; the starting time of the flexible switching period is determined according to the current threshold, so that the secondary side current is not lower than the current threshold at the starting time, and the secondary side control circuit keeps the synchronous rectification switch on at the starting time.

In another aspect, the present invention provides an active clamp buffer for use in a flyback power conversion circuit for generating a switching signal to control a primary side switch to switch a primary side winding of a power transformer to convert an input voltage to an output voltage, the active clamp buffer comprising: a buffer switch connected in series with a buffer capacitor and then connected in parallel with the primary winding; and a control signal generating circuit for controlling the buffer switch to be turned on during a flexible switching period in a non-conduction period of the primary side switch in a switching period of the switching signal, so that the primary side switch realizes flexible switching; the secondary side control circuit in the flyback power supply conversion circuit is used for controlling a synchronous rectification switch connected with the secondary side winding in series according to a secondary side current flowing through the secondary side winding of the power transformer, and the secondary side control circuit does not conduct the synchronous rectification switch when the secondary side current is lower than a current threshold value; the starting time of the flexible switching period is determined according to the current threshold, so that the secondary side current is not lower than the current threshold at the starting time, and the secondary side control circuit keeps the synchronous rectification switch on at the starting time.

In a preferred embodiment, the flyback power conversion circuit operates in a boundary conduction mode (boundary conduction mode, BCM) or a discontinuous conduction mode (discontinuous conduction mode, DCM).

In a preferred embodiment, the buffer capacitor is configured to charge the buffer capacitor with a leakage current of the primary winding during the non-conductive period of the primary switch, different from a buffer period during the soft switching period, in the switching period of the switching signal, so as to transfer an electric energy stored in a leakage current of the primary winding during a conductive period of the primary switch to the buffer capacitor.

In a preferred embodiment, the control signal generating circuit adaptively adjusts an end point of the flexible switching period according to a voltage across the primary switch.

In a preferred embodiment, the control signal generating circuit comprises: a secondary side current simulation circuit for generating a secondary side current simulation signal to simulate the secondary side current according to the voltage across the primary side winding and an excitation inductance value of the primary side winding; and a comparison circuit coupled to the secondary side current analog circuit for generating a flexible switching period determination signal according to the secondary side current analog signal, a primary side current peak value and the current threshold value to determine the start time and the end time of the flexible switching period; the primary side current is the current flowing through the primary side winding in an on period of the primary side switch in the switching cycle.

In a preferred embodiment, the comparison circuit determines the starting point according to the secondary current analog signal, the peak value of the primary current and the current threshold value; and the comparison circuit determines the ending time point according to the secondary side current simulation signal and the peak value of the primary side current.

In a preferred embodiment, the secondary-side current emulation circuit includes: a voltage-to-current conversion circuit for generating a charging current, comprising: a switching resistor; an amplifier circuit coupled to the switching resistor for generating a switching current flowing through the switching resistor according to a voltage across the primary winding and a resistance value of the switching resistor, wherein the switching current is proportional to the voltage across the primary winding; and a current mirror circuit coupled to the amplifier circuit for mirroring the converted current to generate a charging current; and a simulated capacitor coupled to the current mirror circuit for charging the simulated capacitor according to the charging current to generate the secondary winding current simulated signal.

In a preferred embodiment, the control signal generating circuit further comprises: a sample-hold circuit coupled to the comparator circuit for sampling and holding the peak value of the primary current to generate an end threshold value for input to the comparator circuit; and a bias circuit coupled to the sample-and-hold circuit for superimposing the ending threshold with a bias value associated with the current threshold to generate a starting threshold; wherein the comparison circuit compares the secondary side current analog signal with the initial threshold value to determine the initial time point; wherein the comparison circuit compares the secondary side current analog signal with the ending threshold value to determine the ending time point.

In a preferred embodiment, the secondary-side current analog circuit adaptively adjusts the resistance value of the switching resistor and/or the capacitance value of the analog capacitor according to the voltage across the primary-side switch in a set period immediately after the flexible switching period, so that the primary-side switch realizes zero-voltage switching; wherein the set period is related to the time required for the voltage across the primary switch to drop from a charging voltage at the end point to zero voltage.

In a preferred embodiment, the secondary side current is not lower than the current threshold during the flexible switching period, and the secondary side control circuit keeps the synchronous rectification switch on during the flexible switching period.

The objects, technical contents, features and effects achieved by the present invention will be more readily understood from the following detailed description of specific embodiments.

Drawings

FIGS. 1A and 1B illustrate a prior art flyback power conversion circuit with active clamping.

Fig. 2A is a schematic diagram of an embodiment of a flyback power conversion circuit according to the present invention.

Fig. 2B and 2C are schematic signal waveforms of related signals according to the embodiment shown in fig. 2A.

Fig. 3 is a schematic diagram of an embodiment of a control signal generating circuit according to the present invention.

FIG. 4 is a schematic diagram of a control signal generating circuit according to a more specific embodiment of the present invention.

Fig. 5 shows a schematic diagram of an embodiment of a control signal generating circuit 51 according to the present invention.

Fig. 6 shows a signal waveform diagram of a correlation signal according to the present invention.

Description of the symbols in the drawings

1,3: flyback power conversion circuit

10: power transformer

20: primary side control circuit

30: secondary side control circuit

40: load circuit

50: active clamp buffer

51: control signal generating circuit

511: secondary side current imitation circuit

513: comparison circuit

515: sample-and-hold circuit

517: bias circuit

5111: voltage-current conversion circuit

5113: current mirror circuit

A1, A2, A3: amplifier circuit

Ci: input capacitance

Cr: buffer capacitor

Ct: imitation capacitor

Coss: parasitic capacitance

D1: parasitic diode

Icg: charging current

Icr: leakage inductance current

Icv: conversion current

IDS: electric current

IIN: input current

Im: electric current

IP: primary side current

IOUT: output current

IS: secondary side current

Ith: current threshold value

Lm: exciting inductor

Lr: leakage inductance

n: ratio of turns

OUT: output node

PWML: pulse width modulated signal

Pre_zcs: initiation determination signal

PSN: buffer pulse wave

PSS: flexibly switching pulses

REF: reference potential

Rt: switching resistor

S1: primary side switch

S1C: primary side switch control signal

S2: buffer switch

S2C: buffer control signal

S3: synchronous rectification switch

S3C: synchronous rectification control signal

S4: switch

S5: transistor with a high-voltage power supply

t1, t2, t3, t4, t4', t5, t6: time point

Td: time of empty lag

TSN: buffer period

TSS: during flexible switching

Vbs: bias value

Vch: charging voltage

Vct: secondary side current analog signal

Vcta, vctb: current analog signal

Vcr: cross-over pressure

VDS: cross-over pressure

VI: input voltage

VO: output voltage

Vpk: end threshold

Vpri: threshold of onset

Vro, vsr: cross-over pressure

W1: primary side winding

W2: secondary side winding

ZCS: end decision signal

Detailed Description

The drawings in the present invention are schematic and are mainly intended to represent coupling relationships between circuits and relationships between signal waveforms, which are not drawn to scale.

Fig. 2A shows an embodiment of the flyback power conversion circuit (flyback power conversion circuit 3) according to the present invention. The flyback power conversion circuit 3 includes a power transformer 10, a primary side switch S1, a snubber capacitor Cr, a primary side control circuit 20, a secondary side control circuit 30, a synchronous rectification switch S3, and an active clamp buffer 50. As shown in fig. 2A, the power transformer 10 includes a primary winding W1 and a secondary winding W2. The primary winding W1 is coupled to an input power source, wherein the input power source includes an input voltage VI and an input current IIN. For convenience of description, fig. 2A shows that the primary winding W1 has leakage inductance Lr and excitation inductance Lm. The secondary winding W2 is coupled to the output node OUT. The primary switch S1 is coupled to the primary winding W1 for switching the primary winding W1 to convert the input power, so that the secondary winding W2 generates an output power at the output node OUT for supplying to the load circuit 40; the output power supply includes an output voltage VO and an output current IOUT.

The primary winding W1 has leakage inductance Lr, which is referred to herein as leakage inductance (leakage inductance), and is derived from a power transformer that is not completely coupled, in a power transformer that is not ideal in practice, the coupling coefficient between the primary winding and the secondary winding is smaller than 1, and some windings in the power transformer do not have a transformation effect, and the inductance of this part of windings is referred to as leakage inductance. In an ideal case, the primary winding and the secondary winding of the power transformer are fully coupled (coupling coefficient equal to 1, indicated by the excitation inductance Lm in fig. 2A). That is, in an ideal power transformer, the inductance value of the leakage inductance is zero, but in an actual circuit, the ideal power transformer does not exist; that is, in an actual circuit, leakage inductance is necessarily present in the primary winding of the power transformer, which is well known to those skilled in the art, and will not be described herein.

With continued reference to fig. 2A and with reference to fig. 2B, fig. 2B shows a schematic signal waveform of the relevant signal according to the present invention. As shown in fig. 2A, the power transformer 10 is electrically coupled between the input voltage VI and the output voltage VO. The primary control circuit 20 is configured to generate a switching signal S1C to control the primary switch S1 to switch the primary winding W1 of the power transformer 10, wherein the primary winding W1 is coupled to the input voltage VI. The secondary control circuit 30 IS configured to generate a synchronous rectification control signal S3C according to a secondary current IS flowing through the secondary winding W2 of the power transformer 10 (in this embodiment, the secondary current IS equal to the output current IOUT), so as to control the synchronous rectification switch S3 connected in series with the secondary winding W2, and the secondary control circuit 30 does not turn on the synchronous rectification switch S3 when the secondary current IS (i.e. the output current IOUT) IS lower than the current threshold Ith. The secondary side control circuit 30 generates the synchronous rectification control signal S3C according to the voltage Vsr across the synchronous rectification switch S3, for example, to correspond to the secondary side current IS.

The active clamp buffer 50 includes a buffer switch S2 and a control signal generating circuit 51. The control signal generating circuit 51 is configured to generate the flexible switching pulse PSS in the buffer control signal S2C to control the buffer switch S2 to be turned on during a flexible switching period TSS (shown in fig. 2B, time t4 to t 5) in a non-conductive period (shown in fig. 2B, time t2 to time t 6) of the primary switch S1 in one switching cycle (shown in fig. 2B, time t1 to time t 6) of the switching signal S1C, so that the primary switch S1 is flexibly switched (soft switching).

Wherein the snubber switch S2 is connected in series with the snubber capacitor Cr and then connected in parallel with the primary winding W1. The power transformer 10 is magnetically induced when the primary switch S1 is turned on, and transfers energy obtained when the primary switch S1 is turned off to the output voltage VO. The starting point (time t 4) of the flexible switching period TSS (time t4 to time t5 shown in fig. 2B) IS determined according to the current threshold Ith, so that the secondary side current IS (equal to the output current IOUT) IS not lower than the current threshold Ith at the starting point (time t4 shown in fig. 2B), and the secondary side control circuit 30 keeps the synchronous rectification switch S3 turned on at the starting point (time t4 shown in fig. 2B).

It should be noted that "flexibly switching" means that before the transistor (for example, corresponding to the primary side switch S1) is turned on, the residual voltage of the parasitic capacitance (for example, corresponding to the capacitance Coss) of the transistor is discharged to a lower voltage through the energy-free discharging path (for example, corresponding to the primary side winding W1) by the discharging current (for example, corresponding to the flexible switching period TSS, the current flowing out of the parasitic capacitance Coss generated by the on buffer switch S2), so that when the transistor is turned on, the drain-source voltage (for example, corresponding to the voltage across VDS of the primary side switch S1) is reduced to a lower voltage, and the charge stored in the parasitic capacitance (for example, corresponding to the parasitic capacitance Coss of the primary side switch S1) is not discharged by the on-resistance of the transistor in the process, so that the power conversion efficiency can be improved. Taking fig. 2A as an example, before the primary switch S1 is turned on, the parasitic capacitor Coss of the primary switch S1 may be discharged by the energy stored in the auxiliary capacitor Cr, so that the voltage across VDS of the primary switch S1 is reduced to substantially zero voltage at the starting point of the primary switch S1 on, and the optimal condition in flexible switching, i.e., zero voltage switching (Zero Voltage Switching, ZVS) is achieved.

In addition, the buffer capacitor Cr is further used for controlling the buffer pulse PSN in the buffer control signal S2C generated by the signal generating circuit 51 to turn on the buffer switch S2 during the switching period of the switching signal S1C (as shown in fig. 2B and 2C, and at time points t1 to t6 shown in fig. 2B and 2C), and for charging the buffer capacitor Cr with the leakage inductance current Icr of the primary winding W1 during the non-conductive period of the primary switch S1 (as shown in fig. 2B and 2C, and for transmitting the electric energy stored in the non-conductive period of the primary switch S1 (as shown in time points t1 to t6 shown in fig. 2B and 2C) to the buffer capacitor Cr, and for avoiding the excessive pulse voltage caused by the switching of the primary switch S1 from damaging the circuit element and increasing the voltage Vcr of the buffer capacitor Cr for the subsequent flexible switching period TSSs.

In a preferred embodiment, the flyback power conversion circuit 3 operates in a boundary conduction mode (boundary conduction mode, BCM) or discontinuous conduction mode (discontinuous conduction mode, DCM), wherein BCM and DCM are well known to those skilled in the art and will not be described herein.

Taking the flyback power conversion circuit 3 shown in fig. 2A as an example; as shown in fig. 2A, and referring to fig. 2C, fig. 2C shows a schematic signal waveform of the voltage across VDS and the secondary current IS of the primary switch S1 in one switching cycle (time t1 to t6 shown in fig. 2C) of the switching signal S1C in fig. 2B. In a preferred embodiment, the control signal generating circuit 51 adaptively adjusts the ending time t5 of the segment flexible switching period TSS (as shown in fig. 2C, time t4 to time t 5) according to the voltage across VDS of the primary switch S1.

When the secondary side current IS flowing through the secondary side winding W2 IS lower than the current threshold Ith, the secondary side control circuit 30 does not turn on the synchronous rectification switch S3 connected in series with the secondary side winding W2, so that the secondary side current IS cannot flow through the transistor in the synchronous rectification switch S3 but flows through the parasitic diode D1 in the synchronous rectification switch S3. In this way, before the primary switch S1 IS turned on (as shown in fig. 2C, at time t 6) (as shown by the thick dotted line between time t4' and time t6 in fig. 2C), the secondary current IS flows through the parasitic diode D1, which causes a higher power loss than the current flowing through the transistor, and reduces the power conversion efficiency of the flyback power conversion circuit 3.

In the present embodiment, the on period of the buffer switch S2, i.e. the control time points t4 and t5, IS controlled to enable the primary side switch S1 to realize flexible switching (soft switching), i.e. the flexible switching period TSS (as shown in fig. 2B, time points t4 to t 5), and the inductive coupling effect of the power transformer 10 IS utilized to increase the secondary side current IS to be not lower than the current threshold Ith at time point t4, so that the secondary side control circuit 30 still keeps the synchronous rectifying switch S3 on at the initial time point t4 of the flexible switching period TSS, so that the secondary side current IS flows through the transistor switch in the synchronous rectifying switch S3, thereby reducing the power loss and improving the power conversion efficiency of the flyback power conversion circuit 3. And according to the voltage-across VDS, the end time t5 is adaptively adjusted to ensure that the voltage-across VDS is substantially zero before the primary switch S1 is turned on, so as to realize zero-voltage switching with optimal effect in flexible switching. Since the primary winding W1, the primary switch S1, the snubber switch S2, and the snubber capacitor Cr are all preset elements, when the snubber switch S2 is turned on during the flexible switching period TSS, the time point when the voltage across VDS of the primary switch S1 drops to zero voltage can be predicted according to the voltage across VDS at the time point t 4. Therefore, the control signal generating circuit 51 adaptively adjusts the ending time t5 of the segment flexible switching period TSS (as shown in fig. 2C, from time t4 to time t 5) according to the voltage across VDS of the primary side switch S1 at time t4, so as to realize zero voltage switching and improve the power conversion efficiency.

According to the present invention, taking the flyback power conversion circuit 3 shown in fig. 2A as an example, the secondary control circuit 30 IS configured to control the synchronous rectification switch S3 connected in series with the secondary winding W2 according to the secondary current IS flowing through the secondary winding W2 of the power transformer 10 (in this embodiment, the secondary current IS equal to the output current IOUT), and the secondary control circuit 30 does not turn on the synchronous rectification switch S3 when the secondary current IS (i.e. the output current IOUT) IS lower than the current threshold value Ith.

As shown in fig. 2B, the flyback power supply circuit 3 operates in a boundary conduction mode (Boundary Conduction Mode, BCM). Of course, according to the present invention, the flyback power supply circuit 3 can also operate in the discontinuous conduction mode (discontinuous conduction mode, DCM), and the present invention IS applicable as long as the secondary side current IS IS reduced to the zero current operation mode in the non-conduction period of the primary side switch S1 in one switching cycle of the switching signal S1C.

In a preferred embodiment, the secondary side current IS not lower than the current threshold Ith during the flexible switching period TSS, and the secondary side control circuit 30 keeps the synchronous rectification switch S3 turned on during the flexible switching period TSS. According to the present invention, as long as the secondary side current IS not lower than the current threshold Ith at the starting time t4, the primary side switch S1 can be flexibly switched, and the secondary side current IS flows through the transistor switch in the synchronous rectification switch S3, so that the power loss IS reduced, and the power conversion efficiency of the flyback power conversion circuit 3 IS improved. In a preferred embodiment, the secondary side current IS not lower than the current threshold Ith during the flexible switching period TSS, and the secondary side control circuit 30 keeps the synchronous rectification switch S3 turned on during the flexible switching period TSS, so as to achieve better flexible switching and higher power conversion efficiency.

It should be noted that, because the parasitic effect of the circuit components itself or the matching between the components is not necessarily ideal, although the parasitic capacitor Coss is discharged to 0V to achieve zero voltage switching, it may not be possible to accurately discharge to 0V, but only near 0V, that is, according to the present invention, it is acceptable that there is a certain error between the voltage across VDS and 0V after the parasitic capacitor Coss is discharged due to the circuit non-ideality, that is, the foregoing discharging means to "substantially" 0V, and other references herein are the same.

As shown in fig. 2B, signal waveforms of the buffer control signal S2C, the switching signal S1C, the current Im flowing through the magnetizing inductance Lm, the current IDS flowing through the primary side switch S1, the secondary side current IS, the current IC flowing through the buffer capacitor Cr, and the voltage across VDS of the primary side switch are shown in fig. 2B. The voltage Vro across the primary winding W1 is the turns ratio n multiplied by the output voltage VO, and is proportional to the output voltage VO.

Fig. 3 shows a schematic diagram of an embodiment of a control signal generating circuit (control signal generating circuit 51) according to the present invention. As shown in the figure, the control signal generating circuit 51 includes a secondary-side current analog circuit 511 and a comparison circuit 513. The secondary-side current simulation circuit 511 IS configured to generate a secondary-side current simulation signal to simulate the secondary-side current IS according to the voltage Vro across the primary winding W1 and the magnetizing inductance Lm of the primary winding W1. The comparison circuit 513 is coupled to the secondary-side current analog circuit 511 for generating a flexible switching period determining signal according to the secondary-side current analog signal Vct, the peak value of the primary-side current IP and the current threshold Ith to determine a start time t4 and an end time t5 of the flexible switching period TSS. In the switching period (time t1 to t6 shown in fig. 2B and 2C), the current flowing through the primary winding W1 is substantially equal to the current Im flowing through the magnetizing inductance Lm in the on period (time t1 to t2 shown in fig. 2B and 2C) of the primary switch S1. Since the peak value of the primary current IP IS proportional to the peak value of the secondary current IS according to the characteristic of the inductor current, the comparison circuit 513 obtains the peak value of the secondary current IS from the peak value of the primary current IP.

In a preferred embodiment, the comparison circuit 513 determines the ending time point (as shown in time t5 in fig. 2B and 2C) according to the peaks of the secondary-side current analog signal Vct and the primary-side current IP; the comparison circuit 513 determines a start point (as shown in fig. 2B and 2C, point t 4) according to the secondary current analog signal Vct and the start threshold Vpri. The start threshold Vpri is a result of superimposing the end threshold Vpk on the bias value Vbs related to the current threshold Ith.

Fig. 4 shows a schematic diagram of a control signal generating circuit 51 according to a more specific embodiment of the invention. As shown in the figure, the control signal generating circuit 51 includes a secondary-side current analog circuit 511 and a comparison circuit 513. The secondary-side current analog circuit 511 includes a voltage-to-current conversion circuit 5111, an analog capacitor Ct, and a switch S4. The voltage-current conversion circuit 5111 is used for generating a charging current Icg, and has a conversion resistor Rt, an amplifier circuit A1 and a current mirror circuit 5113. The amplifier circuit A1 is coupled to the converting resistor Rt for generating a converting current Icv flowing through the converting resistor Rt according to the voltage Vro across the primary winding W1 and the resistance value of the converting resistor Rt, wherein the converting current Icv is proportional to the voltage Vro across the primary winding W1. The current mirror circuit 5113 is coupled to the amplifier circuit A1 for generating the charging current Icg according to the conversion current Icv in a mirroring manner.

The analog capacitor Ct is coupled to the current mirror 5113 for charging the analog capacitor Ct according to the charging current Icg to generate the secondary winding current analog signal Vct. The switch S4 may be omitted, and receives the pwm signal PWML substantially in phase with the switching signal S1C to determine that an input end of the comparing circuit 513 is shorted to the reference potential REF when the primary switch S1 is turned on, so that the input end of the comparing circuit 513 is directly electrically connected to the reference potential REF when the primary switch S1 is turned on to reset the secondary winding current analog signal Vct when the primary switch S1 is turned on. The reference potential REF may be, for example, a ground potential.

As shown in fig. 4, the amplifier circuit A1 and the transistor S5 form a unit gain buffer (unit gain buffer) circuit to generate a current Icv according to a voltage Vro across the primary winding W1. The current mirror 5113 includes, for example, a transistor S5 and a current source, and mirrors the current Icv to the charging current Icg. Since the current Icv is adjusted according to the conversion resistor Rt, the charging current Icg and thus the secondary winding current analog signal Vct can be adjusted by adjusting the resistance value of the conversion resistor Rt. In addition, the charge current Icg charges the analog capacitor Ct to generate the secondary winding current analog signal Vct. The capacitance value of the analog capacitor Ct is adjusted, and the secondary winding current analog signal Vct may also be adjusted.

With continued reference to fig. 4, the comparison circuit 513 includes an amplifier circuit A2 and an amplifier circuit A3. The amplifier circuit A2 compares the secondary-side current analog signal Vct with a termination threshold Vpk associated with a peak value of the primary-side current IP to generate a termination determination signal ZCS, and determines a termination point (as shown in fig. 2B and 2C, point t 5). The amplifier circuit A3 compares the secondary current analog signal Vct with the start threshold Vpri to generate a start determination signal pre_zcs to determine a start point (as shown in fig. 2B and fig. 2C, point t 4). The start threshold Vpri is generated by superimposing the end threshold Vpk and the bias voltage Vbs related to the current threshold Ith, so that the synchronous rectification switch S3 is kept on at the start point (as shown in fig. 2B and fig. 2C at time t 4).

Fig. 5 shows a schematic diagram of an embodiment of a control signal generating circuit 51 according to the present invention. The present embodiment is intended to explain that the control signal generating circuit 51 includes a sample-and-hold circuit 515 and a bias circuit 517 in addition to the secondary-side current analog circuit 511 and the comparison circuit 513. The sample-and-hold circuit 515 is coupled to the comparing circuit 513 for sampling and holding the peak value of the primary current IP, and generating an ending threshold Vpk for inputting to the comparing circuit 513. The bias circuit 517 is coupled to the sample-and-hold circuit 515 for superimposing the ending threshold Vpk with the bias value Vbs associated with the current threshold Ith to generate the starting threshold Vri.

Fig. 6 shows a signal waveform diagram of a correlation signal according to the present invention. Fig. 6 is a schematic diagram for explaining that the control signal generating circuit 51 adaptively adjusts the resistance value of the converting resistor Rt and/or the capacitance value of the dummy capacitor Ct according to the voltage across VDS of the primary switch S1 in the set period Tz immediately after the flexible switching period TSS, so that the primary switch S1 realizes zero voltage switching; the set period Tz corresponds to the time required for the voltage Vch of the primary switch S1 to drop to zero from the end point t 5.

The charging voltage Vch is a sum of the input voltage VI and the voltage Vcr across the snubber capacitor Cr after charging the snubber capacitor Cr with the leakage inductance current Icr of the primary winding W1 in the non-conductive period (the period from the time t2 to the time t 6) of the primary switch S1, which is different from the snubber period TSN of the soft switching period TSS. The sum of the voltage across Vcr and the input voltage VI is TSS during the soft switching period, because of the conduction of the snubber switch S2, the snubber capacitor Cr is electrically connected to the primary switch S1, so that the voltage across VDS of the primary switch S1 reaches the charging voltage Vch after charging on the parasitic capacitor.

In a preferred embodiment, at the time t5 when the buffer switch S2 is turned off and the time t6 when the next primary switch S1 is turned on, the voltage across VDS of the primary switch S1 is discharged from the charging voltage Vch to zero through the energy-free discharging path (corresponding to the primary winding W1, for example), and charges are charged back into the energy-free element (such as the input capacitor Ci), so that when the primary switch S1 is turned on, the drain-source voltage (corresponding to the voltage across VDS of the primary switch S1) is reduced to zero, and the charge stored in the parasitic capacitor Coss is not discharged with the on-resistance of the primary switch S1 in the process, thereby improving the power conversion efficiency.

In fig. 6, the current analog signal Vcta of the broken line in the secondary current analog signal Vct indicates that the TSS is delayed during the flexible switching period. When the primary switch S1 is turned on due to the delay of the TSS during the flexible switching period, the voltage across VDS of the primary switch S1 is not discharged to zero voltage, and zero voltage switching cannot be achieved, so that the power conversion efficiency is reduced. On the other hand, in the secondary-side current analog signal Vct, the current analog signal Vctb of the broken line indicates a case where the TSS is advanced during flexible switching. When the TSS is advanced during flexible switching, on the one hand, because of the cyclic resonance of the LC circuit, the primary side switch S1 is turned on, the voltage across VDS of the primary side switch S1 is not discharged to zero voltage, zero voltage switching cannot be realized, and the power conversion efficiency is reduced; in addition, the synchronous rectification switch S3 IS not turned on earlier, so that the secondary current IS flows through the parasitic diode D1, resulting in higher power loss and reduced power conversion efficiency of the flyback power conversion circuit 3. Since the characteristics of the circuit element are known, the set period Tz, that is, the time required for the voltage Vch of the voltage across VDS of the primary switch S1 to drop from the end point t5 to zero voltage can be calculated, and the resistance value of the converting resistor Rt and/or the capacitance value of the dummy capacitor Ct can be adjusted accordingly, so that the primary switch S1 realizes zero voltage switching.

The present invention has been described in terms of the preferred embodiments, but the above description is only for the purpose of easily understanding the present invention by those skilled in the art, and is not intended to limit the scope of the claims of the present invention. The embodiments described are not limited to single applications but may be combined, for example, two or more embodiments may be combined, and portions of one embodiment may be substituted for corresponding components of another embodiment. In addition, various equivalent changes and various combinations will be apparent to those skilled in the art, and for example, the term "processing or calculating based on a signal or generating an output result" in the present invention is not limited to the processing or calculating based on the signal itself, but includes performing voltage-to-current conversion, current-to-voltage conversion, and/or scaling conversion of the signal, if necessary, and then processing or calculating based on the converted signal to generate an output result. It will thus be appreciated that those skilled in the art will be able to devise various arrangements which, although not explicitly described herein, embody the principles of the invention and are thus equally well suited to the particular use contemplated. Accordingly, the scope of the invention should be assessed as that of the above and all other equivalent variations.

Claims

1. A flyback power conversion circuit for converting an input voltage to generate an output voltage, the flyback power conversion circuit comprising:

a power transformer electrically coupled between the input voltage and the output voltage;

a primary side control circuit for generating a switching signal to control a primary side switch to switch a primary side winding of the power transformer, wherein the primary side winding is coupled to the input voltage;

a secondary side control circuit for controlling a synchronous rectification switch connected in series with the secondary side winding according to a secondary side current flowing through the secondary side winding of the power transformer, wherein the secondary side control circuit does not conduct the synchronous rectification switch when the secondary side current is lower than a current threshold; and

an active clamping buffer comprises a buffer switch and a control signal generating circuit, wherein the control signal generating circuit is used for controlling the buffer switch to be conducted in a flexible switching period in a non-conducting period of the primary side switch in a switching period of the switching signal so as to realize flexible switching of the primary side switch;

the buffer switch is connected with a buffer capacitor in series and then connected with the primary winding in parallel;

The power transformer senses magnetism when the primary side switch is conducted, and transmits energy obtained when the primary side switch is conducted to the output voltage when the primary side switch is turned to be non-conducting;

the starting time of the flexible switching period is determined according to the current threshold, so that the secondary side current is not lower than the current threshold at the starting time, and the secondary side control circuit keeps the synchronous rectification switch on at the starting time.

2. The flyback power conversion circuit of claim 1 wherein the flyback power conversion circuit operates in a boundary conduction mode or a discontinuous conduction mode.

3. The flyback power conversion circuit of claim 1 wherein the snubber capacitor is configured to charge the snubber capacitor with a leakage current of the primary winding during the non-conductive period of the primary switch, different from a snubber period during the soft switching, during the switching period of the switching signal, and transfer an electrical energy stored by a leakage current of the primary winding during a conductive period of the primary switch to the snubber capacitor.

4. The flyback power conversion circuit of claim 1 wherein the control signal generation circuit adaptively adjusts an end point of the flexible switching period according to a voltage across the primary side switch.

5. The flyback power conversion circuit of claim 1 wherein the control signal generation circuit comprises:

a secondary side current simulation circuit for generating a secondary side current simulation signal to simulate the secondary side current according to the voltage across the primary side winding and an excitation inductance value of the primary side winding; and

the comparison circuit is coupled with the secondary side current simulation circuit and is used for generating a flexible switching period determining signal according to the secondary side current simulation signal, a primary side current peak value and the current threshold value so as to determine the starting time point and the ending time point of the flexible switching period;

the primary side current is the current flowing through the primary side winding in an on period of the primary side switch in the switching cycle.

6. The flyback power converter of claim 5 wherein the comparison circuit determines the starting point based on the secondary-side current-analog signal, the peak value of the primary-side current, and the current threshold; and the comparison circuit determines the ending time point according to the secondary side current simulation signal and the peak value of the primary side current.

7. The flyback power conversion circuit of claim 5 wherein the secondary-side current-emulation circuit comprises:

A voltage-to-current conversion circuit for generating a charging current, comprising:

a switching resistor;

an amplifier circuit coupled to the switching resistor for generating a switching current flowing through the switching resistor according to a voltage across the primary winding and a resistance value of the switching resistor, wherein the switching current is proportional to the voltage across the primary winding; and

a current mirror circuit coupled to the amplifier circuit for mirroring the converted current to generate a charging current; and

and the analog capacitor is coupled with the current mirror circuit and is used for charging the analog capacitor according to the charging current so as to generate the secondary side winding current analog signal.

8. The flyback power conversion circuit of claim 6 wherein the control signal generation circuit further comprises:

a sample-hold circuit coupled to the comparator circuit for sampling and holding the peak value of the primary current to generate an end threshold value for input to the comparator circuit; and

a bias circuit coupled to the sample-and-hold circuit for superimposing the ending threshold value with a bias value associated with the current threshold value to generate a starting threshold value;

wherein, the comparison circuit compares the secondary side current simulation signal with the initial threshold value to determine the initial time point;

The comparison circuit compares the secondary side current analog signal with the ending threshold value to determine the ending time point.

9. The flyback power conversion circuit of claim 7, wherein the secondary-side current analog circuit is further configured to adaptively adjust the resistance value of the conversion resistor and/or the capacitance value of the analog capacitor according to the voltage across the primary-side switch in a set period immediately after the flexible switching period, so that the primary-side switch achieves zero-voltage switching;

the set period is related to the time required for the voltage across the primary switch to drop from a charging voltage at the end point to zero voltage.

10. The flyback power conversion circuit of claim 1 wherein the secondary side current is not below the current threshold during the segment of flexible switching and the secondary side control circuit maintains the synchronous rectification switch on during the segment of flexible switching.

11. An active clamp buffer for use in a flyback power conversion circuit for generating a switching signal to control a primary side switch to switch a primary side winding of a power transformer to convert an input voltage to an output voltage, the active clamp buffer comprising:

A buffer switch connected in series with a buffer capacitor and then connected in parallel with the primary winding; and

a control signal generating circuit for controlling the buffer switch to be turned on during a flexible switching period in a non-conduction period of the primary switch in a switching period of the switching signal, so that the primary switch realizes flexible switching;

the secondary side control circuit in the flyback power supply conversion circuit is used for controlling a synchronous rectification switch connected with the secondary side winding in series according to a secondary side current flowing through the secondary side winding of the power transformer, and the secondary side control circuit does not conduct the synchronous rectification switch when the secondary side current is lower than a current threshold value;

12. The active clamp buffer of claim 11, wherein the flyback power conversion circuit operates in a boundary conduction mode or a discontinuous conduction mode.

13. The active clamp buffer of claim 11, wherein the snubber capacitor is configured to charge the snubber capacitor with a leakage current of the primary winding during the non-conduction period of the primary switch, different from a snubber period during the soft switching, in the switching cycle of the switching signal, to transfer electrical energy stored by a leakage inductance of the primary winding during a conduction period of the primary switch to the snubber capacitor.

14. The active clamp buffer of claim 11, wherein the control signal generation circuit adaptively adjusts an ending point of the flexible switching period according to a voltage across the primary side switch.

15. The active clamp buffer of claim 11 wherein the control signal generation circuit comprises:

16. The active clamp buffer of claim 15, wherein the comparison circuit determines the start point based on the secondary side current analog signal, the peak value of the primary side current, and the current threshold; and the comparison circuit determines the ending time point according to the secondary side current simulation signal and the peak value of the primary side current.

17. The active clamp buffer of claim 15 wherein the secondary side current emulation circuit comprises:

a switching resistor;

18. The active clamp buffer of claim 16 wherein the control signal generation circuit further comprises:

19. The active clamp buffer of claim 17, wherein the secondary side current emulation circuit is further adapted to adjust the resistance value of the switching resistor and/or the capacitance value of the emulation capacitor according to the voltage across the primary side switch in a set period immediately after the flexible switching period, such that the primary side switch achieves zero voltage switching;

20. The active clamp buffer of claim 11 wherein the secondary side current is not below the current threshold during the segment of flexible switching and the secondary side control circuit maintains the synchronous rectification switch on during the segment of flexible switching.