CN114078794A - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

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Publication number
CN114078794A
CN114078794A CN202010875484.XA CN202010875484A CN114078794A CN 114078794 A CN114078794 A CN 114078794A CN 202010875484 A CN202010875484 A CN 202010875484A CN 114078794 A CN114078794 A CN 114078794A
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China
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wafer
conductive pad
semiconductor structure
layer
barrier layer
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CN202010875484.XA
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Chinese (zh)
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施信益
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Nanya Technology Corp
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Nanya Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof. The first wafer has a conductive pad. The second wafer is disposed overlying the first wafer and includes a through hole aligned with the conductive pad. The inner wall of the through hole is connected with the conductive pad. The barrier layer covers the inner wall of the through hole. The barrier layer includes a bottom. The bottom covers the conductive pad. The via extends from the bottom of the barrier layer into the conductive pad. The inner diameter of the communication passage is smaller than that of the through hole. The conductive material fills the through hole and the connecting channel and is connected to the conductive pad. Thus, the overall electrical properties can be further improved.

Description

Semiconductor structure and manufacturing method thereof
Technical Field
The invention relates to a semiconductor structure and a manufacturing method thereof.
Background
In a semiconductor structure, electrical connections between devices are made by forming through holes. To avoid undesired electrical connections and to protect the via structure, the via hole should be first filled with a barrier layer of sufficient thickness. However, in the process, this corresponds to the deposition of a thick barrier layer material at the bottom of the via, which affects the connection of the conductive material within the via and thus the overall electrical performance.
Therefore, how to improve the electrical problem caused by the accumulated thickness of the barrier layer at the bottom of the via hole is one of the problems to be solved by those skilled in the art.
Disclosure of Invention
One objective of the present invention is to provide a semiconductor structure, which can further improve the overall electrical performance of the semiconductor structure.
According to one embodiment of the present invention, a semiconductor structure includes a first wafer, a second wafer, a barrier layer, a via, and a conductive material. The first wafer has a conductive pad. The second wafer is disposed overlying the first wafer and includes a through hole aligned with the conductive pad. The inner wall of the through hole is connected with the conductive pad. The barrier layer covers the inner wall of the through hole and comprises a bottom, and the bottom of the barrier layer covers the conductive pad. The via extends from the bottom of the barrier layer into the conductive pad. The inner diameter of the communication passage is smaller than that of the through hole. The conductive material fills the through hole and the connecting channel and is connected to the conductive pad.
In one or more embodiments, the conductive material extends into the conductive pad.
In one or more embodiments, the semiconductor structure further includes an insulating layer. The insulating layer is located between the inner wall of the through hole and the barrier layer and connected with the conductive pad.
In one or more embodiments, the semiconductor structure further includes an adhesive layer. The adhesive layer is located between the first wafer and the second wafer. The through holes extend through the adhesive layer to interface with the conductive pads.
In one or more embodiments, the first wafer includes a first substrate and a first dielectric layer on the first substrate. The conductive pad is located on the first dielectric layer.
In some embodiments, the first substrate includes active elements therein. The active device is connected to the conductive pad through a line in the first dielectric layer.
In some embodiments, the second wafer includes a second substrate and a second dielectric layer on the second substrate. The second wafer is connected with the first dielectric layer of the first wafer and the conductive pad through the second dielectric layer.
In some embodiments, the second wafer further comprises a passivation layer. The passivation layer is positioned on the surface of the second substrate opposite to the second dielectric layer.
One aspect of the present invention relates to a method for fabricating a semiconductor structure.
According to one embodiment of the present invention, a method for fabricating a semiconductor structure includes the following steps. The second wafer is connected to the first wafer having the conductive pad. Through holes aligned with and connected to the conductive pads are formed in the second wafer. Depositing a barrier layer covering the via and the conductive pad. And forming a sacrificial material which is filled in the through holes and covers the second wafer. A temporary via is formed in the sacrificial material aligned with the conductive pad, the temporary via exposing the barrier layer. The bottom of the barrier layer is etched according to the temporary via to form a via exposing the conductive pad. The sacrificial material is removed. Filling the conductive material into the through hole and the connecting channel.
In one or more embodiments, the method for fabricating a semiconductor structure further comprises the following steps. Before depositing the barrier layer, an insulating layer is formed to cover the second wafer, the via hole and the conductive pad. The conductive pad is exposed by penetrating the bottom of the insulating layer, wherein the barrier layer further covers the insulating layer after depositing the barrier layer.
In one or more embodiments, the method for fabricating a semiconductor structure further comprises the following steps. A mask and a photoresist pattern are formed on the sacrificial material. Etching a temporary via aligned with the conductive pad in the sacrificial material through the mask and the photoresist pattern, the temporary via exposing the barrier layer.
In one or more embodiments, the method for fabricating a semiconductor structure further comprises the following steps. The conductive material is planarized.
In one or more embodiments, the method for fabricating a semiconductor structure further comprises the following steps. And thinning the second substrate of the second wafer, wherein the second dielectric layer is positioned on the second substrate.
In some embodiments, the semiconductor structure fabrication method further includes the following flow. And forming a passivation layer on the second substrate, wherein the passivation layer is formed on the other surface opposite to the second dielectric layer.
In summary, the present invention provides a semiconductor structure and a method for fabricating the same, in which a via is formed in a barrier layer by a sacrificial material, so that a conductive material can be electrically connected to the via, thereby improving the electrical problem caused by an excessively thick barrier layer.
The foregoing is merely illustrative of the problems to be solved, solutions to problems, and effects produced by the present invention, and specific details thereof are set forth in the following description and the related drawings.
Drawings
The advantages of the invention, together with the accompanying drawings, will be best understood from the following description taken in connection with the accompanying drawings. The description of the figures is for illustrative embodiments only and is not intended to limit individual embodiments or the scope of the claims.
FIG. 1 is a schematic cross-sectional view of a semiconductor structure according to one embodiment of the present invention; and
fig. 2-13 illustrate various cross-sectional views of a method of fabricating a semiconductor structure in various flow charts, according to one embodiment of the present invention.
Description of the main reference numerals:
100-semiconductor structure, 110-first wafer, 112-first substrate, 114-first dielectric layer, 116-conductive pad, 130-second wafer, 132-second substrate, 134-second dielectric layer, 136-passivation layer, 138-via, 140-adhesion layer, 145-insulating layer, 150-barrier layer, 151-bottom, 155-via, 160-conductive material, 210-sacrificial material, 215-mask, 220-photoresist, 230-temporary via, D-depth, W1-inner diameter, W2-inner diameter.
Detailed Description
The following detailed description of the embodiments with reference to the accompanying drawings is provided for purposes of illustration, and is not intended to limit the scope of the invention, which is defined by the claims, as the term "means" comprising "or" including "any arrangement of elements, when read in conjunction with the accompanying drawings. In addition, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, the same or similar elements will be described with the same reference numerals in the following description.
Also, the terms (terms) used throughout the specification and claims have the ordinary meaning as is accorded to each term used in this field, in the context of this disclosure, and in any specific context, unless otherwise indicated. Certain terms used to describe the invention are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing the invention.
In this document, the terms "first", "second", and the like are used only for distinguishing elements or operation methods having the same technical terms, and are not intended to indicate a sequence or limit the present invention.
Furthermore, the terms "comprising," "including," "providing," and the like, are intended to be open-ended terms that mean including, but not limited to.
Further, in this document, the terms "a" and "an" may be used broadly to refer to a single or to a plurality of such terms, unless the context specifically states otherwise. It will be further understood that the terms "comprises," "comprising," "includes," "including," "has," "having," and similar language, when used herein, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
In order to solve the problem that the overall electrical performance of the conventional semiconductor structure is affected due to the excessive thickness of the deposited barrier layer in the conductive via hole, the present invention provides a novel semiconductor structure and a corresponding manufacturing method thereof, so as to improve the above problem.
Please refer to fig. 1. Fig. 1 is a schematic cross-sectional view of a semiconductor structure 100 according to an embodiment of the invention.
As shown in fig. 1, in the present embodiment, the semiconductor structure 100 includes a first wafer 110 and a second wafer 130, and the first wafer 110 and the second wafer 130 are connected together by an adhesive layer 140.
In some embodiments, each of the first wafer 110 and the second wafer 130 may include active devices already formed thereon, such as capacitors and transistors, which may constitute a memory. After the first wafer 110 and the second wafer 130 are stacked, the space can be saved, and the first wafer 110 and the second wafer 130 can form a through via (through via) for electrical connection to the outside.
Specifically, in the present embodiment, the first wafer 110 includes a first substrate 112, a first dielectric layer 114, and a conductive pad 116 stacked from bottom to top, wherein the conductive pad 116 is disposed on the first dielectric layer 114. The first substrate 112 may have a plurality of active devices therein, including memory cells formed by transistors and capacitors, which are not shown for simplicity. A plurality of lines connected to the outside may be disposed in the first dielectric layer 114, so that the active device inside the first substrate 112 may be connected to the conductive pad 116 through the lines inside the first dielectric layer 114. Thus, the active devices in the first substrate 112 can be electrically connected to the conductive pads 116.
In some embodiments, the material of the conductive pad 116 includes aluminum.
In this embodiment, the second wafer 130 includes a second substrate 132, a second dielectric layer 134, and a passivation layer 136. The second dielectric layer 134 and the passivation layer 136 are respectively disposed on two opposite sides of the second substrate 132. Similar to the first wafer 110, in the second wafer 130, the second substrate 132 may also have a plurality of capacitors and transistors therein to form memory cells arranged together. The second dielectric layer 134 may also have a plurality of lines therein for connecting the memory cells within the second substrate 132. In some embodiments, the thickness of the second substrate 132 may be thinned as desired.
As shown in fig. 1, the second wafer 130 is connected together with the second dielectric layer 134 facing the first dielectric layer 114 of the first wafer 110. This causes the second wafer 130 to substantially cover the first dielectric layer 114 and the conductive pads 116 of the first wafer 110 with the second dielectric layer 134. Then, a passivation layer 136 is formed on the second substrate 132 on the side opposite to the second dielectric layer 134 to enhance the overall structural strength. In other words, the second dielectric layer 134 is closer to the first wafer 110 than the passivation layer 136.
In this embodiment, in order to electrically connect the conductive pads 116 of the first wafer 110, a via 138 is formed in the second wafer 130, and then the via 138 is filled with the connected conductive material 160. The through holes 138 extend through the adhesive layer 140 to interface with the conductive pads 116. In the horizontal direction, the through hole 138 has an inner diameter W1, and the inner diameter W1 is smaller than the inner diameter of the conductive pad 116 of the first wafer 110, so as to avoid damaging other circuits in the first dielectric layer 114. In other words, the inner wall of the through hole 138 is substantially connected to the top of the conductive pad 116.
In summary, in some embodiments, the inner diameter W1 of the through hole 138 may be set to be in a range from 5 μm to 10 μm, if desired. In some embodiments, the depth of the through hole 138 (i.e., approximately equal to the overall thickness of the second wafer 130) is in a range from 20 μm to 50 μm.
To avoid undesired connections of the conductive material 160 to active devices in the second substrate 132 of the second wafer 130, additional material may be disposed between the conductive material 160 and the through-holes 138. In the semiconductor structure 100 of the present embodiment, an insulating layer 145 and a barrier layer 150 are disposed between the conductive material 160 and the through hole 138.
In fig. 1, an insulating layer 145 is provided extending from the passivation layer 136 of the second wafer 130 towards the conductive pads 116. This allows the insulating layer 145 to substantially completely cover the inner walls of the perforations 138.
In some embodiments, the material of the insulating layer 145 is, for example, a non-conductive oxide or nitride, but not limited thereto.
The barrier layer 150 is further disposed over the insulating layer 145 within the via 138, and the bottom 151 of the barrier layer 150 further covers the conductive pad 116. Generally, the barrier layer 150 may be deposited in the via 138. The barrier layer 150 serves to prevent the conductive material 160 from undesirably contacting the inner wall of the through hole 138 and affecting the electrical properties, and also to increase the strength of the overall structure.
In some embodiments, the material of the barrier layer 150 may comprise tantalum (Ta) or tantalum nitride (TaN), and may be deposited by Physical Vapor Deposition (PVD) over the insulating layer 145 in the via 138 and the conductive pad 116.
In order to make the barrier layer 150 have a certain thickness and function as a barrier, the barrier layer 150 deposited on the conductive pad 116 generally has a certain thickness. In the semiconductor structure 100 of this embodiment, a communication channel 155 is further formed to extend from the barrier layer 150 to the conductive pad 116. The channel 155 extends into the conductive pad 116 to a depth D. This allows the conductive material 160 filled in the through hole 138 to be directly connected to the conductive pad 116 through the via 155, thereby avoiding the overall electrical problem caused by the thickness of the barrier layer 150. As shown in FIG. 1, inner diameter W2 of communication channel 155 is smaller than inner diameter W1 of perforations 138. This corresponds to the barrier layer 150 appearing as two L-shapes in the cross-section of fig. 1.
In fig. 1, the conductive material 160, the barrier layer 150, and the insulating layer 145 are flush on top. In some embodiments, after all of the conductive material 160, the barrier layer 150 and the insulating layer 145 are formed, the conductive material, the barrier layer 150 and the insulating layer 145 may be leveled by a planarization process. The exposed conductive material 160 is flattened to facilitate electrical connection with other structures.
In some embodiments, the conductive material 160 comprises copper.
To further illustrate the formation of the semiconductor structure 100 of the present invention, refer to fig. 2-13. Fig. 2 to 13 show a plurality of schematic cross-sectional views in different flows of a method of manufacturing the semiconductor structure 100 according to an embodiment of the present invention.
In fig. 2, a first wafer 110 and a second wafer 130 are provided. The first wafer 110 and the second wafer 130 may be semiconductor wafers. In this embodiment, the first wafer 110 includes a first substrate 112, a first dielectric layer 114, and a conductive pad 116 stacked from bottom to top, the conductive pad 116 is disposed on the first dielectric layer 114, the second wafer 130 includes a second substrate 132, a second dielectric layer 134, and a passivation layer 136, and the second dielectric layer 134 and the passivation layer 136 are respectively disposed on two opposite sides of the second substrate 132.
The first substrate 112 and the second substrate 132 are, for example, silicon substrates, but not limited thereto. As mentioned above, active devices, such as memory cells, and corresponding circuits may be disposed on the first substrate 112 and the second substrate 132, and the first dielectric layer 114 and the second dielectric layer 134 may be disposed with interconnection lines for connecting the active devices.
In some embodiments, the second substrate 132 may be thinned before the first wafer 110 and the second wafer 130 are connected, if desired.
In fig. 2, the first dielectric layer 114 of the first wafer 110 is face-to-face connected to the second dielectric layer 134 of the second wafer 130 by an adhesive layer 140. Thus, as shown in fig. 2, the vertical direction is stacked from top to bottom in sequence as follows: the first substrate 112, the first dielectric layer 114, the conductive pad 116, the adhesive layer 140, the second dielectric layer 134, the second substrate 132, and the passivation layer 136 of the first wafer 110.
Referring to fig. 2, in fig. 3, a through hole 138 aligned with and connected to the conductive pad 116 is formed in the second wafer 130. The through hole 138 may be formed by a TSV patterning (TSV patterning) process including using a yellow light and an etch (tch). Thus, the inner wall corresponding to the through hole 138 is also connected to the conductive pad 116.
Continuing with the process of FIG. 3, in FIG. 4, an insulating layer 145 is formed by liner deposition (liner deposition) to cover the second through-hole 138 and the conductive pad 116 of the wafer 130. As shown in FIG. 4, the insulating layer 145 is disposed with a uniform thickness covering the inner wall of the through hole 138 and the conductive pad 116.
Referring to fig. 4, in fig. 5, the conductive pad 116 is exposed by a bottom substrate punch-through (bottom line punch) process, which may be performed through the bottom of the insulating layer 145. Thus, only a small amount of the insulating layer 145 covers the conductive pad 116.
In fig. 6, a barrier layer 150 is deposited by a pvd process to cover the inner walls of the vias 138 and the conductive pads 116. The barrier layer 150 substantially covers the insulating layer 145. In the present embodiment, the barrier layer 150 is tantalum (Ta) or tantalum nitride (TaN) to further enhance the structural strength of the via 138. The material of the barrier layer 150 is capable of conducting electricity to a lesser extent affecting the electrical properties of the overall structure. The bottom 151 of the barrier layer 150 directly contacts the conductive pad 116.
Continuing with the flow of fig. 6, in fig. 7, a sacrificial material 210 is formed by a deposition process that fills the through-hole 138 and substantially covers the second wafer 130. Sacrificial material 210 includes polymers that can function to protect barrier layer 150 to some extent during subsequent processing.
Proceeding to fig. 8, a mask 215(hard mask) is disposed on the sacrificial material 210 by a deposition process, and a photoresist 220 for patterning is disposed on the mask 215 as a photoresist pattern. The material of the mask 215 includes a metal oxide or a silicon oxynitride (SiON) film.
In FIG. 8, the photoresist pattern formed by the photoresist 220 has a void at the alignment pad 116. Thus, the vias aligned with the conductive pads 116 can be formed in a subsequent process.
Referring to fig. 8, in fig. 9, a temporary via 230 aligned with the conductive pad 116 is etched in the sacrificial material 210 by the photoresist pattern of the mask 215 and the photoresist 220, and the temporary via 230 exposes the bottom 151 of the barrier layer 150. The remaining mask 215 may then be passed through the bottom 151 of the barrier layer 150.
As shown in FIG. 9, the through hole 138 has an inner diameter W1, the temporary channel 230 is formed following the photoresist pattern aligned with the conductive pad 116 to have an inner diameter W2, and the inner diameter W2 is smaller than the inner diameter W1.
Continuing with fig. 9, in fig. 10, the bottom portion 151 of the barrier layer 150 is etched according to the temporary via 230 and the remaining mask 215, thereby forming a communication channel 155 extending from the bottom portion 151 to the interior of the conductive pad 116. The mask 215 is completely removed. In the presence of the sacrificial material 210, the formation of the via 155 will not damage the via 138, the insulating layer 145, and the portion of the barrier layer 150 other than the bottom 151.
In fig. 10, the vias 155 are assured to have a depth D extending to the conductive pads to ensure that the conductive material 160 can directly contact the conductive pads 116 when the conductive material 160 is subsequently filled.
Proceeding to fig. 11, after the communication channel 155 is formed, the sacrificial material 210 is removed by a method including wet cleaning (wet cleaning).
Referring to fig. 12, in the through hole 138 and the connecting channel 155, a conductive material 160 is further filled, as shown in fig. 11. The conductive material 160 is, for example, copper. Conductive material 160 also covers insulating layer 145 and barrier layer 150 over passivation layer 136.
Thus, the conductive material 160 can directly contact the conductive pad 116, and the influence of the thickness of the barrier layer 150 on the overall electrical performance is relatively reduced.
In some embodiments, the conductive material 160 may be filled by forming a metal seed layer (seed layer) in the through hole 138, and then filling the metal seed layer with the conductive material 160. For example, in some embodiments, the conductive material 160 is copper, and a metal seed layer of copper may be deposited by physical vapor deposition in a small amount prior to the through holes 138 and the connecting channels 155. Copper can then be easily plated (plated) on the copper metal seed layer until the via 138 and the via 155 are filled.
In such a process of filling the conductive material 160, after the copper is filled by electroplating, the copper may be further heated, so that the metal seed layer of copper and the electroplated copper form an alloy (alloy) with each other. In some embodiments, after the copper is filled by electroplating, the entire structure may be subjected to a temperature of 150 ℃ to 300 ℃ for an alloying time. In some embodiments, the alloying time may be thirty minutes. In some embodiments, the alloying time may be from one hour to two hours. After the re-heating for the alloying time, it is ensured that the metal seed layer of copper of the conductive material 160 and the electroplated copper are alloyed (alloy) with each other, and the structure can be more stable.
Further, in fig. 13, after the conductive material 160 fills the through holes 138 and the connecting channels 155, the conductive material 160 is planarized such that the conductive material 160 is substantially flush with the second wafer 130. In fig. 13, the tops of the conductive material 160, the barrier layer 150, and the insulating layer 145 are substantially flush. The flat exposed conductive material 160 can be easily integrated with other structures and electrically connected. In some embodiments, the Planarization may be performed by Chemical-Mechanical Planarization (CMP). In this manner, the semiconductor structure 100 shown in fig. 1 can be obtained.
In summary, the present invention provides a semiconductor structure and a method for fabricating the same. By additionally providing the sacrificial material in the process of the semiconductor device manufacturing method, a communication channel can be formed without damaging the conductive via and the barrier layer, and the communication channel can directly contact the conductive material for electrical connection with the wafer conductive pad. Therefore, the problem of poor electrical property caused by over-thick barrier layer can be improved.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (14)

1. A semiconductor structure, comprising:
a first wafer having a conductive pad;
the second wafer is arranged to overlap the first wafer and comprises a through hole aligned with the conductive pad, wherein the inner wall of the through hole is connected with the conductive pad;
a barrier layer covering the inner wall of the via, wherein the barrier layer includes a bottom covering the conductive pad;
a via extending from the bottom of the barrier layer into the conductive pad, wherein an inner diameter of the via is smaller than an inner diameter of the through hole; and
and the conductive material is filled in the through hole and the communication channel and is connected to the conductive pad.
2. The semiconductor structure of claim 1, wherein the conductive material extends into the conductive pad.
3. The semiconductor structure of claim 1, further comprising:
and the insulating layer is positioned between the inner wall of the through hole and the barrier layer and is connected with the conducting pad.
4. The semiconductor structure of claim 1, further comprising:
an adhesive layer between the first wafer and the second wafer, the through hole extending through the adhesive layer to connect with the conductive pad.
5. The semiconductor structure of claim 1, wherein the first wafer comprises a first substrate and a first dielectric layer on the first substrate, the conductive pad being on the first dielectric layer.
6. The semiconductor structure of claim 5, wherein the first substrate includes active elements therein, the active elements being connected to the conductive pads by wires located within the first dielectric layer.
7. The semiconductor structure of claim 5, wherein the second wafer comprises a second substrate and a second dielectric layer on the second substrate, the second wafer connecting the first dielectric layer of the first wafer and the conductive pad with the second dielectric layer.
8. The semiconductor structure of claim 7, wherein the second wafer further comprises a passivation layer on a surface of the second substrate opposite the second dielectric layer.
9. A method of fabricating a semiconductor structure, comprising:
connecting the second wafer to the first wafer with the conductive pad;
forming a through hole aligned and connected with the conductive pad on the second wafer;
depositing a barrier layer covering the via and the conductive pad;
forming a sacrificial material filled in the through hole and covering the second wafer;
forming a temporary via in the sacrificial material aligned with the conductive pad, the temporary via exposing the barrier layer;
etching the bottom of the barrier layer according to the temporary channel to form a communication channel exposing the conductive pad;
removing the sacrificial material; and
and filling a conductive material into the through hole and the communication channel.
10. The method of fabricating a semiconductor structure of claim 9, further comprising:
forming an insulating layer covering the second wafer, the vias and the conductive pads before depositing the barrier layer;
penetrating the bottom of the insulating layer to expose the conductive pad, wherein the barrier layer further covers the insulating layer after depositing the barrier layer.
11. The method of fabricating a semiconductor structure of claim 9, further comprising:
arranging a photomask and a photoresist pattern on the sacrificial material; and
and etching the temporary channel aligned with the conductive pad on the sacrificial material through the photomask and the photoresist pattern, wherein the barrier layer is exposed by the temporary channel.
12. The method of fabricating a semiconductor structure of claim 9, further comprising:
planarizing the conductive material.
13. The method of fabricating a semiconductor structure of claim 9, further comprising:
and thinning the second substrate of the second wafer, wherein a second dielectric layer is positioned on the second substrate.
14. The method of fabricating a semiconductor structure of claim 13, further comprising:
and forming a passivation layer on the second substrate, wherein the passivation layer is formed on the other surface opposite to the second dielectric layer.
CN202010875484.XA 2020-08-11 2020-08-27 Semiconductor structure and manufacturing method thereof Pending CN114078794A (en)

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TWI236100B (en) * 2003-12-18 2005-07-11 United Microelectronics Corp Method of forming a dual damascene copper wire
US9147767B2 (en) * 2014-02-07 2015-09-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
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