CN114078533A

CN114078533A - Memory device, memory device and method of operating the memory device

Info

Publication number: CN114078533A
Application number: CN202110366065.8A
Authority: CN
Inventors: 刘炳晟
Original assignee: SK Hynix Inc
Current assignee: SK Hynix Inc
Priority date: 2020-08-12
Filing date: 2021-04-06
Publication date: 2022-02-22
Also published as: US11367505B2; US20220051745A1; KR20220020731A

Abstract

The application discloses a memory device, a memory device and a method for operating the memory device. The present technology relates to an electronic device. In accordance with the present technique, a memory device with reduced latency includes: a plurality of memory cells; an optimum read voltage information storage configured to store optimum read voltage information determined according to a cell count value that is the number of memory cells, among the plurality of memory cells, that are read as first memory cells based on data read from the plurality of memory cells; and a read voltage controller configured to calculate a cell count value corresponding to a default read voltage based on data read from the plurality of memory cells using the default read voltage in response to an optimal read voltage setting command input from the memory controller, and generate a first optimal read voltage based on the cell count value corresponding to the default read voltage and the optimal read voltage information.

Description

Memory device, memory device and method of operating the memory device

Technical Field

The present disclosure relates to electronic devices, and more particularly, to a memory device and a method of operating the same.

Background

A storage device is a device that stores data under the control of a host device such as a computer or a smartphone. The memory device may include a memory device to store data and a memory controller to control the memory device. Memory devices can be classified into volatile memory devices and non-volatile memory devices.

A volatile memory device may be a device that stores data only when power is supplied and loses the stored data when power is cut off. Volatile memory devices may include Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and the like.

A nonvolatile memory device is a device that does not lose data even if power is cut off. Non-volatile memory devices include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), flash memory, and the like.

Disclosure of Invention

The memory device according to an embodiment of the present disclosure may include: a plurality of memory cells; an optimum read voltage information storage configured to store optimum read voltage information determined according to a cell count value that is the number of memory cells, among the plurality of memory cells, that are read as first memory cells based on data read from the plurality of memory cells; and a read voltage controller configured to calculate a cell count value corresponding to a default read voltage based on data read from the plurality of memory cells using the default read voltage in response to an optimal read voltage setting command input from the memory controller, and generate a first optimal read voltage based on the cell count value corresponding to the default read voltage and the optimal read voltage information.

The storage device according to an embodiment of the present disclosure may include: a memory device including a plurality of memory cells and configured to store optimal read voltage information determined according to a cell count value, which is a number of memory cells, among the plurality of memory cells, that are read as first memory cells based on data read from the plurality of memory cells; and a memory controller configured to execute one or more recovery algorithms for recovering data corresponding to a failed read operation among read operations performed on the memory device. The memory controller controls the memory device to generate a read voltage used in a recovery algorithm to be currently executed among the one or more recovery algorithms based on a cell count value calculated according to a read operation corresponding to a previously executed recovery algorithm among the one or more recovery algorithms and the optimal read voltage information.

A method of operating a memory device comprising a plurality of memory cells comprises the steps of: storing optimal read voltage information determined according to a cell count value, which is the number of memory cells, among the plurality of memory cells, that are read as first memory cells based on data read from the plurality of memory cells; receiving an optimal read voltage setting command from a memory controller; calculating a cell count value corresponding to a default read voltage based on data read from the plurality of memory cells using the default read voltage in response to the optimal read voltage setting command; and generating a first optimal read voltage based on the cell count value corresponding to the default read voltage and the optimal read voltage information.

Drawings

Fig. 1 is a diagram illustrating a storage device according to an embodiment of the present disclosure.

Fig. 2 is a diagram illustrating the memory device of fig. 1.

Fig. 3 is a diagram showing the structure of any one of the memory blocks of fig. 2.

Fig. 4 is a graph showing the default read voltage.

Fig. 5 is a diagram illustrating a recovery algorithm.

Fig. 6 is a diagram illustrating read retries.

Fig. 7 is a diagram illustrating eBoost.

Fig. 8 is a diagram illustrating soft decoding.

Fig. 9 is a diagram illustrating a read operation processor according to an embodiment of the present disclosure.

Fig. 10 is a circuit diagram illustrating an embodiment of the optimum read voltage information storage device and the read voltage controller of fig. 9.

Fig. 11 is a diagram illustrating optimal read voltage information according to an embodiment of the present disclosure.

Fig. 12A is a diagram illustrating an optimal read voltage setting command according to an embodiment of the present disclosure.

Fig. 12B is a diagram illustrating an optimal read voltage obtaining command according to an embodiment of the present disclosure.

Fig. 13 is a flowchart illustrating an operating method of a memory device according to an embodiment of the present disclosure.

Fig. 14 is a flowchart illustrating a method of performing a recovery algorithm according to an embodiment of the present disclosure.

Fig. 15 is a flowchart illustrating an operating method of a memory device according to an embodiment of the present disclosure.

Fig. 16 is a diagram illustrating the memory controller of fig. 1.

Fig. 17 is a block diagram showing a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

Fig. 18 is a block diagram showing a Solid State Drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

Fig. 19 is a block diagram showing a user system to which a storage device according to an embodiment of the present disclosure is applied.

Detailed Description

Only the specific structural or functional descriptions of embodiments according to the concepts disclosed in the present specification or application are shown to describe embodiments according to the concepts disclosed in the present disclosure. Embodiments in accordance with the concepts of the present disclosure may be implemented in various forms and the description is not limited to the embodiments described in the specification or the application.

Embodiments of the present disclosure provide a memory device with reduced latency and a method of operating the same.

In accordance with the present techniques, a memory device with reduced latency and a method of operating the same may be provided.

Referring to fig. 1, a memory device 50 may include a memory device 100 and a memory controller 200 controlling the operation of the memory device 100. The storage device 50 may be a device that stores data under the control of a host 300 (e.g., a cellular phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, a tablet PC, or a vehicle infotainment system).

The storage device 50 may be manufactured as one of various types of storage devices according to a host interface as a communication method with the host 300. For example, the storage device 50 may be configured as any of various types of storage devices, such as a multimedia card in the form of an SSD, MMC, eMMC, RS-MMC, and micro-MMC, a secure digital card in the form of an SD, mini-SD, and micro-SD, a Universal Serial Bus (USB) storage device, a universal flash memory (UFS) device, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a Peripheral Component Interconnect (PCI) card type storage device, a PCI express (PCI-E) card type storage device, a Compact Flash (CF) card, a smart media card, and a memory stick.

The storage device 50 may be manufactured in any of various types of packages. For example, the storage device 50 may be manufactured in any of various types of package types such as a Package On Package (POP), a System In Package (SIP), a System On Chip (SOC), a multi-chip package (MCP), a Chip On Board (COB), a wafer-level manufacturing package (WFP), and a wafer-level package on package (WSP).

The memory device 100 may store data. The memory device 100 operates under the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown) including a plurality of memory cells storing data.

Each memory cell may be configured as a Single Level Cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a Triple Level Cell (TLC) that stores three data bits, or a Quadruple Level Cell (QLC) that is capable of storing four data bits.

The memory cell array (not shown) may include a plurality of memory blocks. One memory block may include a plurality of pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100. The memory block may be a unit for erasing data.

In an embodiment, the memory device 100 may be a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate 4(LPDDR4) SDRAM, a Graphics Double Data Rate (GDDR) SDRAM, a low power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory devices, Resistive Random Access Memory (RRAM), phase change random access memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), spin torque transfer random access memory (STT-RAM), or the like. In this specification, for convenience of description, it is assumed that the memory device 100 is a NAND flash memory.

The memory device 100 is configured to receive a command CMD and an address ADDR from the memory controller 200 and access a region selected by the address in the memory cell array. The memory device 100 may perform an operation indicated by the command CMD on the area selected by the address ADDR. For example, the memory device 100 may perform a write operation (programming operation), a read operation, and an erase operation. During a program operation, the memory device 100 may program data to an area selected by the address ADDR. During a read operation, the memory device 100 may read data from the area selected by the address ADDR. During the erase operation, the memory device 100 may erase data stored in the area selected by the address ADDR.

In an embodiment, the memory device 100 may include a read operation processor 131.

The read operation processor 131 may store optimum read voltage information determined according to a cell count value, which is the number of memory cells, among the plurality of memory cells, that are read as the first memory cell based on data read from the plurality of memory cells. At this time, the read operation processor 131 may calculate a cell count value corresponding to a specific read voltage based on data read from a plurality of memory cells using the specific read voltage. For example, the read operation processor 131 may calculate a cell count value corresponding to a specific read voltage based on a comparison result of currents sensed from a plurality of memory cells using the specific read voltage and a reference current. In addition, the read operation processor 131 may generate an optimal read voltage to be used in the recovery algorithm based on the cell count value and the optimal read voltage information. Accordingly, the speed of the read operation of the recovery algorithm can be improved by generating an optimal read voltage to be used for the read operation corresponding to the recovery algorithm using the cell count value obtained by the specific read voltage and the previously stored optimal read voltage information. Thus, the delay of the recovery algorithm can be reduced.

The memory controller 200 may control the overall operation of the memory device 50.

When power is applied to the storage device 50, the storage controller 200 may execute Firmware (FW). When the memory device 100 is a flash memory device, the Firmware (FW) may include a Host Interface Layer (HIL) controlling communication with the host 300, a Flash Translation Layer (FTL) controlling communication between the memory controller 200 and the host 300, and a Flash Interface Layer (FIL) controlling communication with the memory device 100.

In an embodiment, the storage controller 200 may receive data and Logical Block Addresses (LBAs) from the host 300 and may convert the LBAs into Physical Block Addresses (PBAs) indicating addresses of memory units in which the data included in the memory device 100 is to be stored. In this specification, the LBA and the "logical address" may be used in the same meaning. In this specification, PBA and "physical address" may be used as the same meaning.

The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, an erase operation, etc. according to a request of the host 300. During a programming operation, the memory controller 200 may provide write commands, PBAs, and data to the memory device 100. During a read operation, the memory controller 200 may provide a read command and a PBA to the memory device 100. During an erase operation, the memory controller 200 may provide an erase command and PBA to the memory device 100.

In an embodiment, the memory controller 200 may generate a command, an address, and data independently of a request from the host 300 and transmit the command, the address, and the data to the memory device 100. For example, the memory controller 200 may provide commands, addresses, and data to the memory device 100 for performing read and program operations, along with performing wear leveling, read reclamation, garbage collection, and the like.

In an embodiment, the memory controller 200 may control at least two or more memory devices 100. In this case, the memory controller 200 may control the memory device 100 according to the interleaving method to improve the operation performance. The interleaving method may be a method of controlling operations of at least two memory devices 100 to overlap each other.

The read request provided from the host 300 is a request to provide the host 300 again with the original data requested by the host 300 to be stored in the storage device 50. The memory controller 200 generates write data including parity data for error correction by performing error correction coding on original data. The memory controller 200 may control the memory device 100 to store write data in the memory device 100.

Thereafter, in response to a read request from the host 300, the memory controller 200 may provide a read command and a physical address indicating a location of a memory cell storing data to be read to the memory device 100 in order to obtain data corresponding to the read request of the host 300 from the memory device 100.

The memory device 100 may perform a read operation using the default read voltage. The read voltage may be a voltage applied to identify data stored in the memory cell. The default read voltage may be a read voltage determined through testing during the manufacturing process of the memory device 100.

The memory device 100 may provide read data obtained by reading data stored in the received physical address using a default read voltage to the memory controller 200. The memory controller 200 may perform error correction decoding on the read data.

The error correction decoding may be an operation of obtaining original data by correcting error bits included in read data. The error correction decoding may succeed or fail depending on whether the number of error bits included in the read data is equal to or less than the number of correctable error bits. When the number of error bits included in the read data is equal to or less than the number of correctable error bits, error correction decoding can pass. Conversely, when the number of error bits included in the read data exceeds the number of correctable error bits, the error correction decoding may be considered to have failed or failed. When the error correction decoding passes, original data corresponding to the logical address requested by the host 300 can be obtained. Thus, when error correction decoding passes, the read operation performed by the memory device 100 may pass. When error correction decoding fails, the original data may not be available and the read operation performed by the memory device 100 may fail.

When a read operation fails, the memory controller 200 may execute a plurality of recovery algorithms until the original data is obtained. The plurality of recovery algorithms may be executed according to a preset order. As the complexity of the recovery algorithm increases, the probability of obtaining the original data increases. However, since the amount of operations or calculations performed by the memory controller 200 increases according to complexity, overhead may also increase. In an embodiment, the storage controller 200 may execute the recovery algorithms in order from a recovery algorithm with low complexity to a recovery algorithm with high complexity. When the original data is obtained by any one of the recovery algorithms, the remaining recovery algorithms may not be executed.

In an embodiment, the memory controller 200 may execute one or more recovery algorithms for recovering data corresponding to a failed read operation among read operations performed on the memory device 100. At this time, the memory controller 200 may control the memory device 100 to generate one or more optimal read voltages to be used for the one or more recovery algorithms based on the cell count value calculated according to the read operation corresponding to the one or more recovery algorithms and the optimal read voltage information. For example, the memory controller 200 may control the memory device 100 to generate a read voltage for a recovery algorithm to be currently executed among the one or more recovery algorithms based on a cell count value calculated according to a read operation corresponding to a previously executed recovery algorithm among the one or more recovery algorithms and the optimal read voltage information.

The memory controller 200 may control the memory device 100 to perform a read operation corresponding to a first recovery algorithm among the one or more recovery algorithms using the default read voltage. In an embodiment, the first recovery algorithm may be a read retry.

In addition, when the read operation using the default read voltage fails, the memory controller 200 may calculate a cell count value corresponding to the default read voltage based on a result of comparing currents sensed from the plurality of memory cells using the default read voltage with a reference current. In an embodiment, the memory controller 200 may perform error correction decoding on data read by a read operation using a default read voltage in a bit inversion method. At this time, when the error correction decoding fails, the memory controller 200 may calculate a cell count value based on a result of comparison of a current sensed from the memory cell applied with the default read voltage with the reference current.

In addition, the memory controller 200 may control the memory device 100 to generate the first optimal read voltage based on the cell count value corresponding to the default read voltage and the optimal read voltage information.

The memory controller 200 may control the memory device 100 to re-perform the read operation corresponding to the first recovery algorithm using the first optimal read voltage.

In addition, when the read operation using the first optimal read voltage fails, the memory controller 200 may calculate a cell count value corresponding to the first optimal read voltage based on a result of comparing the reference current with the current sensed from the plurality of memory cells using the first optimal read voltage. In an embodiment, the memory controller 200 may perform error correction decoding on data read by a read operation using the first optimal read voltage in a min-sum method. At this time, when the error correction decoding fails, the memory controller 200 may calculate a cell count value based on a result of comparison of the reference current and the current sensed from the memory cell applied with the first optimal read voltage.

In addition, the memory controller 200 may control the memory device 100 to generate the second optimal read voltage based on the cell count value corresponding to the first optimal read voltage and the optimal read voltage information.

The memory controller 200 may control the memory device 100 to perform a read operation corresponding to a second recovery algorithm among the one or more recovery algorithms using the second optimal read voltage. In an embodiment, the second recovery algorithm may be eBoost.

In addition, when the read operation using the second optimal read voltage fails, the memory controller 200 may control the memory device 100 to generate a plurality of soft read voltages based on the second optimal read voltage. For example, the memory controller 200 may control the memory device 100 to generate a plurality of soft read voltages having a constant offset based on the second optimal read voltage.

In addition, the memory controller 200 may control the memory device 100 to perform a third recovery algorithm among the one or more recovery algorithms using the plurality of soft read voltages. In an embodiment, the third recovery algorithm may be soft decoding.

The host 300 may communicate with the storage device 50 using AT least one of various communication methods such as Universal Serial Bus (USB), serial AT attachment (SATA), serial attached SCSI (sas), high speed inter-chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI express (pcie), non-volatile memory AT high speed (NVMe), universal flash memory (UFS), Secure Digital (SD), Multi Media Card (MMC), embedded MMC (emmc), dual in-line memory module (DIMM), registered dual inline memory (rdimm), and load reduced DIMM (lrdimm).

Fig. 2 is a diagram illustrating the structure of the memory device 100 of fig. 1.

Referring to fig. 2, the memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130. The control logic 130 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 130 may be control logic circuitry that operates according to an algorithm and/or a processor that executes control logic code.

Memory cell array 110 includes a plurality of memory blocks BLK1 through BLKz. A plurality of memory blocks BLK1 through BLKz are connected to row decoder 121 through row lines RL. A plurality of memory blocks BLK1 through BLKz may be connected to the page buffer group 123 through bit lines BL1 through BLn. Each of the plurality of memory blocks BLK1 through BLKz includes a plurality of memory cells. As an embodiment, the plurality of memory cells are non-volatile memory cells. Memory cells connected to the same word line may be defined as one page. Thus, one memory block may include a plurality of pages.

The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line.

Each memory cell included in the memory cell array 110 may be configured as a Single Level Cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a Triple Level Cell (TLC) storing three data bits, or a Quadruple Level Cell (QLC) storing four data bits.

Peripheral circuitry 120 may be configured to perform a program operation, a read operation, or an erase operation on a selected area of memory cell array 110 under the control of control logic 130. The peripheral circuits 120 may drive the memory cell array 110. For example, peripheral circuitry 120 may apply or discharge various operating voltages to row lines RL and bit lines BL 1-BLn under the control of control logic 130.

Peripheral circuitry 120 may include a row decoder 121, a voltage generator 122, a set of page buffers 123, a column decoder 124, and input/output circuitry 125.

The row decoder 121 is connected to the memory cell array 110 through a row line RL. The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line. In an embodiment, the word lines may include a normal word line and a dummy word line. In an embodiment, the row line RL may also include a tube select line.

The row decoder 121 is configured to operate in response to control by the control logic 130. The row decoder 121 receives a row address RADD from the control logic 130.

The row decoder 121 is configured to decode a row address RADD received from the control logic 130. The row decoder 121 selects at least one memory block among the memory blocks BLK1 through BLKz according to the decoded address. In addition, the row decoder 121 may select at least one word line of the selected memory block according to the decoded address to apply the voltage generated by the voltage generator 122 to the at least one word line WL.

For example, during a program operation, the row decoder 121 may apply a program voltage to a selected word line and apply a program pass voltage having a lower level than the program voltage to unselected word lines. During a program verify operation, the row decoder 121 may apply a verify voltage to a selected word line and a verify pass voltage higher than the verify voltage to unselected word lines. During a read operation, the row decoder 121 may apply a read voltage to a selected word line and a read pass voltage higher than the read voltage to unselected word lines.

In an embodiment, the erase operation of the memory device 100 is performed in units of memory blocks. During an erase operation, the row decoder 121 may select one memory block according to the decoded address. During an erase operation, the row decoder 121 may apply a ground voltage to a word line connected to a selected memory block.

The voltage generator 122 operates in response to control by the control logic 130. The voltage generator 122 is configured to generate a plurality of voltages using an external power supply voltage supplied to the memory device 100. Specifically, the voltage generator 122 may generate various operation voltages Vop for a program operation, a read operation, and an erase operation in response to the operation signal OPSIG. For example, the voltage generator 122 may generate a program voltage, a verify voltage, a pass voltage, a read voltage, an erase voltage, and the like in response to control by the control logic 130.

As an embodiment, the voltage generator 122 may generate the internal power voltage by adjusting the external power voltage. The internal power supply voltage generated by the voltage generator 122 is used as an operation voltage of the memory device 100.

As an embodiment, the voltage generator 122 may generate a plurality of voltages using an external power supply voltage or an internal power supply voltage.

For example, the voltage generator 122 may include a plurality of pumping capacitors that receive the internal supply voltage, and the plurality of pumping capacitors may be selectively enabled to generate the plurality of voltages in response to control by the control logic 130.

The generated plurality of voltages may be supplied to the memory cell array 110 by the row decoder 121.

The page buffer group 123 includes first to nth page buffers PB1 to PBn. The first to nth page buffers PB1 to PBn are connected to the memory cell array 110 through first to nth bit lines BL1 to BLn, respectively. The first to nth page buffers PB1 to PBn operate in response to control of the control logic 130. Specifically, the first to nth page buffers PB1 to PBn may operate in response to the page buffer control signals PBSIGNALS. For example, the first to nth page buffers PB1 to PBn may temporarily store data received through the first to nth bit lines BL1 to BLn, or may sense voltages or currents of the bit lines BL1 to BLn during a read operation or a verify operation.

For example, during a program operation, when a program pulse is applied to a selected word line, the first to nth page buffers PB1 to PBn may transfer DATA received through the input/output circuit 125 to a selected memory cell through the first to nth bit lines BL1 to BLn. The memory cells of the selected page are programmed according to the transferred DATA. A memory cell connected to a bit line applied with a program enable voltage (e.g., ground voltage) may have an increased threshold voltage. The threshold voltage of the memory cell connected to the bit line to which the program-inhibit voltage (e.g., power supply voltage) is applied may be maintained. During a program verify operation, the first to nth page buffers PB1 to PBn read page data from selected memory cells through the first to nth bit lines BL1 to BLn.

During a read operation, under the control of the column decoder 124, the first to nth page buffers PB1 to PBn read DATA from the memory cells of a selected page through the first to nth bit lines BL1 to BLn and output the read DATA to the input/output circuit 125.

During the erase operation, the first to nth page buffers PB1 to PBn may float the first to nth bit lines BL1 to BLn.

The column decoder 124 may transfer data between the input/output circuit 125 and the page buffer group 123 in response to a column address CADD. For example, the column decoder 124 may exchange data with the first to nth page buffers PB1 to PBn through the data line DL, or may exchange data with the input/output circuit 125 through the column line CL.

The input/output circuit 125 may transfer a command CMD and an address ADDR received from the memory controller 200 described with reference to fig. 1 to the control logic 130 or may exchange DATA with the column decoder 124.

The sensing circuit 126 may generate a reference current in response to the permission bit signal VRYBIT during a read operation or a verify operation and compare the sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current to output a PASS signal PASS or a FAIL signal FAIL.

The control logic 130 may output an operation signal OPSIG, a row address RADD, a page buffer control signal PBSIGNALS, and an enable bit VRYBIT to control the peripheral circuit 120 in response to the command CMD and the address ADDR. In addition, control logic 130 may determine whether the verify operation passed or failed in response to PASS signal PASS or FAIL signal FAIL.

In an embodiment, control logic 130 may include a read operation processor 131.

The read operation processor 131 may control the peripheral circuit 120 to perform a read operation according to a read command input from the memory controller 200. The read operation performed by the read operation processor 131 is described with reference to fig. 9 and 10.

The memory block BLKi is any one of the memory blocks BLK1 through BLKi of fig. 2.

Referring to fig. 3, a plurality of word lines arranged in parallel with each other may be connected between a first selection line and a second selection line. Here, the first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL. More specifically, the memory block 110 may include a plurality of strings ST connected between the bit lines BL1 to BLn and the source lines SL. The bit lines BL1 to BLn may be connected to the strings ST, respectively, and the source lines SL may be connected in common to the strings ST. Since the strings ST may be configured to be identical to each other, the strings ST connected to the first bit line BL1 will be specifically described as an example.

The string ST may include a source select transistor SST, a plurality of memory cells MC1 to MC16, and a drain select transistor DST connected in series between a source line SL and a first bit line BL 1. One string ST may include at least one or more of the source select transistor SST and the drain select transistor DST, and may include memory cells MC1 through MC16 (more than the number shown in the drawing).

A source of the source selection transistor SST may be connected to a source line SL, and a drain of the drain selection transistor DST may be connected to a first bit line BL 1. The memory cells MC1 through MC16 may be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in the different strings ST may be connected to a source select line SSL, the gates of the drain select transistors DST may be connected to a drain select line DSL, and the gates of the memory cells MC1 through MC16 may be connected to a plurality of word lines WL1 through WL 16. A group of memory cells connected to the same word line among memory cells included in different strings ST may be referred to as a page PG. Accordingly, the memory block BLKi may include pages PG of the number of word lines WL1 to WL 16.

One memory cell can store one bit of data. This is commonly referred to as a Single Level Cell (SLC). In this case, one physical page PG may store one Logical Page (LPG) data. One Logical Page (LPG) data may include the same number of data bits as cells included in one physical page PG.

One memory cell can store two or more bits of data. In this case, one physical page PG may store two or more Logical Page (LPG) data.

Fig. 4 is a graph showing the default read voltage.

Referring to fig. 4, the horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells.

In fig. 4, it is assumed for convenience of description that the memory cell is programmed as a multi-level cell (MLC) storing two bits of data, but the present disclosure is not limited thereto.

Through the program operation, the memory cells included in one physical page may have threshold voltages belonging to threshold voltage distributions in the erase state E and any one of the first through third program states P1 through P3.

When the threshold voltages of the memory cells are sensed using the default read voltages R1, R2, and R3, the respective memory cells may be divided into the erase state E and any one of the first to third program states P1 to P3 according to data stored in the corresponding memory cells. R1 may be a default read voltage for dividing the erase state E and the first program state P1, R2 may be a default read voltage for dividing the first program state P1 and the second program state P2, and R3 may be a default read voltage for dividing the second program state P2 and the third program state P3. The level of the default read voltage may be determined to a specific voltage value through testing in a manufacturing process of the memory device, and the determined voltage value may be stored in the memory device.

At the beginning of the completion of the programming operation, the threshold voltage distributions of the memory cells may be of the form as shown in FIG. 4. However, after data is programmed, the threshold voltage may change due to long retention or due to excessive operation (disturbance) to another memory region.

Accordingly, as the change in the threshold voltage of the memory cell increases, more error bits may be included in the read data sensed by the default read voltage, and thus, the case of a read operation failure may increase.

Fig. 5 is a diagram illustrating a recovery algorithm.

Referring to fig. 5, when a read operation fails, a plurality of recovery algorithms may be executed until original data corresponding to the failed read operation is obtained.

In an embodiment, the plurality of recovery algorithms may include read retries, eBoost, soft decode operations, and the like.

The read retry may be an operation to retry the read operation using a read voltage different from the default read voltage. The read voltage for the read retry may be stored in advance in the memory device 100 or the memory controller 200.

The eBoost may be an operation of calculating an optimal read voltage and performing a read operation using the calculated optimal read voltage. Here, the optimum read voltage may be calculated by various methods. In an embodiment, the optimal read voltage may be calculated using gaussian modeling. Alternatively, the optimum read voltage may be calculated according to the number of "0" s or "1" s included in data read using a plurality of read voltages.

The soft decoding may be an operation of performing a read operation using a plurality of soft read voltages. Here, the plurality of soft read voltages may be determined based on a default read voltage or an optimal read voltage. For example, the plurality of soft read voltages may be voltages whose magnitudes increase or decrease at constant intervals based on a default read voltage or an optimal read voltage.

Fig. 6 is a diagram illustrating read retries.

Referring to fig. 6, a read retry table 610 indicating a read voltage for a read retry may be stored in advance in the memory device 100 or the memory controller 200.

For example, assume that the read retry table 610 includes 50 read voltages RRT0 through RRT 49. However, the number of read voltages included in the read retry table 610 may vary according to embodiments.

The memory controller 200 may select five read voltages RRT25, RRT3, RRT7, RRT0, and RRT34 among the 50 read voltages RRT0 to RRT49, and may perform a read operation using the selected five read voltages RRT25, RRT3, RRT7, RRT0, and RRT 34. For example, the memory controller 200 may perform a read operation by sequentially using the selected five read voltages RRT25, RRT3, RRT7, RRT0, and RRT34 until the read operation passes.

Fig. 7 is a diagram illustrating eBoost.

Fig. 7 is a diagram illustrating a generalization of threshold voltage distributions of states adjacent to each other among the erase state E and the first through third program states P1 through P3 of fig. 4.

Referring to fig. 7, the left threshold voltage distribution represents the threshold voltage distribution of the memory cell in the P (x) state, and the right threshold voltage distribution represents the threshold voltage distribution of the memory cell in the P (x +1) state.

The threshold voltages of the memory cells in the P (x) state and the P (x +1) state may change more than the beginning of programming completion, and thus, the threshold voltage distributions in the two states may overlap. In this case, even if the read operation is performed at the default read voltage, many error bits may be included in the read data.

The eBoost may be an operation of calculating an optimal read voltage and performing a read operation using the calculated optimal read voltage.

The memory controller 200 may obtain the optimal read voltage Vro by performing a read operation using the plurality of sampling voltages Vra and Vrb. For example, the memory controller 200 may calculate the optimum read voltage Vro using a change amount of the number of "0" or "1" or the number of "0" or "1" of sample data obtained using a plurality of sample voltages Vra and Vrb.

Further, in fig. 7, the plurality of sampling voltages for obtaining the optimal read voltage is two, but is not limited thereto, and the number of sampling voltages for obtaining the optimal read voltage may vary according to embodiments.

Fig. 8 is a diagram illustrating soft decoding.

Referring to fig. 8, the threshold voltage of the memory cell in the P (x) state and the threshold voltage of the memory cell in the P (x +1) state may be changed more than that of fig. 7. In this case, even if the read operation is performed at the optimum read voltage Vro, the read operation may fail.

The soft decoding may be a recovery algorithm that performs a read operation using a plurality of soft read voltages having different voltage levels. The plurality of soft read voltages for soft decoding may be voltages having a constant offset based on the optimal read voltage Vro.

The memory controller 200 may perform a read operation while changing the read voltage in the order of the first soft read voltage Vsoft1 to the fourth soft read voltage Vsoft 4.

Further, in fig. 8, the plurality of soft read voltages for soft decoding is four, but is not limited thereto, and the number of soft read voltages for soft decoding may vary according to embodiments.

The read operation processor 900 of fig. 9 may indicate the read operation processor 131 of fig. 1 and 2. The peripheral circuit 120 may be configured and operate the same as the peripheral circuit 120 described with reference to fig. 2.

Referring to fig. 9, the read operation processor 900 may include an optimum read voltage information storage 910, a read voltage controller 920, and a read operation controller 930.

The optimal read voltage information storage 910 may store optimal read voltage information determined according to a cell count value, which is the number of memory cells, among the plurality of memory cells, that are read as the first memory cell based on data read from the plurality of memory cells. At this time, the cell count value, which is the number of memory cells read as the first memory cells, may be the number of set logic values included in read data obtained from the plurality of memory cells by applying a specific read voltage to the plurality of memory cells. For example, the set logic value may be "1" when the first memory cell is in an on cell state or an on cell, and the set logic value may be "0" when the first memory cell is an off cell. As another example, the set logic value may be "0" when the first memory cell is in an on-cell state, and the set logic value may be "1" when the first memory cell is an off-cell. That is, the cell count value may be the number of "0" or "1" included in data read from the plurality of memory cells using a specific read voltage.

The optimum read voltage information may include information on an optimum read voltage predetermined by a test using a plurality of read voltages. That is, based on experimental results obtained through a plurality of read operations using a plurality of read voltages, the optimal read voltage information may be a lookup table including information on an optimal read voltage determined according to a cell count value.

In response to the optimal read voltage setting command input from the memory controller 200, the read voltage controller 920 may calculate a cell count value corresponding to a default read voltage based on data read from a plurality of memory cells using the default read voltage.

In an embodiment, the read voltage controller 920 may calculate a cell count value corresponding to a default read voltage based on a comparison result of a reference current and a current sensed from a plurality of memory cells using the default read voltage. For example, the read voltage controller 920 may sense a current flowing through a plurality of memory cells to which a default read voltage is applied and compare the sensed current with a reference current. The read voltage controller 920 may calculate a cell count value corresponding to a default read voltage based on a result of comparing the reference current with the current sensed using the default read voltage. At this time, the reference current may be determined as a specific current value through a test in a manufacturing process of the memory device 100, and the determined current value may be stored in the memory device 100.

In addition, the read voltage controller 920 may generate the first optimal read voltage based on the cell count value corresponding to the default read voltage and the optimal read voltage information. For example, the read voltage controller 920 may generate a first optimal read voltage corresponding to a cell count value corresponding to a default read voltage based on the optimal read voltage information. At this time, the first optimum read voltage may be set to a read voltage of a next read operation to be performed after a read operation using the default read voltage.

In an embodiment, the read voltage controller 920 may convert the cell count value corresponding to the default read voltage from an analog value form to a digital value form. In addition, the read voltage controller 920 may generate the first optimal read voltage based on the optimal read voltage information and the cell count value corresponding to the default read voltage converted into a digital value form.

The read operation controller 930 may control the peripheral circuit 120 to perform a read operation on the plurality of memory cells using the default read voltage.

For example, when the read operations for the plurality of memory cells fail, the read operation controller 930 may perform the read operation using the default read voltage in response to the read command input from the memory controller 200. At this time, the read operation using the default read voltage may be a read operation corresponding to a first recovery algorithm for recovering data corresponding to the failed read operation. In an embodiment, the first recovery algorithm may be a read retry.

In an embodiment, the read operation controller 930 may request some data read from a plurality of memory cells. One page including a plurality of memory cells may be divided and programmed. For example, one page can store data by four times of programming. In this case, the size of data stored in one page by one-time programming may be 1/4, which is the size of data stored in one page. For example, when it is assumed that the size of data storable in one page is 16KB, the size of data stored by one-time programming may be 4 KB. Since one page is divided and stores data, even if only some data read from one page is output, it is possible to determine whether a corresponding page is a program page or an erase page. Thus, by requesting only some data to be read from the plurality of memory cells, the read operation controller 930 can increase the speed of read operations to the plurality of memory cells.

In addition, when the read operation using the default read voltage fails, the read operation controller 930 may control the peripheral circuit 120 to perform the read operation on the plurality of memory cells using the first optimal read voltage. At this time, the read operation using the first optimal read voltage may be a read operation corresponding to a first recovery algorithm for recovering data corresponding to the failed read operation.

For example, when a read operation using the default read voltage fails, the read operation controller 930 may perform the read operation using the first optimal read voltage in response to a read command input from the memory controller 200.

In an embodiment, the read voltage controller 920 may calculate a cell count value corresponding to the first optimal read voltage based on data read from the plurality of memory cells using the first optimal read voltage. For example, the read voltage controller 920 may calculate a cell count value corresponding to a first optimal read voltage based on a comparison result of a reference current and a current sensed from a plurality of memory cells using the first optimal read voltage. For example, the read voltage controller 920 may sense a current flowing through a plurality of memory cells to which a first optimal read voltage is applied, and compare the sensed current with a reference current. The read voltage controller 920 may calculate a cell count value corresponding to the first optimal read voltage based on a result of comparing the reference current with the current sensed using the first optimal read voltage.

In addition, the read voltage controller 920 may generate a second optimal read voltage based on the optimal read voltage information and a cell count value corresponding to the first optimal read voltage. For example, the read voltage controller 920 may generate a second optimal read voltage corresponding to a cell count value corresponding to the first optimal read voltage based on the optimal read voltage information. At this time, the second optimal read voltage may be set to a read voltage of a next read operation to be performed after the read operation using the first optimal read voltage.

In an embodiment, the read voltage controller 920 may convert the cell count value corresponding to the first optimal read voltage from an analog value form to a digital value form. In addition, the read voltage controller 920 may generate the second optimal read voltage based on the cell count value corresponding to the first optimal read voltage converted into a digital value form and the optimal read voltage information.

In addition, when the read operation using the first optimal read voltage fails, the read operation controller 930 may control the peripheral circuit 120 to perform the read operation on the plurality of memory cells using the second optimal read voltage. At this time, the read operation using the second optimal read voltage may be a read operation corresponding to a second recovery algorithm for recovering data corresponding to the failed read operation. In an embodiment, the second recovery algorithm may be an eBoost operation.

For example, when a read operation using the first optimal read voltage fails, the read operation controller 930 may perform the read operation using the second optimal read voltage in response to a read command input from the memory controller 200.

In an embodiment, when a read operation using the second optimal read voltage fails, the read voltage controller 920 may generate a plurality of soft read voltages based on the second optimal read voltage. For example, the read voltage controller 920 may generate a plurality of soft read voltages that are voltages having a constant offset based on the second optimal read voltage.

In addition, the read operation controller 930 may control the peripheral circuit 120 to perform a plurality of read operations on the plurality of memory cells using the plurality of soft read voltages. At this time, the read operation using the plurality of soft read voltages may be a read operation corresponding to a third recovery algorithm for recovering data corresponding to the failed read operation. In an embodiment, the third recovery algorithm may be soft decoding.

According to an embodiment of the present disclosure, by generating an optimal read voltage to be used for a read operation corresponding to a recovery algorithm using a cell count value obtained by a specific read voltage and previously stored optimal read voltage information, a speed of the read operation of the recovery algorithm may be improved. Thus, the delay of the recovery algorithm can be reduced.

Referring to fig. 10, the read voltage controller 920 may obtain a current value Icell flowing through a plurality of memory cells to which a specific read voltage is applied. For example, the read voltage controller 920 may obtain the current value Icell by multiplying the number N of memory cells by the current value I flowing through one memory cell. At this time, a plurality of memory cells may be connected in units of blocks of the page buffer, and the current value Icell obtained from the plurality of memory cells may be obtained in units of blocks of the page buffer. Read voltage controller 920 may sense current value Icell using a sense node SO node and a transistor SO _ CS connected to the sense node SO node.

In addition, the read voltage controller 920 may calculate cell count values Sel <0> to Sel < i > based on a comparison result of the current Icell sensed from the plurality of memory cells and the reference current Iref. For example, the read voltage controller 920 may calculate a cell count value (i.e., Sel < i:0> -Icell-Iref) by a difference between the current Icell and the reference current Iref. At this time, the cell count value may be calculated in the form of an analog value. In this case, the read voltage controller 920 may convert the cell count value from an analog value form to a digital value form. Thereafter, the read voltage controller 920 may generate optimal read voltages OptimalLevel _ R1<7:0> to OptimalLevel _ SLC <7:0> based on the cell count value converted into the form of a digital value and the optimal read voltage information stored in the optimal read voltage information storage 910. At this time, when it is assumed that the memory cell is a tri-level cell storing three data bits, the read voltage controller 920 may generate an optimal read voltage from level 1 to level 7. In addition, the memory device 100 may generate an optimal read voltage to be applied during a read operation of a single level cell unit. The optimal read voltages OptimalLevel _ R1<7:0> through OptimalLevel _ SLC <7:0> may be stored in the characteristic parameters FP0<7:0> through FP7<7:0 >.

In an embodiment, the read voltage controller 920 may include a reference current setting Circuit Ref Circuit for setting the reference current Iref. The reference current setting Circuit Ref Circuit may include a plurality of transistors B0 to B4. The plurality of transistors B0 to B4 may be nMOS (n-type metal oxide semiconductor) transistors. In addition, the reference current setting Circuit Ref Circuit may include an enable transistor EN. According to an embodiment, the read voltage controller 920 may set various reference currents Iref using a reference current setting Circuit Ref Circuit. The reference current setting Circuit Ref Circuit may regulate the plurality of currents 0.5I to 16I using the plurality of transistors B0 to B4 and the enable transistor EN. The reference current setting Circuit Ref Circuit may set various reference currents Iref using a plurality of currents 0.5I to 16I.

Referring to fig. 11, the optimal read voltage information may be a lookup table indicating a relationship between a cell count value and an optimal read voltage to be used for a recovery algorithm.

The optimal read voltage information may include optimal read voltages corresponding to a plurality of cell count values (i.e., a first cell count value Sel <1> to an ith cell count value Sel < i >, where i is a natural number). At this time, the optimal read voltage information may include an optimal read voltage for each of the read retries and the eBoost.

For example, when the cell count value calculated by a previously performed specific read operation in the process of determining the optimum read voltage to be used for the read operation corresponding to the read retry is 20, the optimum read voltage to be used for the read operation corresponding to the read retry may be determined to be 2.0.

As another example, when a cell count value calculated by a previously performed specific read operation is 1 in a process of determining an optimal read voltage to be used for a read operation corresponding to the eBoost, the optimal read voltage to be used for the read operation corresponding to the eBoost may be determined to be 3.5.

Further, in fig. 11, one piece of optimum read voltage information is shown, but there may be optimum read voltage information for each level of the read voltage. For example, when it is assumed that the memory cell is a tri-level cell storing three data bits, the memory device 100 may store optimal read voltage information for each read voltage from level 1 to level 7. In addition, the memory device 100 may store optimal read voltage information of the read voltage of level 1 applied during the read operation of the single-level cell unit.

Fig. 12A is a diagram illustrating an optimal read voltage setting command according to an embodiment of the present disclosure. In addition, fig. 12B is a diagram illustrating an optimal read voltage obtaining command according to an embodiment of the present disclosure.

In an embodiment, the optimal read voltage set command EFh and the optimal read voltage get command EEh may be commands generated by a memory controller.

Referring to fig. 12A, when the optimal read voltage setting command EFh and the feature parameter selection command AA are input from the memory controller 200, the memory device 100 may store an optimal read voltage in the enabled feature parameters FP0 through FP 3. For example, when the optimum read voltage setting command EFh and the characteristic parameter selection command AA are input, the memory device 100 may perform a read operation on memory cells corresponding to the selected address ADD according to the read commands 00h to 3Xh, and calculate a cell count value corresponding to the corresponding read operation. In addition, the memory device 100 may generate an optimal read voltage based on the calculated cell count value and the optimal read voltage information and store the generated optimal read voltage in the characteristic parameters FP0 through FP 3.

Further, in fig. 12A, only the optimum read voltage setting operation for the feature parameters FP0 through FP3 is shown, but the same optimum read voltage setting operation may be performed for the other feature parameters FP4 through FP 7.

In addition, referring to fig. 12B, when the optimal read voltage obtaining command EEh is input from the memory controller 200, the memory device 100 may provide the optimal read voltage stored in the characteristic parameters FP0 through FP7 to the memory controller 200. The feature parameters FP 0-FP 6 may store the optimal read voltages R1-R7 from level 1 to level 7. The characteristic parameter FP7 may store the optimal read voltage SLC/SLCFW for a single level cell unit. For example, when the optimal read voltage obtaining command EEh and the feature parameter selection command BB are input from the memory controller 200, the memory device 100 may provide the optimal read voltage stored in the feature parameters FP0 through FP3 to the memory controller 200. When the optimal read voltage obtaining command EEh and the feature parameter selection command CC are input from the memory controller 200, the memory device 100 may provide the optimal read voltage stored in the feature parameters FP4 through FP7 to the memory controller 200.

The method illustrated in FIG. 13 may be performed, for example, by the memory device 50 illustrated in FIG. 1.

In step S1301, the memory device 50 may perform a read operation on a plurality of memory cells.

In step S1303, the storage device 50 may determine whether the read operation for the plurality of memory cells failed.

For example, the memory device 50 may determine whether the read operation passes by performing error correction decoding on the data read by the read operation.

When the read operation passes according to the determination result in step S1303, the storage device 50 may end the read operation.

In contrast, when the read operation fails according to the determination result in step S1303, the storage device 50 may execute one or more recovery algorithms.

For example, when the read operation fails according to the determination result in step S1303, the memory device 50 may generate an optimal read voltage in step S1305.

For example, the storage device 50 may generate an optimal read voltage to be used for a recovery algorithm based on a cell count calculated according to a read operation and previously stored optimal read voltage information.

In step S1307, the storage device 50 may perform a read operation corresponding to the recovery algorithm using the optimal read voltage.

In step S1309, the storage device 50 may determine whether the read operation corresponding to the optimal read voltage passes.

For example, the memory device 50 may determine whether the read operation passes by performing error correction decoding on data read by the read operation corresponding to the optimal read voltage.

When the read operation passes according to the determination result in step S1309, the storage apparatus 50 may end the read operation.

In contrast, when the read operation fails according to the determination result in step S1309, the storage device 50 may generate the optimal read voltage again and perform the read operation corresponding to the recovery algorithm using the optimal read voltage that is generated again.

In an embodiment, the method illustrated in fig. 14 may be a method of restoring the operation of the algorithm described by steps S1305, S1307, and S1309 illustrated in fig. 13.

The method illustrated in FIG. 14 may be performed, for example, by the memory device 50 illustrated in FIG. 1.

In step S1401, the storage device 50 may perform a read operation corresponding to the first recovery algorithm using a default read voltage. In an embodiment, the first recovery algorithm may be a read retry.

In step S1403, the storage device 50 may determine whether the read operation using the default read voltage passes. For example, the memory device 50 may perform error correction decoding on data read by a read operation using a default read voltage in a bit inversion method. At this time, the memory device 50 may determine whether the read operation using the default read voltage passes based on whether the error correction decoding passes/fails.

When the read operation using the default read voltage passes according to the determination result in step S1403, the storage device 50 may end the recovery algorithm operation.

In contrast, when the read operation using the default read voltage fails according to the determination result in step S1403, the storage device 50 may generate the first optimal read voltage based on the cell count value corresponding to the default read voltage and the optimal read voltage information in step S1405. For example, the storage device 50 may calculate a cell count value corresponding to a default read voltage based on a comparison result of a reference current and a current sensed from a plurality of memory cells using the default read voltage. Thereafter, the storage device 50 may generate a first optimal read voltage based on the cell count value corresponding to the default read voltage and the optimal read voltage information.

In step S1407, the memory device 50 may re-perform the read operation corresponding to the first recovery algorithm using the first optimal read voltage.

In step S1409, the memory device 50 may determine whether the read operation using the first optimal read voltage passes. For example, the memory device 50 may perform a min-sum method of error correction decoding on data read by a read operation using the first optimal read voltage. At this time, the memory device 50 may determine whether the read operation using the first optimal read voltage passes based on whether the error correction decoding passes/fails.

When the read operation using the first optimum read voltage passes according to the determination result in step S1409, the storage device 50 may end the resume algorithm operation.

In contrast, when the read operation using the first optimal read voltage fails according to the determination result of S1409 in step S1411, the storage device 50 may generate the second optimal read voltage based on the cell count value corresponding to the first optimal read voltage and the optimal read voltage information. For example, the storage device 50 may calculate a cell count value corresponding to a first optimal read voltage based on a comparison result of a reference current and a current sensed from a plurality of memory cells using the first optimal read voltage. Thereafter, the storage device 50 may generate a second optimal read voltage based on the cell count value corresponding to the first optimal read voltage and the optimal read voltage information.

In step S1413, the memory device 50 may perform a read operation corresponding to the second recovery algorithm using the second optimal read voltage. In an embodiment, the second recovery algorithm may be eBoost.

In step S1415, the memory device 50 may determine whether the read operation using the second optimal read voltage passes. For example, the memory device 50 may perform error correction decoding on data read by a read operation using the second optimal read voltage in a minimum sum method. At this time, the memory device 50 may determine whether the read operation using the second optimal read voltage passes based on whether the error correction decoding passes/fails.

When the read operation using the second optimum read voltage passes according to the determination result in step S1415, the memory device 50 may end the resume algorithm operation.

In contrast, when the read operation using the second optimal read voltage fails according to the determination result in step S1415, the memory device 50 generates a plurality of soft read voltages based on the second optimal read voltage in step S1417. For example, the memory device 50 may generate a plurality of soft read voltages having a constant offset based on the second optimal read voltage.

In step S1419, the memory device 50 may perform a read operation corresponding to the third recovery algorithm using the plurality of soft read voltages. In an embodiment, the third recovery algorithm may be soft decoding.

The method shown in FIG. 15 may be performed, for example, by the memory device 100 shown in FIGS. 1 and 2.

In step S1501, the memory device 100 may store optimal read voltage information determined according to a cell count value, which is the number of memory cells, among the plurality of memory cells, that are read as the first memory cells based on data read from the plurality of memory cells.

In step S1503, the memory device 100 may receive an optimal read voltage setting command from the memory controller.

In step S1505, in response to the optimal read voltage setting command, the memory device 100 may calculate a cell count value corresponding to a default read voltage based on data read from a plurality of memory cells using the default read voltage.

In step S1507, the memory device 100 may generate a first optimal read voltage based on the cell count value corresponding to the default read voltage and the optimal read voltage information.

Fig. 16 is a diagram illustrating the memory controller of fig. 1.

Referring to fig. 1 and 16, the memory controller 200 may include a processor 220, a RAM 230, an error correction circuit 240, a ROM 260, a host interface 270, and a flash interface 280.

The processor 220 may control the overall operation of the memory controller 200. The RAM 230 may be used as a buffer memory, a cache memory, an operation memory, and the like of the memory controller 200.

The error correction circuit 240 may perform error correction. The error correction circuit 240 may perform error correction coding (ECC coding) based on data to be written to the memory device through the flash interface 280. The error correction encoded data may be transferred to the memory device through the flash interface 280. The error correction circuit 240 may perform error correction decoding (ECC decoding) on data received from the memory device through the flash interface 280. For example, the error correction circuit 240 may be included in the flash interface 280 as a component of the flash interface 280.

The ROM 260 may store various information required for the controller 200 to operate in the form of firmware.

The storage controller 200 may communicate with external devices (e.g., host 300, application processor, etc.) through a host interface 270.

The memory controller 200 may communicate with the memory device 100 through a flash interface 280. The memory controller 1200 may transmit a command CMD, an address ADDR, a control signal CTRL, etc. to the memory device 100 and receive DATA through the flash interface 1280. For example, flash interface 280 may include a NAND interface.

Referring to fig. 17, the memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

The memory controller 2100 is connected to the memory device 2200. The memory controller 2100 is configured to access the memory device 2200. For example, the memory controller 2100 may be configured to control read operations, write operations, erase operations, and background operations of the memory device 2200. The memory controller 2100 is configured to provide an interface between the memory device 2200 and a host. The memory controller 2100 is configured to drive firmware for controlling the memory device 2200. The memory controller 2100 may be implemented identically to the memory controller 200 described with reference to fig. 1. The memory device 2200 may be implemented identically to the memory device 100 described with reference to FIG. 2.

For example, the memory controller 2100 may include components such as a Random Access Memory (RAM), a processor, a host interface, a memory interface, and an error corrector.

The memory controller 2100 may communicate with an external device through the connector 2300. The storage controller 2100 may communicate with external devices (e.g., hosts) according to a particular communication standard. For example, the storage controller 2100 is configured to communicate with external devices through at least one of various communication standards such as Universal Serial Bus (USB), multi-media card (MMC), embedded MMC (emmc), Peripheral Component Interconnect (PCI), PCI express (PCI-E), Advanced Technology Attachment (ATA), serial ATA, parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash (UFS), Wi-Fi, bluetooth, and NVMe. For example, the connector 2300 may be defined by at least one of the various communication standards described above.

For example, the memory device 2200 may be configured by various non-volatile memory elements such as electrically erasable programmable rom (eeprom), NAND flash memory, NOR flash memory, phase change RAM (pram), resistive RAM (reram), ferroelectric RAM (fram), and spin torque transfer magnetic RAM (STT-MRAM).

The memory controller 2100 and the memory device 2200 may be integrated into one semiconductor device to configure a memory card. For example, the memory controller 2100 and the memory device 2200 may be integrated into one semiconductor device to configure a memory card such as a PC card (personal computer memory card international association (PCMCIA)), a compact flash Card (CF), a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro, or eMMC), an SD card (SD, miniSD, microSD, or SDHC), and a universal flash memory (UFS).

Fig. 18 is a block diagram illustrating a Solid State Drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

Referring to fig. 18, the SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals SIG with the host 3100 through the signal connector 3001, and receives power PWR through the power connector 3002. The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply device 3230, and a buffer memory 3240.

According to an embodiment of the present disclosure, the SSD controller 3210 may perform the functions of the storage controller 200 described with reference to fig. 1.

The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal SIG received from the host 3100. For example, signal SIG may be a signal based on an interface between host 3100 and SSD 3200. For example, the signal SIG may be a signal defined by at least one of interfaces such as Universal Serial Bus (USB), multimedia card (MMC), embedded MMC (emmc), Peripheral Component Interconnect (PCI), PCI express (PCI-E), Advanced Technology Attachment (ATA), serial ATA, parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash (UFS), Wi-Fi, bluetooth, and NVMe.

The auxiliary power supply device 3230 is connected to the host 3100 through a power supply connector 3002. The auxiliary power supply device 3230 may receive power PWR from the host 3100 and may be charged with the power. When the power supply from the host 3100 is not smooth, the auxiliary power supply device 3230 may provide the power of the SSD 3200. For example, the auxiliary power supply device 3230 may be provided in the SSD 3200 or may be provided outside the SSD 3200. For example, the auxiliary power supply device 3230 may be provided on a main board and may supply auxiliary power to the SSD 3200.

The buffer memory 3240 operates as a buffer memory of the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or may temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322 n. The buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

Fig. 19 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present disclosure is applied.

Referring to fig. 19, the user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

The application processor 4100 may drive components, an Operating System (OS), user programs, and the like included in the user system 4000. For example, the application processor 4100 may include a controller, an interface, a graphic engine, etc. that controls components included in the user system 4000. The application processor 4100 may be provided as a system on chip (SoC).

The memory module 4200 may operate as a main memory, working memory, buffer memory, or cache memory of the user system 4000. The memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDARM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 may be packaged on a Package On Package (POP) basis and provided as one semiconductor package.

The network module 4300 may communicate with an external device. For example, the network module 4300 may support wireless communication such as Code Division Multiple Access (CDMA), global system for mobile communications (GSM), wideband CDMA (wcdma), CDMA-2000, Time Division Multiple Access (TDMA), long term evolution, Wimax, WLAN, UWB, bluetooth, and Wi-Fi. For example, the network module 4300 may be included in the application processor 4100.

The memory module 4400 may store data. For example, the memory module 4400 may store data received from the application processor 4100. Alternatively, the memory module 4400 may transmit data stored in the memory module 4400 to the application processor 4100. For example, the memory module 4400 may be implemented as a nonvolatile semiconductor memory element such as a phase change ram (pram), a magnetic ram (mram), a resistance ram (rram), a NAND flash memory, a NOR flash memory, and a three-dimensional NAND flash memory. For example, the memory module 4400 may be provided as a removable storage device (removable drive) such as a memory card and an external drive of the user system 4000.

For example, the memory module 4400 may include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices may operate the same as the memory device 100 described with reference to fig. 1. The memory module 4400 may operate the same as the memory device 50 described with reference to fig. 1.

The user interface 4500 may include an interface for inputting data or instructions to the application processor 4100 or for outputting data to an external device. For example, user interface 4500 may include user input interfaces such as keyboards, keypads, buttons, touch panels, touch screens, touch pads, touch balls, cameras, microphones, gyroscope sensors, vibration sensors, and piezoelectric elements. The user interface 4500 may include user output interfaces such as Liquid Crystal Displays (LCDs), Organic Light Emitting Diode (OLED) display devices, active matrix OLED (amoled) display devices, LEDs, speakers, and monitors.

Cross Reference to Related Applications

The present application claims priority from korean patent application No. 10-2020-0101424, filed on 12.8.2020 by the korean intellectual property office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device, the memory device comprising:

a plurality of memory cells;

an optimum read voltage information storage configured to store optimum read voltage information determined according to a cell count value that is the number of memory cells, among the plurality of memory cells, that are read as first memory cells based on data read from the plurality of memory cells; and

a read voltage controller configured to calculate a cell count value corresponding to a default read voltage based on data read from the plurality of memory cells using the default read voltage in response to an optimal read voltage setting command input from the memory controller, and to generate a first optimal read voltage based on the cell count value corresponding to the default read voltage and the optimal read voltage information.

2. The memory device of claim 1, wherein the first memory cell is an on cell or an off cell.

3. The memory device according to claim 1, wherein the read voltage controller converts the cell count value corresponding to the default read voltage from an analog value form to a digital value form, and generates the first optimum read voltage based on the cell count value converted to the digital value form and the optimum read voltage information.

4. The memory device of claim 1, further comprising:

peripheral circuitry configured to perform a read operation that senses the plurality of memory cells; and

a read operation controller configured to control the peripheral circuitry to perform the read operation on the plurality of memory cells using the default read voltage.

5. The memory device of claim 4, wherein the read operation controller requests some of the data read from the plurality of memory cells.

6. The memory device according to claim 4, wherein the read voltage controller calculates the cell count value corresponding to the misread voltage based on a result of comparison of currents sensed from the plurality of memory cells using the misread voltage with a reference current.

7. The memory device according to claim 5, wherein the read operation controller controls the peripheral circuit to perform the read operation on the plurality of memory cells using the first optimum read voltage when the read operation using the default read voltage fails.

8. The memory device according to claim 7, wherein the read voltage controller calculates a cell count value corresponding to the first optimal read voltage based on data read from the plurality of memory cells using the first optimal read voltage, and generates a second optimal read voltage based on the cell count value corresponding to the first optimal read voltage and the optimal read voltage information.

9. The memory device according to claim 8, wherein the read voltage controller calculates the cell count value corresponding to the first optimum read voltage based on a result of comparison of a current sensed from the plurality of memory cells using the first optimum read voltage and a reference current.

10. The memory device of claim 8, wherein the read operation controller controls the peripheral circuit to perform the read operation on the plurality of memory cells using the second optimal read voltage when the read operation using the first optimal read voltage fails.

11. The memory device of claim 10, wherein the read voltage controller generates a plurality of soft read voltages based on the second optimal read voltage when a read operation using the second optimal read voltage fails.

12. The memory device of claim 11, wherein the read operation controller controls the peripheral circuitry to perform a plurality of read operations on the plurality of memory cells using the plurality of soft read voltages.

13. A memory device, the memory device comprising:

a memory device including a plurality of memory cells and configured to store optimal read voltage information determined according to a cell count value, which is a number of memory cells, among the plurality of memory cells, that are read as first memory cells based on data read from the plurality of memory cells; and

a memory controller configured to execute one or more recovery algorithms for recovering data corresponding to a failed read operation among read operations performed on the memory device,

wherein the memory controller controls the memory device to generate a read voltage used in a recovery algorithm to be currently executed among the one or more recovery algorithms based on the optimal read voltage information and a cell count value calculated according to a read operation corresponding to a previously executed recovery algorithm among the one or more recovery algorithms.

14. The memory device of claim 13, wherein the first memory cell is an on cell or an off cell.

15. The memory device of claim 13, wherein the memory controller controls the memory device to perform a read operation corresponding to a first recovery algorithm among the one or more recovery algorithms using a default read voltage.

16. The memory device according to claim 15, wherein when the read operation using the default read voltage fails, the memory controller controls the memory device to calculate a cell count value corresponding to the default read voltage based on a result of comparison of a current sensed from the plurality of memory cells using the default read voltage with a reference current, and to generate a first optimum read voltage based on the cell count value corresponding to the default read voltage and the optimum read voltage information.

17. The memory device of claim 16, wherein the memory controller controls the memory device to re-perform the read operation corresponding to the first recovery algorithm using the first optimal read voltage.

18. The memory device according to claim 17, wherein when the read operation using the first optimal read voltage fails, the memory controller controls the memory device to calculate a cell count value corresponding to the first optimal read voltage based on a result of comparison of a current sensed from the plurality of memory cells using the first optimal read voltage and the reference current, and to generate a second optimal read voltage based on the cell count value corresponding to the first optimal read voltage and the optimal read voltage information.

19. The memory device of claim 18, wherein the memory controller controls the memory device to perform a read operation corresponding to a second recovery algorithm of the one or more recovery algorithms using the second optimal read voltage.

20. The memory device of claim 19, wherein when the read operation using the second optimal read voltage fails, the memory controller controls the memory device to generate a plurality of soft read voltages based on the second optimal read voltage and to perform a third recovery algorithm of the one or more recovery algorithms using the plurality of soft read voltages.

21. A method of operating a memory device comprising a plurality of memory cells, the method comprising:

storing optimal read voltage information determined according to a cell count value, which is the number of memory cells, among the plurality of memory cells, that are read as first memory cells based on data read from the plurality of memory cells;

receiving an optimal read voltage setting command from a memory controller;

calculating a cell count value corresponding to a default read voltage based on data read from the plurality of memory cells using the default read voltage in response to the optimal read voltage setting command; and

generating a first optimal read voltage based on the cell count value corresponding to the default read voltage and the optimal read voltage information.

22. The method of claim 21, wherein the first memory cell is an on cell or an off cell.