CN114077718A - Matrix calculation circuit, matrix calculation method, electronic device, and computer-readable storage medium - Google Patents

Abstract

The embodiment of the disclosure discloses a matrix calculation circuit, a matrix calculation method, electronic equipment and a computer-readable storage medium. Wherein the matrix calculation circuit includes: a first data reading circuit for reading a plurality of first data in the first matrix according to a read address of the first matrix; generating a second data read control signal according to the plurality of first data; the second data reading circuit is used for reading a plurality of second data in the second matrix according to the second data reading control signal and the reading address of the second matrix; and the calculation circuit is used for calculating third data according to the plurality of first data and the plurality of second data. The matrix calculation circuit generates the reading control signal of the second data through the plurality of read first data, and solves the problem that calculation time is wasted due to the fact that data which do not need to be calculated are calculated in the prior art.

Description

Matrix computing circuit, method, electronic device, and computer-readable storage medium

technical field

The present disclosure relates to the field of processors, and in particular, to a matrix computing circuit, method, electronic device, and computer-readable storage medium.

Background technique

With the development of science and technology, human society is rapidly entering the era of intelligence. An important feature of the intelligent age is that people obtain more and more types of data, the amount of data obtained is increasing, and the speed of processing data is getting higher and higher. The chip is the cornerstone of task distribution, and it fundamentally determines people's ability to process data. From the perspective of application fields, there are two main routes for chips: one is general-purpose chip routes, such as CPU, which can provide great flexibility, but the effective computing power is relatively low when processing algorithms in specific fields; the other is dedicated chips Routes, such as TPU, can exert high effective computing power in some specific fields, but in the face of flexible and more general fields, their processing power is relatively poor or even impossible. Due to the wide variety and huge amount of data in the intelligent era, chips are required to have extremely high flexibility, capable of processing algorithms in different fields and changing with each passing day, and extremely strong processing capabilities to rapidly process huge and rapidly growing data. quantity.

In neural network computing, convolution computing accounts for most of the total computing volume, and convolution computing can be converted into matrix multiplication computing, so it is necessary to improve the throughput of neural network tasks, reduce latency, and improve the effective computing power of the chip , the focus is to improve the speed of matrix multiplication calculations.

Figure 1a is a schematic diagram of a matrix multiplication calculation in a neural network. As shown in Figure 1a, M1 is the data matrix, M2 is the parameter matrix, and M is the output matrix. A row of data in M1 and a column of parameters in M2 are multiplied and added to obtain a data in M.

Fig. 1b is a hardware structure diagram used for matrix calculation. As shown in Figure 1b, in order to better improve the speed of matrix calculation and improve the efficiency of data utilization, the calculation unit array is often used to realize the matrix operation. Taking an array composed of MxN (M>1, N>1) computing units as an example, the data can be fully utilized through the computing unit array. For example, an element in M1 can be simultaneously multiplexed by N computing units in the same row, and an element in M2 can be simultaneously multiplexed by M computing units in the same column. One column of elements of M1 and one row of elements of M2 can be calculated at a time.

The above scheme has the following disadvantages: many data matrices and/or parameter matrices in neural networks are sparse matrices, that is, there are a large number of 0s in the data of the matrix, and such 0 elements will also be calculated as normal elements, which will waste computing time. Reduce the performance of chip computing power and increase power consumption.

SUMMARY OF THE INVENTION

This Summary is provided to introduce concepts in a simplified form that are described in detail in the Detailed Description section that follows. This summary section is not intended to identify key features or essential features of the claimed technical solution, nor is it intended to be used to limit the scope of the claimed technical solution.

In order to solve the technical problems of inflexible task assignment and complex control of processing cores in the prior art, the embodiments of the present disclosure propose the following technical solutions:

In a first aspect, an embodiment of the present disclosure provides a matrix calculation circuit, characterized in that it includes:

a first data reading circuit, configured to read a plurality of first data in the first matrix according to a read address of the first matrix; generate a second data read control signal according to the plurality of first data;

a second data read circuit, configured to read a plurality of second data in the second matrix according to the second data read control signal and the read address of the second matrix;

A calculation circuit, configured to calculate and obtain third data according to the plurality of first data and the plurality of second data.

Further, the first data reading circuit is configured to generate a second data reading control signal according to the plurality of first data, including:

The first data read circuit is configured to generate the second data read control signal according to whether each data of the plurality of data is zero.

Further, generating the second data read control signal according to whether each of the plurality of data is zero, specifically includes:

in response to the value of each of the plurality of first data being zero, generating the second data read control signal indicating the accumulation of the read address of the second matrix; or,

In response to the value of at least one of the plurality of first data being non-zero, generating a signal instructing the second data read circuit to read the plurality of second data according to the read address of the second matrix the second data read control signal.

Further, the first data reading circuit includes:

a first value comparison circuit, configured to determine whether the value of each of the plurality of first data is zero;

The first control circuit is configured to generate the second data read control signal according to the judgment result of the first numerical comparison circuit.

Further, the second data reading circuit also includes:

a second value comparison circuit, configured to determine whether the value of each of the plurality of second data is zero;

The second control circuit is configured to generate a calculation control signal according to the judgment result of the second numerical value comparison circuit.

Further, the second control circuit is used for:

The calculation control signal is generated to instruct the calculation circuit to perform a calculation operation in response to at least one of the plurality of second data being non-zero.

Further, the first control circuit includes:

a first control signal generating circuit, configured to generate a first control signal according to the judgment result of the first numerical comparison circuit;

The first read address generation circuit is configured to accumulate the read addresses of the first matrix to obtain a new read address of the first matrix.

Further, the plurality of first data is a column of first data in the first matrix; the plurality of second data is a row of second data in the second matrix.

Further, the computing circuit includes:

a computing unit array, wherein the computing unit array includes a plurality of computing units;

Each row of computing units in the computing unit array respectively receives the plurality of first data;

Each column of computing units in the computing unit array respectively receives the plurality of second data. In a second aspect, an embodiment of the present disclosure provides a matrix calculation method, characterized in that it includes:

Read a plurality of first data in the first matrix according to the read address of the first matrix;

generating a second data read control signal according to the plurality of first data;

Read a plurality of second data in the second matrix according to the second data read control signal and the read address of the second matrix;

The third data is calculated and obtained according to the plurality of first data and the plurality of second data. In a third aspect, an embodiment of the present disclosure provides a chip, including the matrix computing circuit described in any one of the first aspect.

In a fourth aspect, embodiments of the present disclosure provide an electronic device, including: a memory for storing computer-readable instructions; and one or more processors for executing the computer-readable instructions, so that the processors run When implementing the matrix calculation method described in any one of the foregoing first aspects.

In a fifth aspect, an embodiment of the present disclosure provides a non-transitory computer-readable storage medium, characterized in that the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to cause a computer to execute the foregoing first aspect. Any of the described matrix calculation methods.

In a sixth aspect, an embodiment of the present disclosure provides a computer program product, which is characterized by comprising computer instructions, and when the computer instructions are executed by a computing device, the computing device can execute any one of the foregoing first aspects. Matrix calculation method.

In a seventh aspect, an embodiment of the present disclosure provides a computing device, characterized by comprising one or more chips according to the third aspect.

Embodiments of the present disclosure disclose a matrix computing circuit, method, electronic device, and computer-readable storage medium. Wherein the matrix calculation circuit includes: a first data reading circuit for reading a plurality of first data in the first matrix according to the read address of the first matrix; generating a second data reading according to the plurality of first data a control signal; a second data reading circuit for reading a plurality of second data in the second matrix according to the second data reading control signal and the read address of the second matrix; a calculation circuit for reading a plurality of second data according to the second matrix The plurality of first data and the plurality of second data are calculated to obtain third data. The above-mentioned matrix calculation circuit generates a read control signal of the second data by using the plurality of read first data, which solves the problem of wasting calculation time caused by calculating the data that does not need to be calculated in the prior art.

The above description is only an overview of the technical solutions of the present disclosure. In order to understand the technical means of the present disclosure more clearly, it can be implemented according to the content of the description, and to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand , the following specific preferred embodiments, and in conjunction with the accompanying drawings, are described in detail as follows.

Description of drawings

The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent when taken in conjunction with the accompanying drawings and with reference to the following detailed description. Throughout the drawings, the same or similar reference numbers refer to the same or similar elements. It should be understood that the drawings are schematic and that the originals and elements are not necessarily drawn to scale.

1a and 1b are schematic diagrams of the prior art of the disclosure;

FIG. 2 is a schematic structural diagram of a matrix calculation circuit provided by an embodiment of the present disclosure;

3 is a schematic diagram of a storage format of a first matrix provided by an embodiment of the present disclosure;

FIG. 4 is a schematic structural diagram of a first data reading circuit provided by an embodiment of the present disclosure;

5 is a schematic structural diagram of a second data reading circuit provided by an embodiment of the present disclosure;

6a-6e are schematic diagrams of an application example of an embodiment of the present disclosure;

FIG. 7 is a flowchart of a matrix calculation method provided by an embodiment of the present disclosure.

Detailed ways

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for the purpose of A more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes, and are not intended to limit the protection scope of the present disclosure.

It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and/or in parallel. Furthermore, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present disclosure is not limited in this regard.

As used herein, the term "including" and variations thereof are open-ended inclusions, ie, "including but not limited to". The term "based on" is "based at least in part on." The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions of other terms will be given in the description below.

It should be noted that concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or interdependence.

It should be noted that the modifications of "a" and "a plurality" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless the context clearly indicates otherwise, they should be understood as "one or a plurality of". multiple".

The names of messages or information exchanged between multiple devices in the embodiments of the present disclosure are only for illustrative purposes, and are not intended to limit the scope of these messages or information.

FIG. 2 is a schematic diagram of a matrix calculation circuit provided by an embodiment of the present disclosure. The matrix calculation circuit (EU) 200 provided by this embodiment includes:

A first data reading circuit (LD_M1) 201, the first data reading circuit is used to read a plurality of first data in the first matrix according to the read address of the first matrix; according to the plurality of first data generating a second data read control signal;

A second data read circuit (LD_M2) 202, the second data read circuit is configured to read a plurality of second data in the second matrix according to the second data read control signal and the read address of the second matrix data;

The calculation circuit 203 is configured to calculate and obtain third data according to the plurality of first data and the plurality of second data.

Exemplarily, the read address of the first matrix is the first storage address of the first matrix, and the read address of the second matrix is the first storage address of the second matrix. The storage first address of the first matrix and the storage first address of the second matrix are obtained by the instruction decoding circuit ID (Instruction Decoder), and the instruction decoding circuit is used to decode the matrix calculation instruction to obtain the storage first address of the first matrix, the second Parameters such as the storage address of the matrix and the size of the first matrix and the second matrix.

Exemplarily, the matrix calculation instruction includes an instruction type, a first storage address of the first matrix involved in the calculation, a storage first address of the second matrix, and size parameters of the first matrix and the second matrix. In one embodiment, the instruction type is a matrix multiplication instruction, the first matrix is a data matrix in a neural network convolution calculation, and the second matrix is a parameter matrix in a neural network convolution calculation; wherein, The first matrix and/or the second matrix are sparse matrices, and a large number of elements in the sparse matrix are 0. It can be understood that the storage first address of the matrix in the matrix calculation instruction and the size parameters of the matrix (such as the number of rows and columns of the matrix) can be expressed in the form of register addresses, and the instruction decoding circuit shown is from the corresponding register address. Get the corresponding data.

In this embodiment of the present disclosure, the first data reading circuit 201 receives the first address of the first matrix decoded by the instruction decoding circuit, and generates a reading address of the first matrix according to the first address; A read address of a matrix reads out a plurality of first data in the first matrix at one time. Exemplarily, the plurality of first data is data of one column in the first matrix, and when the first matrix is stored, it is stored in the order of columns first and then rows, that is, stored column by column. As shown in FIG. 3 , the first matrix M1 stores a11-a41 first, then stores a12-a42, and so on until the entire first matrix is stored in the order of first column and then row. a11-a44 are stored logically consecutively. Set the storage first address of the first matrix as PD, and set the number of rows of the first matrix as L1, then each time the first data reading circuit reads the first data according to the current storage first address, after reading After one column of data in the first matrix, automatically add L1 to the read address of the first matrix, that is, PD=PD+L1, to obtain the first read address of the next first matrix, until the number of reads reaches the number of times of the first matrix. up to the number of columns. Taking M1 as shown in FIG. 3 as an example, PD=PD+4.

In this embodiment of the present disclosure, after the first data reading circuit 201 reads the plurality of first data, a second data read control signal is generated according to the plurality of first data. In matrix calculation, the matrix involved in the calculation may be a sparse matrix, that is, many data in the first matrix are 0. At this time, many calculations can actually be skipped. For example, in matrix multiplication, a data in the first matrix is is 0, no matter what the value of the corresponding second data of the second matrix is, the result is 0, and the calculation may not be performed. Therefore, optionally, the first data reading circuit is configured to generate the second data reading control signal according to the plurality of first data, including: the first data reading circuit is configured to generate the second data reading control signal according to the The second data read control signal is generated whether each of the plurality of data is zero.

Specifically, in response to the value of each of the plurality of first data being zero, the second data read control signal indicating the accumulation of the read address of the second matrix is generated; or, in response to The value of at least one data in the plurality of first data is not zero, and generating the second data reading circuit that instructs the second data reading circuit to read the plurality of second data according to the current read address of the second matrix. The second data read control signal.

In this embodiment, if the value of each of the plurality of data is 0, the corresponding plurality of second data may not be read, and at this time, a second data read control signal is generated to instruct the accumulation of all data. The read address of the second matrix, skip the reading of the current multiple second data; if the value of at least one of the multiple data is not zero, it means that the calculation needs to be performed, and the second data is generated at this time. The data read control signal instructs the second data read circuit to read a plurality of second data corresponding to the plurality of first data according to the current read address of the second matrix.

In the embodiment of the present disclosure, the second data reading circuit 202 receives the first address of the second matrix decoded by the instruction decoding circuit, and according to the first address and the first address generated by the first data reading circuit 201 The second data read control signal generates a read address of the second matrix to read a plurality of second data in the second matrix. Optionally, the second data reading circuit reads a row of data in the second matrix each time, and when storing the second matrix, it is stored in the order of the second matrix row first and then the column, that is, row by row storage, each row is stored. Read one row at a time, set the storage first address of the second matrix to be PW, and set the number of columns of the second matrix to be L2, then each time the second data reading circuit reads, it reads the first storage address according to the current storage first address. Two data, after reading a row of data of the second matrix, automatically add L2 to the read address of the second matrix, that is, PW=PW+L2, to obtain the first read address of the second matrix next time, until the read address of the second matrix is read. Take the number of times until the number of rows of the second matrix is reached.

Specifically, the second data read circuit needs to determine the actual read address of the second matrix according to the second data read control signal and the current read address of the second matrix. If the second data read control signal indicates to accumulate the read addresses of the second matrix, use PW=PW+L2 to obtain a new read address of the second matrix, and then continue to wait for a new read of the second data Take the control signal; if the second data read control signal instructs to read the second data through the current read address of the second matrix, first read out a plurality of second data through PW, and then pass PW=PW +L2 calculates the next read address of the second matrix, and waits for a new second data read control signal.

After obtaining the plurality of first data and the plurality of second data, the calculation unit performs the calculation indicated by the matrix calculation instruction according to the plurality of first data and the plurality of second data to obtain The third data, wherein the third data is the data or part of the data in the output matrix.

Optionally, the calculation circuit includes: a calculation unit array, wherein the calculation unit array includes a plurality of calculation units; each row of calculation units in the calculation unit array respectively receives the plurality of first data; the Each column of computing units in the computing unit array respectively receives the plurality of second data. Specifically, as shown in FIG. 2 , the computing circuit includes a computing unit array, which includes a plurality of computing units PU, and each row of computing units respectively receives one of the plurality of first data. Taking M1 in FIG. 3 as an example, When the fetched column of first data is a11-a41, the first row computing unit receives a11, the second row computing unit receives a21, the third row computing unit receives a31, and the fourth row computing unit receives a41. Each column of calculation units in the calculation unit array respectively receives the plurality of second data. Similar to the above example, each column of calculation units receives the same second data, and different columns of calculation units receive different second data. The situation will be described later and will not be repeated here.

As shown in FIG. 4, in order to realize the function of the above-mentioned first data reading circuit, optionally, the first data reading circuit further includes:

a first value comparison circuit 401 (Z_D), for judging whether the value of each of the plurality of first data is zero;

The first control circuit 402 ( Ctrl1 ) is configured to generate the second data read control signal according to the judgment result of the first numerical comparison circuit.

As shown in FIG. 4 , the first value comparison circuit 401 includes a plurality of data comparison buffer circuits Z_Det. After reading a plurality of first data from the memory or storage area M1, each first data is buffered into a Z_Det circuit In the Z_Det circuit, it is judged whether the first data is 0, and the judgment result Z ₀ -Z _M-1 is obtained. Exemplarily, the Z_Det circuit includes an OR gate circuit and a NOT gate circuit, wherein the OR gate circuit includes X input terminals, where X is the number of bits of the first data, and each input terminal corresponds to the first A bit in the data; exemplarily, the X=4, then the OR gate circuit includes 4 input terminals, corresponding to each bit of the first data Data[3:0] respectively, through the OR gate circuit After performing bitwise logical OR operation on each bit of the first data, a judgment result is obtained through the NOT gate circuit; exemplarily, if the first data is 1110, then bitwise logical OR operation is performed to obtain a result of 1, and then If the result obtained through the NOT gate circuit is 0, then it is judged that the first data is not 0; if the first data is 0000, then the bitwise logical OR operation is performed and the result is 0, and then the result obtained through the NOT gate circuit is 1, Then it is judged that the first data is 0. It can be understood that the Z_Det may not include the NOT gate circuit. At this time, when the result output by the OR gate is 1, it is judged that the first data is not 0, and when the result outputted by the OR gate is 0, it is judged that the The first data is 0.

As shown in FIG. 4 , the plurality of judgment results Z ₀ -Z _M-1 of the plurality of data comparison buffer circuits Z_Det are input to the first control circuit 402 , and the first control circuit 402 compares according to the first value The judgment result of the circuit generates the second data read control signal C1. Exemplarily, the first control circuit includes a first read address generation circuit AG1 and a first control signal generation circuit CL1, wherein the first control signal generation circuit CL1 receives the plurality of judgment results Z ₀ -Z _{M -1} to generate the second data read control signal C1, the exemplary first control signal generation circuit CL1 includes an AND gate circuit with multiple input terminals, each input terminal of the AND gate circuit is respectively used for receiving A described judgment result Z ₀ -Z _M-1 ; when the Z ₀ -Z _M-1 are all 1, C1 is 1; when not all of the Z ₀ -Z _M-1 are 0, C1 is 0. The second data reading circuit 202 receives the second data reading control signal C1, if the C1 is 1, indicating that the plurality of first data retrieved are all 0, the second data reading circuit 202 Accumulate the read addresses of the second matrix, and do not read the second data corresponding to the plurality of first data; if the C1 is 0, indicating that the plurality of second data fetched are not all 0, then the first data A data reading circuit 201 reads a plurality of second data corresponding to the plurality of first data according to the current read address of the second matrix.

As shown in FIG. 5 , in order to realize the function of the above-mentioned second data reading circuit, optionally, the second data reading circuit further includes:

A second value comparison circuit 501 (DB), configured to determine whether the value of each of the plurality of second data is zero;

The second control circuit 502 ( Ctrl2 ) is configured to generate a calculation control signal according to the judgment result of the second numerical value comparison circuit.

Optionally, the structure of the second numerical comparison circuit 501 is the same as that of the first numerical comparison circuit 401, and also includes a plurality of data comparison buffer circuits, which determine each data in the plurality of second data. The step of whether the value of is zero is the same as the step of determining whether the value of each of the plurality of first data is zero by the above-mentioned first numerical comparison circuit, which is not repeated here.

The second control circuit 502, when the judgment result of the second data comparison circuit is that each second data is 0, generates a calculation control signal C_Start to be 0, so that the calculation circuit does not perform calculation; If the judgment result of the second data comparison circuit is that at least one second data in the plurality of second data is not 0, the generated calculation control signal C_Start is 1, so that the calculation circuit can make the calculation circuit according to the plurality of first data. The data and the plurality of second data are calculated to obtain third data.

Optionally, the second control circuit 502 further includes: a second read address generation circuit AG2 and a second control signal generation circuit CL2, wherein the second control signal generation circuit CL2 is used to read the circuit according to the second data The control signal generates the control signal of the second read address generation circuit AG2 and generates the calculation control signal according to the judgment result of the second data comparison circuit. The second read address generation circuit AG2 is used for The read address of the second matrix is generated by taking the control signal of the address generating circuit AG2. Exemplarily, after obtaining the first read address of the second data sent by the decoding circuit, the second read address generation circuit AG2 determines whether the read address of the second matrix needs to be accumulated according to the C1 signal, if If the C1 signal is 1, AG2 accumulates the read address of the second matrix; if the C1 signal is 0, then AG2 does not accumulate the read address of the second matrix, and the second data read circuit LD_M2 reads from the memory or storage area. A plurality of second data are read in M2.

6a-6e are examples of the calculation process of the matrix calculation circuit in the above embodiment. As shown in FIG. 6a, for the matrix multiplication calculation to be performed by the matrix calculation circuit, M1 is the first matrix, M2 is the second matrix, and M is the third matrix obtained by multiplying the M1 and M2 matrices.

As shown in FIG. 6b, it is an overall schematic diagram of using a matrix computing circuit to perform the above-mentioned matrix multiplication. The matrix calculation circuit includes a 2*2 calculation unit array, one column and two first data read by LD_M1 are respectively input to each row in the calculation unit array, and one row and two second data read by LD_M2 are respectively Input to each column in the array of calculation units, and obtain the third matrix M after three clock cycles of calculation.

As shown in Figure 6c, it is the process of the first fetching and the first calculation. LD_M1 takes out the first data 1 and 0 of the first column of the first matrix, buffers them into Z_Det, Z_Det outputs the judgment result 01 to Ctrl1, and Ctrl1 performs a bitwise AND logical operation on 01 to obtain C1=0; LD_M2 according to C1=0, according to the current The read address of the second matrix reads the second data 1 and 2 of the first row in the second matrix, and buffers them in the DB. If the DB judges that the second data is not all 0, it generates the calculation control signal C_Start=1, so that the calculation The cell array performs the calculation, where 1 and 1 are input to the input of PU _0,0 , and the product is calculated as 1; 1 and 2 are input to the input of _{PU 0,1} , and the product is calculated as 2; 1, the calculation product is 0; the input terminals of PU _1,1 input 0 and 2, and the calculation product is 0; thus, the result M_temp of the first calculation is obtained. After reading the one column of the first data, the LD_M1 accumulates the read addresses of the first matrix; after reading the row of the second data, the LD_M2 accumulates the read addresses of the second matrix.

As shown in Figure 6d, it is the process of the second fetching and the second calculation. LD_M1 takes out the first data 0 and 0 of the second column of the first matrix, buffers them into Z_Det, Z_Det outputs the judgment result 11 to Ctrl1, and Ctrl1 performs a bitwise AND logical operation on 11 to obtain C1=1; LD_M2 accumulates the first data according to C1=1. For the read address of the second matrix, in the second calculation, since the two first data of the first matrix are both 0, the calculation unit array skips this calculation; M_temp does not change.

As shown in Figure 6e, it is the process of the third fetching and the third calculation. LD_M1 takes out the first data 0 and 2 of the third column of the first matrix, buffers them into Z_Det, Z_Det outputs the judgment result 10 to Ctrl1, and Ctrl1 performs a bitwise AND logical operation on 10 to obtain C1=0; LD_M2 according to C1=0, according to the current The read address of the second matrix reads the second data 0 and 0 in the third row of the second matrix, and buffers them into DB. If DB judges that the second data is all 0, the calculation control signal C_Start=0 is generated. Therefore, The calculation cell array skips this calculation; M_temp remains unchanged.

According to the size parameters of the first matrix, such as the number of rows and columns of the matrix, it can be determined that the matrix calculation is completed, thereby obtaining the final third matrix M.

According to the above matrix calculation circuit, it can be judged whether multiple first data in the first matrix are all 0 before calculation, and if all are 0, this calculation can be skipped to save calculation resources; when the first data in the first matrix are all 0s When the plurality of first data are not all 0, it is further judged whether the plurality of extracted second data are all 0, and if all are 0, no calculation is performed, so as to save computing resources. The calculation circuit performs the matrix calculation only when the plurality of first data are not all 0 and the plurality of second data are not all 0. In the case where the first matrix and/or the second matrix are sparse, it can save a lot of money computing resources.

FIG. 7 is a flowchart of a matrix calculation method provided by an embodiment of the present disclosure. As shown in Figure 7, the method includes the following steps:

Step S701, reading a plurality of first data in the first matrix according to the read address of the first matrix;

Step S702, generating a second data read control signal according to the plurality of first data;

Step S703, reading a plurality of second data in the second matrix according to the second data read control signal and the read address of the second matrix;

Step S704, calculating and obtaining third data according to the plurality of first data and the plurality of second data.

Further, the described generation of the second data read control signal according to the plurality of first data includes:

The second data read control signal is generated according to whether each of the plurality of data is zero.

Further, generating the second data read control signal according to whether each of the plurality of data is zero, specifically includes:

in response to the value of each of the plurality of first data being zero, generating the second data read control signal indicating the accumulation of the read address of the second matrix; or,

In response to the value of at least one of the plurality of first data being non-zero, generating a signal instructing the second data read circuit to read the plurality of second data according to the read address of the second matrix the second data read control signal.

Further, the generating a second data read control signal according to the plurality of first data includes:

judging whether the value of each data in the plurality of first data is zero;

The second data read control signal is generated according to the judgment result.

Further, the matrix calculation method also includes:

judging whether the value of each of the plurality of second data is zero;

A calculation control signal is generated according to the judgment result.

Further, generating the calculation control signal according to the judgment result includes:

In response to at least one of the plurality of second data being non-zero, a calculation control signal is generated to instruct the calculation circuit to perform a calculation operation.

Further, the matrix calculation method also includes:

generating a first control signal according to the judgment result;

The read addresses of the first matrix are accumulated to obtain a new read address of the first matrix.

In the above, although the steps in the above method embodiments are described in the above order, it should be clear to those skilled in the art that the steps in the embodiments of the present disclosure are not necessarily executed in the above order, and may also be performed in reverse order, parallel, interleaved and other steps are performed in other order, and, on the basis of the above steps, those skilled in the art can also add other steps, these obvious modifications or equivalent replacement modes should also be included within the protection scope of the present disclosure, and will not be repeated here. .

An embodiment of the present disclosure further provides a chip, where the chip includes at least any one of the matrix computing circuits in the foregoing embodiments.

An embodiment of the present disclosure provides an electronic device, including: a memory for storing computer-readable instructions; and one or more processors for executing the computer-readable instructions, so that the processor implements the embodiment when running Any of the matrix calculation methods described in .

Embodiments of the present disclosure also provide a non-transitory computer-readable storage medium, characterized in that the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to cause a computer to execute any one of the foregoing embodiments. The matrix calculation method described above.

Embodiments of the present disclosure also provide a computer program product, which is characterized by comprising computer instructions, and when the computer instructions are executed by a computing device, the computing device can execute the matrix in any one of the foregoing embodiments. calculation method.

An embodiment of the present disclosure further provides a computing device, which is characterized in that it includes the chip described in any one of the embodiments.

The flowchart and block diagrams in the figures of the present disclosure illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, task segment, or portion of code that contains one or more logical functions for implementing the specified functions executable instructions. It should also be noted that, in some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It is also noted that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented in dedicated hardware-based systems that perform the specified functions or operations , or can be implemented in a combination of dedicated hardware and computer instructions.

The units involved in the embodiments of the present disclosure may be implemented in a software manner, and may also be implemented in a hardware manner. Among them, the name of the unit does not constitute a limitation of the unit itself under certain circumstances.

The functions described herein above may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), Systems on Chips (SOCs), Complex Programmable Logical Devices (CPLDs) and more.

In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in connection with the instruction execution system, apparatus or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media may include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media would include one or more wire-based electrical connections, portable computer disks, hard disks, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), fiber optics, compact disk read only memory (CD-ROM), optical storage, magnetic storage, or any suitable combination of the foregoing.

Claims (10)

1. a matrix computing circuit, is characterized in that, comprises: a first data reading circuit, configured to read a plurality of first data in the first matrix according to a read address of the first matrix; generate a second data read control signal according to the plurality of first data; a second data read circuit, configured to read a plurality of second data in the second matrix according to the second data read control signal and the read address of the second matrix; A calculation circuit, configured to calculate and obtain third data according to the plurality of first data and the plurality of second data. 2. The matrix calculation circuit of claim 1, wherein the first data read circuit is configured to generate a second data read control signal according to the plurality of first data, comprising: The first data read circuit is configured to generate the second data read control signal according to whether each data of the plurality of data is zero. 3. The matrix calculation circuit according to claim 2, wherein the second data read control signal is generated according to whether each data of the plurality of data is zero, specifically comprising: in response to the value of each of the plurality of first data being zero, generating the second data read control signal indicating to accumulate the read address of the second matrix; or, In response to the value of at least one of the plurality of first data being non-zero, generating a signal instructing the second data read circuit to read the plurality of second data according to the read address of the second matrix the second data read control signal. 4. The matrix computing circuit according to claim 1, wherein the first data reading circuit comprises: a first value comparison circuit, configured to determine whether the value of each of the plurality of first data is zero; The first control circuit is configured to generate the second data read control signal according to the judgment result of the first numerical comparison circuit. 5. The matrix calculation circuit according to any one of claims 1-4, wherein the second data reading circuit further comprises: a second value comparison circuit, configured to determine whether the value of each of the plurality of second data is zero; The second control circuit is configured to generate a calculation control signal according to the judgment result of the second numerical value comparison circuit. 6. The matrix calculation circuit according to claim 5, wherein the second control circuit is used for: The calculation control signal is generated to instruct the calculation circuit to perform a calculation operation in response to at least one of the plurality of second data being non-zero. 7. The matrix calculation circuit according to any one of claims 4-6, wherein the first control circuit comprises: a first control signal generating circuit, configured to generate a first control signal according to the judgment result of the first numerical comparison circuit; The first read address generation circuit is configured to accumulate the read addresses of the first matrix to obtain a new read address of the first matrix. 8. The matrix computing circuit according to any one of claims 1-7, wherein: The plurality of first data is a column of first data in the first matrix; The plurality of second data are one row of second data in the second matrix. 9. The matrix calculation circuit according to claim 1, wherein the calculation circuit comprises: a computing unit array, wherein the computing unit array includes a plurality of computing units; Each row of computing units in the computing unit array respectively receives the plurality of first data; Each column of computing units in the computing unit array respectively receives the plurality of second data. 10. A matrix calculation method, characterized in that, comprising: Read a plurality of first data in the first matrix according to the read address of the first matrix; generating a second data read control signal according to the plurality of first data; Read a plurality of second data in the second matrix according to the second data read control signal and the read address of the second matrix; The third data is calculated and obtained according to the plurality of first data and the plurality of second data.

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