CN114077424A

CN114077424A - Method and apparatus for extending MIPS instruction set processor to support RISC instruction set multimode system

Info

Publication number: CN114077424A
Application number: CN202011581906.9A
Authority: CN
Inventors: 王炳立; 何薇龄
Original assignee: Shanghai Xinlianxin Intelligent Technology Co ltd
Current assignee: Shanghai Xinlianxin Intelligent Technology Co ltd
Priority date: 2020-08-14
Filing date: 2020-12-28
Publication date: 2022-02-22
Also published as: CN113703770A

Abstract

The invention discloses a method and a device for supporting a RISC instruction set multimode system by an extended MIPS instruction set processor. The invention enhances the function of the MIPS instruction set processor as a Host (Host) processor so as to efficiently support a Guest (Guest) instruction system processor instruction system. Specifically, the method comprises the following steps: by translating and converting the parts of the guest processor similar to those in the instruction set of the host processor, and simultaneously, supporting the parts of the guest processor which are different from those in the instruction set of the host processor by instruction extension on the host processor. The host processor is enabled to complete and efficiently support the guest processor. Thus, the host processor is enabled to perfectly support the software ecosystem of the guest processor.

Description

Method and apparatus for extending MIPS instruction set processor to support RISC instruction set multimode system

[ technical field ] A method for producing a semiconductor device

The invention relates to a method and a device for supporting a RISC instruction set multimode system by an extended MIPS instruction set processor.

[ background of the invention ]

MIPS architecture processors have emerged in the 1980 s as MIPS architecture, and so far there has been a recent technology accumulation of forty years, which is very mature and has been widely used for nearly a hundred chip products. To date, there have been over a billion shipments. In recent years, many emerging RISC-based instruction set systems have been developed vigorously, and the ecology of the current instruction set has presented a variety of different instruction-developing situations. Then, the success of an instruction set system depends on various factors, and besides the efficient design of the CPU based on the instruction set system, the ecological development is a very critical ring, and the ecological development needs to invest a great deal of openers such as CPU manufacturers and third parties to continuously invest a great deal of time and resources to enrich the ecology and application of the instruction set.

In this context, therefore, we have developed and designed a multi-mode system that supports multiple RISC instruction set architectures above the MIPS instruction architecture. The system can support the instruction system of RISC on the processor of MIPS. While maintaining extremely high support efficiency in the whole process and simultaneously having very low conversion complexity of a translation system.

[ summary of the invention ]

MIPS is a RISC processor that is popular worldwide. MIPS means "microprocessors without internal interlocked pipeline stages" (microprocessors with interlocked pipeline stages), and its mechanism is to avoid data-related problems in the pipeline by using a software method as much as possible. It was first developed by the research group led by professor Hennessy of Stanford university in the early 80 s, and it is a RISC architecture that is simple, convenient to optimize, and highly scalable, and is also the most efficient in the industry, and can provide the highest performance per square millimeter and the lowest power consumption in current SoC design. The R series of MIPS company is the microprocessor of RISC industrial products developed on the basis of the R series. These families of products are adopted by many computer companies to form various workstations and computer systems.

The MIPS32 architecture is based on a fixed-length set of regularly coded instructions and employs a load/store (load/store) data model. Improved, this architecture can support optimized execution of high-level languages. The MIPS32 architecture is a high-performance industry standard architecture, the heart of billions of electronic products ranging from micro-microcontrollers to high-end network devices. The MIPS32 architecture incorporates important functions including SIMD (single instruction multiple data) and virtualization. These techniques, combined with Multithreading (MT), DSP extensions and EVA (enhanced virtual addressing) technologies, enrich the architecture and can be used with modern software workloads that require more memory, more computing power and a secure execution environment. The MIPS architecture perfectly supports optimized execution of high-level languages. Its arithmetic and logical operations take the form of three operands, allowing the compiler to optimize complex expressions. In addition, it has 32 general registers, which makes the compiler further optimize the generation performance of the code by keeping frequent access to the data in the register. Privileged mode exception handling and memory management functions. It employs a set of registers to reflect the configuration of registers, MMUs, TLBs, and other privileged functions implemented in the various cores. By standardizing privilege modes and memory management and providing information via configuration registers, the MIPS32 architecture enables real-time operating systems, other development tools, and application code to be executed simultaneously and multiplexed between various products of the MIPS32 and MIPS64 processor families.

MIPS, as a classical RISC CPU, covers a differentiated design from a low-end MCU to a server-level processor in a macro ISA design. The advantages of RISC reduced instructions in power consumption performance increase additional area and power consumption compared to CISC redundant instructions, while increasing instruction decoding complexity.

MIPS authorizes CPU IPs, which are specifically optimized in the design of micro-architecture, and are therefore more suitable for use in network processing-related fields. Such as the I-Class of MIPS, supports the MTK processor IP. Many of the high-end network switches adopting the MIPS IP in the market adopt a multi-core mode, dozens of CPU IPs or even hundreds of MIPS are integrated in the SoC, and the CPUs fully utilize the advantages of light weight and support of multithreading of the MIPS IPs to enable corresponding threads to wait for the data of a packet to arrive and immediately process the data without context switching, so that extremely high throughput rate is obtained. At the same time, it is still possible to ensure that the chip power consumption and area are within the allowable range. Thus, MIPS is deeply accumulated in the field of network processors, can perform slightly differently with the product's features, but still presents its great advantages in the network processor context.

RISC has also gained explosive growth in recent years. RISC-V is an open Instruction Set Architecture (ISA) built based on the principles of Reduced Instruction Set Computing (RISC). In contrast to most ISAs, RISC-V ISAs can be used freely in all desired devices, allowing anyone to design, manufacture and sell RISC-V chips and software. FIG. 1 shows a prior generation RISC processor prototype chip. She is a completely open source, and the RISC-V fund will not charge a high authorization fee for instruction set usage. The open source adopts a loose BSD protocol, enterprises can use the BSD protocol freely and completely, and meanwhile, the enterprises are allowed to add own instruction sets for expansion without open sharing to realize differential development. The structure is simple, and the RISC-V structure has simple design philosophy.

The RISC-V basic instruction set has only 40 instructions, plus other modular extension instructions for a total of tens of instructions. The method is easy to transplant, a modern operating system separates a privilege level instruction from a user level instruction, the privilege instruction can be only called by the operating system, and the user level instruction can be called in a user mode, so that the stability of the operating system is guaranteed. RISC-V provides privileged level instruction and user level instruction, and also provides detailed information of RISC-V privileged level instruction specification and RISC-V user level instruction specification, so that developers can very conveniently transplant linux and unix systems to RISC-V platforms. The RISC-V architecture is not only short and elegant, but also its different parts can be organized in a modular way, trying to meet various application scenarios with a set of unified architectures. A user can flexibly select different module combinations to meet the requirements of self-customized equipment, for example, aiming at a small-area low-power-consumption embedded scene, the user can select an instruction set combined by RV32IC and only use a Machine Mode; the high performance os scenario may select an instruction set such as RV32IMFDC, using Machine Mode and User Mode.

Therefore, if a certain microprocessor design can be compatible with two or more instruction sets with different modes, the ecology of two instruction systems can be utilized, and the applicable scenes of the product can be greatly improved.

A Host (Host) processor system using an MIPS instruction set is designed to be compatible with a dual-mode or multi-mode scheme of a plurality of different instruction set systems, and under the scheme, the Host system running the MIPS instructions can efficiently run programs of other non-MIPS instruction set ecosystems such as RISC-V. This support of multiple instruction system types may be from the source code level or the two-mechanism level for non-native instruction system support. In the scheme, other non-RISC instruction sets are directly converted on the level of a source code, and the converted code can be efficiently and efficiently operated on a host machine by ensuring.

Support for guest processor instruction system specification

In order to efficiently support a variety of different instruction systems, it is therefore necessary to modify and support the design of the host CPU at both the software level and the hardware microarchitectural design level, as shown in fig. 1. Efficient support for guest instruction systems can be ensured.

In terms of hardware level, because different instruction systems have different instruction set specifications, different processor state registers, different privileged instruction architectures, different processor peripherals, and the like in design, it is necessary to make reasonable changes in the hardware level according to performance requirements in order to support the different instruction systems.

At the software level, from the perspective of an application program and an operating system, a compiler and a linker need to modify software-related functional modules so that they can support different instruction systems.

In the aspect of hardware, modification needs to be performed on the aspect of an instruction set, a state register and a peripheral part of an original architecture, and a new instruction system can be supported efficiently. Inefficient emulation of new instruction set functionality due to the use of a large host instruction set is avoided.

First, from the instruction system perspective, as shown in fig. 2, the instruction system of the Guest (Guest) processor can be generally divided into two major parts, where part a is a part of the instruction system of the Guest (Guest) processor and the Host (Host) processor, where the difference between the parts is small, and the instruction of the Guest processor is similar in function to the instruction system of the Host processor. However, some guest instructions have a large difference from the host instruction system in terms of function, and therefore need to be implemented in hardware or simulated in software using multiple instructions.

The whole planning and design implementation process is shown in fig. 4. When the host processor source program conversion planning is carried out, the system is required to analyze an instruction set of an instruction system to be converted and mapped, and a simple mapping method is selected according to the condition of the instruction, or a method supported by a hardware instruction is adopted, or a mode of simulating a plurality of instructions is adopted. The whole process needs to be planned in detail, instructions with high occurrence frequency or important performance requirements need to be supported in a hardware support mode to improve the conversion performance, but for special instructions with low occurrence frequency, related instructions can be adopted to perform sequence simulation. The analytical procedure was as follows:

if the instructions can be mapped or converted directly, then the simulation can be done directly, possibly via a single mutual aid or a small number of instructions. These mappings or hardware implementations can be done efficiently. These instructions are typically arithmetic or substantive arithmetic operation instructions.

When some instructions are not implemented in the instruction data of the host processor, the instructions need to be implemented by instruction hardware or by a method of simulating by using a plurality of instruction sequences.

A simple example is:

the LUI for loading the immediate number exists in instruction systems of MIPS and RISC-V, but the behaviors of the LUI are slightly different, and the instructions can be easily translated and converted to realize functions efficiently.

Some guest processor instructions may require two or more instruction host processors to complete, rather than being limited to a single instruction.

The part B is a part with larger difference between the guest processor and the Host processor, the instruction of the guest processor has obvious difference similar to the instruction system of the Host processor in function and cannot be realized through simple mapping, and the performance is seriously reduced by using a plurality of instructions for simulation. These instructions require instruction systems that are efficiently supported by the host processor by performing instruction extensions on the host processor that the guest processor does not implement on the host.

Thus, the instruction system support of the new host system's CPU instruction system becomes, as shown in FIG. 3, to support the original instruction set while also supporting the instruction system of part B of the guest processor system by extending the instructions. The host processor can still support the original instruction set specification, and support of the original instruction system is ensured. And the support of the guest CPU system is expanded through instruction expansion.

After the modification of the host processing system is completed, the corresponding compiler or the supporting operating system or the third-party library can support the host processing system efficiently.

In particular, software-related support works,

after the support of the hardware is completed, the enhanced host system can perfectly support the instruction and state control registers of the host system and the guest system and the peripheral module of the processor.

In order to fully utilize the hardware function, the system needs to be supported at the software level so as to maximize the functions and capabilities of the two instruction systems. In particular, it will relate to: application development, operating systems, third party libraries, and the like.

The assembled or quasi-assembled code of the guest processor system is translated into binary code of the host system through mapping and conversion, and can be efficiently run on the host processor.

The code of the high-level language can be compiled into the high-efficiency binary code of the host instruction system by fully utilizing the advantages of the instruction system of the host system through the compiling of the host system. Furthermore, the code of the high-level language can effectively use the advantages of the two types of instruction systems, and the advantages of the two types of instruction systems are fully utilized to compile higher-performance capability capable of compatibly measuring the advantages of the two types of instruction systems.

The assembled or quasi-assembled code of the host system can be efficiently run on the above by being mapped and translated into binary code of the host system.

Similarly, the third-party library and the operating system can compile the operating system and the third-party library which can fully utilize two different instruction systems by the method.

As shown in fig. 6, the final software system can efficiently compile high-level language source code, host assembly language source code, and system-guest assembly language source code. The advantages of the two instruction systems are fully exerted by enhancing the support of the compiler and the assembler to the host system and the guest system.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise. Wherein:

FIG. 1 shows a prior generation RISC processor prototype chip.

FIG. 2 is a schematic diagram of a Guest (Guest) processor instruction system;

FIG. 3 is an architecture diagram of a Guest (Guest) processor instruction system and a host processor instruction system;

FIG. 4 is a diagram of the overall planning and design implementation;

FIG. 5 illustrates an extension method of coprocessor interface CorExtend;

FIG. 6 shows an instruction slot extension using Special 2;

FIG. 7 shows an expansion method using a user expansion instruction (COP2) interface;

figure 8 shows a modification of the software level.

[ detailed description ] embodiments

The following detailed description of the invention refers to the accompanying drawings.

In the present invention, the terms "in one embodiment" and "in an embodiment" do not specifically mean that they are in the same embodiment, and may be in different embodiments.

Examples of the present invention are described below by way of examples only, which are presently representative of the best modes of carrying out the invention that are presently known to the applicant, although they are not the only modes in which the present invention may be practiced. The description sets forth the functions of the examples and the sequence of steps for constructing and operating the examples, however, different examples may carry out the same or equivalent sequences of functions.

The present invention is described by enhancing the hardware design of the MIPS processor and enhancing the software system, taking the RISC-V processor instruction set as an example. To efficiently support a variety of different instruction systems, modifications are made at the hardware microarchitectural design level to efficiently support the new instruction system. To support the above modifications, enhancements at the software compiler and operating system level are needed. That is, the way software and hardware cooperate to efficiently support the new instruction system.

Support for guest processor instruction system specification from hardware perspective

First, from the instruction system perspective, the Guest (Guest) processor instruction system can be generally divided into two major parts, wherein the part a is the part of the Guest (Guest) processor with smaller difference from the part of the Host (Host) processor instruction system, the instruction of the Guest processor is similar to the instruction system of the Host processor in function, the part of the instruction system can use simple mapping relationship, so that the Host system can support the function of the Guest processor, and the function can be supported efficiently without or with little modification.

The mapping can be simply implemented for the part of the guest processor consistent with or similar to the instruction of the host processor. That is, a simple mapping table may be created for the converter to analyze.

To name a few examples:

JAL instruction, JAL instruction of guest register is JAL rd, Offset, but its Offset is 20 bits, and Offset of instruction of host JAL is 26 bits.

Thus, the guest JAL instruction may be directly mapped to the host processor's JAL instruction.

JALR can specify rd register, but its rd is r31, the convention of guest processor specification is r1 as return address register, there is no actual big difference between them.

Therefore, the JAL instruction can be efficiently mapped, and the fast mapping from the guest processor to the host processor can be realized

LUI load immediate instructions exist in both MIPS and RISC-V instruction systems, but their behavior is slightly different, and such instructions can be easily translated and translated to efficiently implement functions. The specific mapping method comprises the following steps: the LUI instruction of the guest processor is LUI rd, immedate

The functions are as follows: the 20-bit immediate of the sign bit extension is shifted left by 12 bits and the lower 12 bits are cleared. Written into x < rd >.

And the definition of the host processor is as follows:

the functions are as follows: the immediate is shifted left by 16 bits and the lower 16 bits are cleared. And writing into GPR [ rt ].

Therefore, two instructions have slight difference and cannot completely and directly correspond to each other, and when mapping is performed, mapping is performed according to the following conditions:

an immediate may be mapped directly to an instruction when the absolute value of the immediate is less than 65535, but when the absolute value of the immediate is about 65535. This needs to be done by mapping into two instructions.

An LW word load instruction, an LW instruction of the host processor, using a 12-bit immediate as an offset address. And the LW instruction of the host processor uses the immediate of 16 bits as the offset address. And the addressing of both is similar. So these two instructions can be mapped for use. Similar instructions are LD, LH, LBU, LHU, SB, SH, SW, LD, SD

Instructions of the BEQ, BNE class,

the function of the guest processor instruction is substantially identical to that of the host processor instruction, and the bit length of the offset of the guest processor is 12 bits and the bit length of the host processor is 16 bits, so that the guest processor instruction can be directly replaced with the host processor.

5.ADDI,SLTI,SLTIU,ORI,ANDI

The immediate of the guest processor in ADDI is 12 bits and the immediate of the host processor is 16 bits, so it can be directly replaced.

The SLTI has a guest processor immediate 12 bits and a host processor immediate 16 bits, and therefore can be directly replaced.

The immediate value of the guest processor in the ORI is 12 bits, while the immediate value of the host processor is 16 bits, so that direct replacement is possible.

The ANDI is one in which the guest processor has 12 bits of immediate data and the host processor has 16 bits of immediate data, and therefore can be directly replaced.

Such instructions that behave identically may be directly replaced.

6.OR,ADD,SUB,SLL,SLT,SLTU,XOR,SRL,SRA,AND,

The above instructions are completely consistent in behavior between the guest processor and the host processor and thus can be directly replaced.

7.ADDW,SUBW,SRLW,SRAW

The instruction behavior of the guest processor in the ADDW is the same as the DADD of the host processor and thus can be directly replaced. The instruction behavior of the guest processor in the SUBW is related to the DSUB of the host processor and thus can be directly replaced. The instruction behavior of the guest processor in SRLW is in direct contact with the DSRL of the host processor and thus can be replaced. The instruction behavior of the guest processor in the SRAW is in direct contact with the DSRA of the host processor and thus can be directly replaced.

8.ECALL

In guest processors, an ecall is used to enable a context call exception. In the host processor, Syscall is very similar to this function.

Instructions such as EBREAK, etc.,

in a guest processor, a debugger is requested in a manner that uses ebreak to trigger a breakpoint exception. Within the host processor, sddbp is very similar to this function.

The above instructions can be supported efficiently in the host. Therefore, efficient mapping can be performed through a simple mapping table, and the mapped instructions can be efficiently executed.

However, some guest processor instructions may require two or more instruction host processors to complete rather than a single or two instruction, which may result in performance-impacting instructions that, if emulated with multiple instructions, may result in a significant performance degradation that may require support and enhancement at the host processor in order to efficiently increase the support for such instructions. I.e., portion B of the figure, where the guest processor differs significantly from the host processor. These instructions require instruction systems that are efficiently supported by the host processor by performing instruction extensions on the host processor that the guest processor does not implement on the host.

Such as: the command function needs to be expanded by VFNMADD and the like.

Since hardware enhancement requires a large amount of hardware resources, for the part B, which is a part with a large difference between the guest processor and the Host (Host) processor, although the part B cannot be implemented by simple mapping, and simulation using multiple instructions may cause a serious performance reduction, since the calling frequency is low, the performance of such instructions on the whole is relatively small. These instructions may also be implemented by a combined mapping of instructions.

In this way, the instruction system support of the new host CPU instruction system is changed to support the instruction system of the part B of the guest processor system by extending the instruction while supporting the original instruction set. The host processor can still support the original instruction set specification, and support of the original instruction system is ensured. The support to the guest CPU system is expanded through instruction expansion, and the instruction with low calling frequency in the guest processor is still realized through conversion and mapping.

Adding instructions to the CPU requires coordination between software and hardware, while adding instructions to the processor will have an impact on the original instruction system. Therefore, different methods are adopted for supporting different performance influences of certain missing instructions. The method is implemented by hardware enhancement for instructions which are important for a guest system and have higher calling frequency. When the frequency of instruction calling is low, a mode of combining a plurality of instructions can be adopted to complete the simulation of the function of the new instruction.

When the key instruction of the guest register needs hardware simulation, the hardware support of the instruction is needed at the moment. In the instruction encoding of the host processor, relevant encoding bits for extending the user instruction have been reserved, and these encoding bits are used for the user-defined instruction.

When adding hardware instruction support to a MIPS processor system, one possible approach is to use the approaches of CorExtend and coprocessors for instruction expansion. Or directly modifying the internal design of the processor for supporting new instructions.

As shown in fig. 5, an extended method of coprocessor interface CorExtend is shown. When extension is performed using the instruction of CorExtend, as shown in fig. 6, extension is performed using an instruction slot of Special 2. That is, when the upper 6 bits of the instruction word are 011100, the instruction is of the instruction class Special 2. When the instruction word is encountered by the instruction decoder, the hardware of the processor controls the hardware of the user-defined instruction to execute the instruction through the CorExtend interface.

As shown in fig. 7, an extension method using a user extension instruction (COP2) interface is shown. As shown in fig. 7, the instruction slot of COP2 is used for expansion. That is, when the upper 6 bits of the instruction word are 010010, the instruction is of the instruction class of COP 2.

When the missing instructions are enhanced by adding user-defined mode, the host processor possesses the hardware capability of directly supporting the instruction system of the guest processor. Under the effective cooperation of software, the system can efficiently support various instruction sets.

Support of software layer

As the hardware aspect needs to be enhanced on the aspect of the instruction set of the original architecture, a new instruction system can be efficiently supported. Inefficient emulation of new instruction set functionality due to the use of a large host instruction set is avoided.

At the software level, from the perspective of an application program and an operating system, a compiler and a linker need to modify software-related functional modules so that they can support different instruction systems. Therefore, the enhanced host system can perfectly support the instruction and state control registers of the host system and the guest system and the peripheral module of the processor, wherein the method comprises the following steps: application development, operating systems, third party libraries, and the like.

As shown in fig. 8, the modification of the software layer includes the following layers:

the high-level language code can be compiled into the high-efficiency binary code of the host instruction system by fully utilizing the advantages of the instruction system of the host system through the compiling of the host system. Furthermore, the code of the high-level language can effectively use the advantages of the two types of instruction systems, and can compile higher-performance capability compatible with the advantages of the two types of instruction systems by fully utilizing the advantages of the two types of instruction systems.

The assembled or quasi-assembled code of the host processor system is compiled into binary code of the host system, and can run efficiently on the host system.

The assembly or quasi-assembly code of the guest processor system is translated into binary code of the host system through mapping and conversion, and then compiled, so that the guest processor system can run on the host system efficiently. This translation and mapping requires the creation of a look-up table of guest processor system instructions and host system processor systems. According to the table, the instruction of the guest processing system is mapped to the instruction of the host system, and the mapping process can be carried out through a direct macro file or through a program.

Common compilation systems like GCC toolchains or LLVM toolchains can accomplish a similar mapping from high level languages to underlying languages. In order to be able to fully utilize multiple instruction systems, the toolchain of GCC and LLVM needs to be enhanced to be able to support multiple instruction systems.

The final software system can efficiently compile high-level language source codes, host assembly language source codes and system-guest assembly language source codes. The advantages of the two instruction systems are fully exerted by enhancing the support of the compiler and the assembler to the host system and the guest system.

The methods and steps described herein may be performed in any suitable order or simultaneously where appropriate, and individual modules may be deleted from any of the methods without departing from the spirit and scope of the subject matter described herein. The precautions of any of the examples described above may be combined with the solutions of any of the other examples described to form further examples, without the effect of seeking protection being marketed. In the case where the modules in the figures are considered to be connected by arrows, it will be clear that: these arrows illustrate only an exemplary flow of communications (including data and control information) between the elements. .

It should be understood that: the above description of the preferred embodiment is given by way of example only and various modifications may be made by those skilled in the art. Although various examples have been described with a certain degree of particularity, or with reference to one or more individual embodiments, those skilled in the art could make numerous alterations to the disclosed examples without departing from the spirit or scope of this invention.

The foregoing description has disclosed fully preferred embodiments of the present invention. It should be noted that those skilled in the art can make modifications to the embodiments of the present invention without departing from the scope of the appended claims. Accordingly, the scope of the appended claims is not to be limited to the specific embodiments described above.

Claims

1. A method and apparatus for extending a MIPS instruction set processor to support a RISC instruction set multimode system, said method comprising: the instruction with similar functions of the Guest instruction and the host instruction set is directly realized by a mapping method, and the instruction with larger function difference between the Guest instruction and the host instruction set is used for carrying out function enhancement or carrying out multi-instruction mapping on the host system instruction set processor so as to comprehensively and simultaneously support a single Guest (Guest) or two or more Guest instruction system processor instruction systems.

2. The method and apparatus of claim 1 for an extended MIPS instruction set processor to support RISC instruction set multimode systems by translating and translating similar parts of the guest processor to those of the host processor instruction set.

3. The method and apparatus of claim 1 for extending the MIPS instruction set processor support for RISC instruction set multimode systems by supporting the portion of the guest processor that differs significantly from the host processor instruction set on the host processor through instruction hardware extensions.

4. The method and apparatus of claim 1 for extending the MIPS instruction set processor to support RISC instruction set multimode systems, which can be implemented on the host processor by combining instructions from the parts of the guest processor that differ significantly from the instruction set of the host processor.

5. The method and apparatus of claim 3 for extending the MIPS instruction set processor support for RISC instruction set multimode systems by supporting the portion of the guest processor that differs significantly from the host processor instruction set on the host processor by using CorExtend or Coprocessor interface extensions.

6. The method and apparatus of claim 1 for extending the MIPS instruction set processor to support RISC instruction set multimode systems, whereby the assembly or quasi-assembly code of the guest processor system is translated into binary code of the host system by mapping and translation, then compiled, and then efficiently run on the host system.

7. The method and apparatus of claim 5 in which the conversion and mapping requires the creation of a table of guest system instructions and host system processor systems, whereby the guest system instructions are mapped to host system instructions, and the mapping can be done either by direct macro-file or by program.