CN114070340A

CN114070340A - Offset calibration circuit and analog front-end equipment

Info

Publication number: CN114070340A
Application number: CN202111342526.4A
Authority: CN
Inventors: 李东明; 白东勋; 花正贝; 范昊; 南帐镇
Original assignee: Beijing Eswin Computing Technology Co Ltd; Hefei Eswin IC Technology Co Ltd
Current assignee: Hefei Yisiwei Computing Technology Co ltd; Beijing Eswin Computing Technology Co Ltd
Priority date: 2021-11-12
Filing date: 2021-11-12
Publication date: 2022-02-18
Anticipated expiration: 2041-11-12
Also published as: CN114070340B

Abstract

The present disclosure provides an offset calibration circuit and an analog front-end device. The offset calibration circuit includes: an offset polarity acquisition unit configured to receive a signal for offset calibration operation, perform a majority voting operation based on a plurality of sample values of the signal to acquire a polarity of the signal; an offset calibration logic unit configured to transmit an offset calibration code corresponding to the polarity from the polarity of the signal received by the offset polarity acquisition unit; and a digitally controlled current source configured to receive the offset calibration code from the offset calibration logic unit and output a compensation signal for the compensation signal according to the offset calibration code. The offset calibration circuit can improve the sensitivity of analog front-end equipment and improve the accuracy of offset calibration.

Description

Offset calibration circuit and analog front-end equipment

Technical Field

Embodiments of the present disclosure relate to offset calibration circuits and analog front-end devices.

Background

In the receiver, Analog Front-end Equipment (AFE) amplifies small signals from a signal path to large signals, which are passed to Clock Data Recovery (CDR) circuits. But as the length of the signal path increases and the data rate increases, the amplitude of the input signal to the analog front-end device is continually decreasing. This results in the slew rate of the input signal to the analog front-end device also becoming slower and slower, which also degrades the signal's immunity to noise. Furthermore, low power consumption and high performance of emi protection are the current trend of receivers, and these requirements will also reduce the amplitude of the transmitter (Tx) output signal. Therefore, it is imperative to provide the sensitivity of the analog front-end equipment of the receiver.

Furthermore, mismatch of the electronic devices may also cause detuning of the analog front-end device and thus reduce the input sensitivity of the analog front-end device. The current misalignment calibration method can be used to compensate for the mismatch of electronic devices and improve the yield. In a receiver (Rx), a conventional offset calibration method is usually that after an analog front end device is powered on, the receiver enters an offset calibration operation mode, and the offset calibration is completed in the offset calibration operation mode. And after the offset calibration is completed, the clock data recovery circuit of the receiver enters a clock training working mode. However, if the working environment of the analog front-end device changes after the offset calibration is completed, the accuracy of the already completed offset calibration is reduced, and all subsequent operations are affected.

Disclosure of Invention

At least one embodiment of the present disclosure provides an offset calibration circuit, an analog front-end device, an offset calibration method, and an apparatus for performing the offset calibration method for the analog front-end device, thereby achieving an improvement in sensitivity of the analog front-end device and coping with a change in a working environment of the analog front-end device.

At least one embodiment of the present disclosure provides an offset calibration circuit, including: an offset polarity acquisition unit configured to receive a signal for offset calibration operation, perform a majority voting operation based on a plurality of sample values of the signal to acquire a polarity of the signal; an offset calibration logic unit configured to transmit an offset calibration code corresponding to the polarity from the polarity of the signal received by the offset polarity acquisition unit; and a digitally controlled current source configured to receive the offset calibration code from the offset calibration logic unit and output a compensation signal for the compensation signal according to the offset calibration code.

For example, in the offset calibration circuit provided in an embodiment of the present disclosure, the offset calibration logic unit is further configured to output first information indicating entering the offset calibration mode in response to receiving the polarity, and output second information indicating leaving the offset calibration mode in response to the polarity being changed.

For example, in the offset calibration circuit provided in an embodiment of the present disclosure, the offset polarity obtaining unit is further configured to perform a majority voting operation once every preset time interval, or continuously perform a majority voting operation on a plurality of sampling values that are received most recently and are fixed in number.

For example, in the offset calibration circuit provided in an embodiment of the present disclosure, the offset calibration logic unit is further configured to continuously output the offset calibration code to the digitally controlled current source before the polarity is changed.

For example, in the offset calibration circuit provided in an embodiment of the present disclosure, the offset calibration logic unit is further configured to output the offset calibration code once every preset time interval, or output the offset calibration code once in response to receiving the polarity sent by the offset polarity acquisition unit each time; wherein, the value of the offset calibration code output at each time is increased or decreased compared with the value of the offset calibration code output at the last time.

For example, in the offset calibration circuit provided in an embodiment of the present disclosure, the polarities include positive and negative, and in response to the polarities being positive, the offset calibration code output at each time is reduced in value compared to the offset calibration code output at the last time; in response to the polarity being negative, the value of the offset calibration code output at each time is increased compared to the offset calibration code output at the last time.

At least one embodiment of the present disclosure provides an analog front end device, including: a multistage amplifier including a plurality of stages and configured to amplify an input signal received by a first stage of the plurality of stages in multiple stages and output the amplified input signal at a last stage; a clock data recovery circuit configured to receive the amplified input signal and perform frequency and clock lock training based on the amplified output signal; and the offset calibration circuit of any one of the above embodiments, coupled to the clock data recovery circuit and the multi-stage amplifier, and configured to perform an offset calibration operation in response to an offset calibration indication.

For example, in the analog front-end device provided by an embodiment of the present disclosure, further including a processor, the offset calibration indication is sent by the processor or sent by the clock data recovery circuit.

For example, in an analog front-end device provided by an embodiment of the present disclosure, a clock data recovery circuit is configured to sequentially perform frequency locking and phase locking.

For example, in the analog front-end device provided by an embodiment of the present disclosure, the offset calibration circuit is further configured to perform the offset calibration operation in response to the clock data recovery circuit completing the frequency locking training between the clock data recovery circuit performing the frequency locking training and the phase locking training.

For example, in an analog front end device provided by an embodiment of the present disclosure, the offset calibration circuit is further configured to perform an offset calibration operation in response to the clock data recovery circuit completing the phase lock training.

For example, in the analog front-end device provided by an embodiment of the present disclosure, the clock data recovery circuit is further configured to output the clock signal and the data signal recovered based on the input signal in response to the offset calibration operation being performed and the frequency locking training and the phase locking training being both completed.

For example, in an analog front-end device provided by an embodiment of the present disclosure, the clock data recovery circuit is further configured to: responding to the frequency loss lock or the phase loss lock, and sending a loss adjustment calibration instruction to a loss adjustment calibration circuit; or, in response to the configuration information of the analog front-end equipment changing, sending an offset calibration instruction to the offset calibration circuit.

For example, in the analog front-end device provided in an embodiment of the present disclosure, the analog front-end device further includes: the first switching unit is coupled with the offset calibration circuit and the multistage amplifier and is configured to control an input signal to be input or not input into the first stage based on first information or second information sent by the offset calibration circuit, wherein the first information indicates that the offset calibration mode is entered, and the second information indicates that the offset calibration mode is left; a second switching unit coupled to the offset calibration circuit and the multi-stage amplifier, configured to control or disable the common voltage input to the multi-stage amplifier based on the first information or the second information; and a voltage terminal coupled with the second switching unit and configured to provide a common voltage for offset calibration operation.

For example, in an analog front end device provided by an embodiment of the present disclosure, the second switching unit is coupled with a data input terminal of a first stage or coupled with a data input terminal of a second stage in a plurality of stages; or the first switching unit is coupled to a data input of the first stage or to a control signal input of the first stage.

For example, in the analog front-end device provided by an embodiment of the present disclosure, when the second switching unit is coupled to the data input terminal of the second stage, the offset calibration circuit is coupled to the data input terminal of the nth stage amplifier after the second stage; or when the second switching unit is coupled with the data input end of the first stage, the offset calibration circuit is coupled with the data input end of the m-th stage amplifier after the first stage, wherein n is an integer larger than 2, and m is an integer larger than 1.

For example, in the analog front-end device provided in an embodiment of the present disclosure, the first switching unit is a logic and gate or a double-pole double-throw switch, and the second switching unit is a double-pole double-throw switch.

At least one embodiment of the present disclosure provides a method of misalignment calibration, comprising: controlling a clock data recovery circuit of analog front-end equipment to perform locking training, wherein the locking training comprises phase locking training and frequency locking training; controlling the clock data recovery circuit to perform locking training again in response to the clock data recovery circuit losing the lock; wherein controlling the clock data recovery circuit to perform lock training comprises: controlling a clock data recovery circuit to perform frequency locking training; controlling an offset calibration circuit of the analog front-end equipment to execute offset calibration operation in response to frequency locking of the clock data recovery circuit; and controlling the clock data recovery circuit to perform phase locking training in response to the completion of the offset calibration operation.

For example, an embodiment of the present disclosure provides a misalignment calibration method, further including: and under the states of frequency locking and phase locking, the offset calibration circuit is controlled to execute offset calibration operation in response to the change of the configuration information of the analog front-end equipment.

For example, an embodiment of the present disclosure provides a misalignment calibration method, further including: acquiring the bit error rate and/or frequency drift of a data signal, wherein the data signal is acquired by a clock data recovery circuit based on an input signal of analog front-end equipment; and controlling the clock data recovery circuit to unlock in response to the error rate being lower than the preset error rate and/or the frequency drift exceeding the preset frequency drift range.

For example, in the offset calibration method provided in an embodiment of the present disclosure, the controlling the offset calibration circuit to perform an offset calibration operation includes: sending a signal indicating offset calibration operation to the offset calibration circuit; controlling the clock data recovery circuit to send a data signal to the offset calibration circuit so that the offset calibration circuit performs the following operations: receiving a data signal in response to receiving a signal indicating to perform a misalignment calibration operation; acquiring the polarity of a data signal; obtaining an offset calibration code corresponding to the polarity; and outputting a compensation signal for compensating the data signal according to the offset calibration code.

For example, in a misalignment calibration method provided by an embodiment of the present disclosure, controlling a clock data recovery circuit to send a data signal to a misalignment calibration circuit includes: controlling a clock data recovery circuit to sample a data signal to obtain a plurality of sampling values; controlling the clock data recovery circuit to send a plurality of sampling values to the offset calibration circuit; wherein the offset calibration circuit performs the following operations: receiving a plurality of sample values in response to receiving a signal indicating to perform an offset calibration operation; performing a majority voting operation based on the plurality of sampling values to obtain a polarity of the data signal; obtaining an offset calibration code corresponding to the polarity; and outputting a compensation signal for compensating the data signal according to the offset calibration code.

For example, in a misalignment calibration method provided by an embodiment of the present disclosure, a majority voting operation is performed based on a plurality of sampling values, including: executing majority voting operation once every preset time interval; alternatively, the majority voting operation is continuously performed on a fixed number of the most recently received sample values.

For example, in the offset calibration method provided in an embodiment of the present disclosure, acquiring an offset calibration code corresponding to a polarity includes: the offset calibration code is continuously acquired until the polarity is changed.

For example, in the misalignment calibration method provided in an embodiment of the present disclosure, the value of the misalignment calibration code obtained at each time is increased or decreased compared to the value of the misalignment calibration code output last time.

For example, in the offset calibration method provided by an embodiment of the present disclosure, the polarities include positive and negative; when the polarity is positive, the value of the offset calibration code obtained at each time is reduced compared with the value of the offset calibration code obtained at the last time; when the polarity is negative, the value of the offset calibration code obtained at each time is increased compared with the value of the offset calibration code obtained at the last time.

At least one embodiment of the present disclosure provides an apparatus for performing an offset calibration method for an analog front-end device, including: a control unit configured to: controlling a clock data recovery circuit of analog front-end equipment to perform locking training, wherein the locking training comprises phase locking training and frequency locking training; controlling the clock data recovery circuit to perform locking training again in response to the clock data recovery circuit losing the lock; wherein controlling the clock data recovery circuit to perform lock training comprises: controlling a clock data recovery circuit to perform frequency locking training; controlling an offset calibration circuit of the analog front-end equipment to execute offset calibration operation in response to frequency locking of the clock data recovery circuit; and controlling the clock data recovery circuit to perform phase locking training in response to the completion of the offset calibration operation.

For example, in an apparatus for performing an offset calibration method for an analog front-end device provided in an embodiment of the present disclosure, the control unit is further configured to: and under the states of frequency locking and phase locking, the offset calibration circuit is controlled to execute offset calibration operation in response to the change of the configuration information of the analog front-end equipment.

For example, in an apparatus for performing an offset calibration method for an analog front-end device provided in an embodiment of the present disclosure, the control unit is further configured to: acquiring the bit error rate and/or frequency drift of a data signal, wherein the data signal is acquired by a clock data recovery circuit based on an input signal of analog front-end equipment; and controlling the clock data recovery circuit to unlock in response to the error rate being lower than the preset error rate and/or the frequency drift exceeding the preset frequency drift range.

For example, in an apparatus for performing an offset calibration method for an analog front-end device provided in an embodiment of the present disclosure, controlling an offset calibration circuit to perform an offset calibration operation includes: sending a signal indicating offset calibration operation to the offset calibration circuit; controlling the clock data recovery circuit to send a data signal to the offset calibration circuit so that the offset calibration circuit performs the following operations: receiving a data signal in response to receiving a signal indicating to perform a misalignment calibration operation; acquiring the polarity of a data signal; obtaining an offset calibration code corresponding to the polarity; and outputting a compensation signal for compensating the data signal according to the offset calibration code.

For example, in an apparatus for performing an offset calibration method for an analog front-end device according to an embodiment of the present disclosure, a method for controlling a clock data recovery circuit to send a data signal to an offset calibration circuit includes: controlling a clock data recovery circuit to sample a data signal to obtain a plurality of sampling values; controlling the clock data recovery circuit to send a plurality of sampling values to the offset calibration circuit; wherein the offset calibration circuit performs the following operations: receiving a plurality of sample values in response to receiving a signal indicating to perform an offset calibration operation; performing a majority voting operation based on the plurality of sampling values to obtain a polarity of the data signal; obtaining an offset calibration code corresponding to the polarity; and outputting a compensation signal for compensating the data signal according to the offset calibration code.

For example, in an apparatus for performing a misalignment calibration method for an analog front-end device according to an embodiment of the present disclosure, a majority voting operation is performed based on a plurality of sampling values, including: executing majority voting operation once every preset time interval; alternatively, the majority voting operation is continuously performed on a fixed number of the most recently received sample values.

For example, in an apparatus for performing an offset calibration method for analog front-end devices according to an embodiment of the present disclosure, acquiring an offset calibration code corresponding to a polarity includes: the offset calibration code is continuously acquired until the polarity is changed.

For example, in an apparatus for performing a misalignment calibration method for an analog front-end device according to an embodiment of the present disclosure, a value of a misalignment calibration code obtained each time is increased or decreased compared to a value of a misalignment calibration code output last time.

For example, in an apparatus for performing an offset calibration method for an analog front-end device provided in an embodiment of the present disclosure, the polarities include positive and negative; when the polarity is positive, the value of the offset calibration code obtained at each time is reduced compared with the value of the offset calibration code obtained at the last time; when the polarity is negative, the value of the offset calibration code obtained at each time is increased compared with the value of the offset calibration code obtained at the last time.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it should be apparent that the drawings described below only relate to some embodiments of the present disclosure and are not limiting on the present disclosure.

FIG. 1A is a schematic diagram of an analog front end device;

FIG. 1B is a schematic diagram of an offset calibration circuit;

FIG. 1C is a flow chart of a method of misalignment calibration;

fig. 2 is a schematic diagram of an offset calibration circuit according to at least one embodiment of the present disclosure;

fig. 3A is a schematic diagram of an analog front end device provided in at least one embodiment of the present disclosure;

fig. 3B is a schematic diagram of another analog front-end device provided in at least one embodiment of the present disclosure;

fig. 4A is a flowchart of a method for misalignment calibration according to at least one embodiment of the present disclosure;

fig. 4B is a detailed flowchart of a misalignment calibration method provided by at least one embodiment of the present disclosure;

fig. 5 is a schematic diagram of an apparatus for performing an offset calibration method for an analog front-end device according to at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below clearly and completely with reference to the accompanying drawings. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

Fig. 1A shows a schematic diagram of an analog front end device. As shown in fig. 1A, the analog front end 100 includes an offset calibration circuit 110, a multi-stage amplifier 120, a clock data recovery circuit 130, a voltage source 140, a switch 150, and a switch 160.

The enable signal EN is input to each stage of the multi-stage amplifier 120, and the multi-stage amplifier 120 includes N stages, where N is a positive integer. Two voltage signals VIP and VIN are input to the first stage (left side in the figure) of the multi-stage amplifier 120, and the two voltage signals VIP and VIN are controlled by the double-pole double-throw switch 150 to be input or not input to the multi-stage amplifier 120. One terminal of the voltage source 140 is connected to ground and the voltage source 140 generates 2 voltage signals which are controlled by the double pole double throw switch 160 and input to the first stage of the multi-stage amplifier 120. Both switch 150 and switch 160 are normally in opposite on-off states or are off at the same time. Two output signals of the multistage amplifier 120 are supplied to the clock data recovery circuit 130, so that the clock data recovery circuit 130 outputs a clock signal CKOUT and a data signal DOUT based on the two output signals. The inputs to the offset calibration circuit 110 are also the two output signals of the multi-stage amplifier 120.

The offset calibration circuit 110 receives the two output signals of the multi-stage amplifier 120 in an offset calibration mode (also referred to as an offset calibration operation mode), generates a compensation signal and outputs the compensation signal to the second stage of the multi-stage amplifier 120, thereby completing the offset calibration. As shown, in the offset calibration mode, the offset calibration circuit 110 further generates a control signal to control the switch 150 and the switch 160. Switch 150 is controlled to open and switch 160 is controlled to close at the beginning of the offset calibration, thereby allowing voltage source 140 to serve as the input to multi-stage amplifier 120. And controls the switch 150 to be closed and the switch 160 to be opened after the offset calibration is completed, so that the external input signals VIP and VIN are normally input to the multi-stage amplifier 120.

FIG. 1B shows a schematic diagram of an offset calibration circuit. The offset calibration circuit 110 shown in fig. 1B is the offset calibration circuit in the analog front-end device shown in fig. 1A. As shown in fig. 1B, the offset calibration circuit 110 includes an error amplifier 111, an offset calibration logic unit 112, and a digital controlled current source 113. Two output signals of the multistage amplifier 120 are input to the error amplifier 111, and the error amplifier 111 determines the polarity of the two output signals and outputs the two output signals to the offset calibration logic unit 112. The offset calibration logic unit 112 controls the digitally controlled current source 113 to output two voltage signals for compensation according to the polarity, and the offset calibration logic unit 112 outputs a control signal to control the switch 150 and the switch 160 in fig. 1A.

Fig. 1C shows a flow chart of a method for performing offset calibration by an analog front-end device. As shown in fig. 1C, the misalignment calibration method includes the following steps:

step S101, power up or reset.

Step S102, entering a detuning calibration mode.

Step S103, entering a clock data recovery training mode.

Step S104, packet and display data reception.

In the offset calibration method, after the analog front end device is powered on or reset, step S102 is performed. Operation in the detuning calibration mode may be seen in the description in connection with fig. 1B. And after the offset calibration is completed, step S103 is performed. Step S103 is to operate the clock data recovery circuit to perform clock data recovery training, and display or group the data received by the analog front-end device after the clock data recovery circuit locks (including frequency locking and phase locking) (i.e., step S104).

In the offset calibration 110 of fig. 1B, an error amplifier is used, and the error amplifier itself has an offset, and the offset voltage generated by the offset cannot be compensated. In analog front-end equipment 100 such as that of fig. 1A, in addition to the offset caused by the offset calibration circuit 110, since the

switches

150 and 160 are directly connected to the input signal and the first stage of the multistage amplifier, the electronic devices such as the switches are soldered, and the switches connected to the pads weaken the protection capability of the electrostatic protection circuit, resulting in further deterioration of the performance of the analog front-end equipment. However, when the offset calibration method shown in fig. 1C is adopted, the offset calibration method is performed only once when the analog front-end device is powered on or reset, and if any change occurs in the working environment after the offset calibration is completed, the completed offset calibration is not accurate any more, so that the method cannot cope with the change in the working environment, which further reduces the performance of the analog front-end device.

At least one embodiment of the present disclosure provides an analog front-end device, including: a multistage amplifier including a plurality of stages and configured to amplify an input signal received by a first stage of the plurality of stages in multiple stages and output the amplified input signal at a last stage; a clock data recovery circuit configured to receive the amplified input signal and perform frequency and clock lock training based on the amplified output signal; and the offset calibration circuit of any one of the above embodiments, coupled to the clock data recovery circuit and the multi-stage amplifier, and configured to perform an offset calibration operation in response to an offset calibration indication.

At least one embodiment of the present disclosure provides a misalignment calibration method, including: controlling a clock data recovery circuit of analog front-end equipment to perform locking training, wherein the locking training comprises phase locking training and frequency locking training; controlling the clock data recovery circuit to perform locking training again in response to the clock data recovery circuit losing the lock; wherein controlling the clock data recovery circuit to perform lock training comprises: controlling a clock data recovery circuit to perform frequency locking training; controlling an offset calibration circuit of the analog front-end equipment to execute offset calibration operation in response to frequency locking of the clock data recovery circuit; and controlling the clock data recovery circuit to perform phase locking training in response to the completion of the offset calibration operation.

At least one embodiment of the present disclosure provides an apparatus for performing an offset calibration method for an analog front-end device, the apparatus including: a control unit configured to: controlling a clock data recovery circuit of analog front-end equipment to perform locking training, wherein the locking training comprises phase locking training and frequency locking training; controlling the clock data recovery circuit to perform locking training again in response to the clock data recovery circuit losing the lock; wherein controlling the clock data recovery circuit to perform lock training comprises: controlling a clock data recovery circuit to perform frequency locking training; controlling an offset calibration circuit of the analog front-end equipment to execute offset calibration operation in response to frequency locking of the clock data recovery circuit; and controlling the clock data recovery circuit to perform phase locking training in response to the completion of the offset calibration operation.

At least one embodiment of the present disclosure provides an offset calibration circuit, an analog front-end device, an offset calibration method, and an apparatus for performing the offset calibration method for the analog front-end device, thereby achieving an improvement in sensitivity of the analog front-end device and an improvement in accuracy of offset calibration.

Fig. 2 shows a schematic diagram of an offset calibration circuit of an embodiment of the present disclosure.

As shown in fig. 2, the offset calibration circuit 200 includes an offset polarity obtaining unit 210, an offset calibration logic unit 220, and a digitally controlled current source 230. One end of the offset polarity obtaining unit 210 is coupled to the offset calibration logic unit 220, and the other end of the offset polarity obtaining unit 210 obtains an externally input signal. The offset calibration logic unit 220 is coupled to the digitally controlled current source 230 and also outputs a signal to the outside. The digitally controlled current source 230 outputs two compensation signals to the outside.

The offset polarity acquisition unit 210 is configured to receive a signal for an offset calibration operation, and perform, for example, a majority voting operation based on a plurality of sample values of the signal to acquire the polarity of the signal.

In this embodiment, the signal for the offset adjustment operation includes an output signal of a multi-stage amplifier in the analog front-end device or an output signal of the clock data recovery circuit, but the signal for the offset adjustment operation is a single signal. For example, two signals are output from the clock data recovery circuit, and the offset polarity obtaining unit 210 receives any one signal from the clock data recovery circuit. For another example, the multi-stage amplifier outputs two signals, and the offset polarity obtaining unit 210 receives any one signal output by the multi-stage amplifier. The signal received by the offset polarity acquisition unit 210 may come from a wider variety of devices, depending on the analog front end equipment to be calibrated, and is not limited herein. The offset polarity obtaining unit 210 may receive a plurality of sample values of the signal for the offset calibration operation, or the offset polarity obtaining unit 210 samples the signal for the offset calibration operation to obtain the plurality of sample values.

Then, the offset polarity acquisition unit 210 performs a majority voting operation on the plurality of sample values to acquire the polarity of the signal. For example, 100 samples, of which 78 samples are negative (representing negative polarity of the signal) and 22 samples are positive (representing positive polarity of the signal), so as to obtain the negative polarity of the current signal. Alternatively, the offset polarity obtaining unit 210 may also use other manners of determining the polarity of the signal, such as directly determining the polarity of the signal without sampling.

After determining the polarity, the offset polarity obtaining unit 210 indicates the determined polarity to the offset calibration logic unit 220. For example, the offset polarity obtaining unit 210 and the offset calibration logic unit 220 preset "0" for negative polarity and "1" for positive polarity, so that the offset polarity obtaining unit 210 sends a corresponding value to inform the offset calibration logic unit 220 of the determined polarity. The numerical value is exemplified using decimal in the embodiments of the present disclosure, but the numerical value is not limited to decimal and may be any binary, such as binary. Alternatively, the offset polarity obtaining unit 210 and the offset calibration logic unit 220 are preset to use high/low levels to indicate the polarity is positive/negative.

Optionally, the offset polarity obtaining unit 210 is further configured to perform the majority voting operation once every preset time interval, or continuously perform the majority voting operation on a plurality of sampling values that are received most recently and have a fixed number. For example, the offset polarity acquisition unit 210 performs a majority voting operation on the sample values acquired within 1s every 1 second(s). For another example, the offset polarity obtaining unit 210 performs a majority voting operation to obtain the polarity every time 100 sampling values are obtained. So that the offset polarity acquisition unit 210 can flexibly select the manner in which the majority voting operation is performed.

The offset calibration logic unit 220 is configured to receive the polarity from the offset polarity acquisition unit 210 and transmit an offset calibration code corresponding to the polarity. In this embodiment, the misalignment calibration code is a value having a preset value range, and the value range may be all positive, all negative, or half of each positive or negative value. For example, the range is 1 to 100 (but not 50), -1 to-100 (but not-50), or-50 to +50 (but not 0). For example, the value range is 1-100, the offset calibration code is determined to be one of 1-49 when the received polarity is positive, and the offset calibration code is determined to be one of 51-100 when the received polarity is negative. Note that different value ranges, different numbers of values may be set, depending on the need for the accuracy of the misalignment calibration operation.

Optionally, the offset calibration logic 220 is further configured to output first information indicating entry into the offset calibration mode in response to receiving the polarity, and to output second information indicating exit from the offset calibration mode in response to a change in the polarity. The first information and the second information in this embodiment are intended to distinguish between entering and leaving the detuning calibration mode, and the first and second information may take various forms, such as levels, values. For example, the first information is high level, and the second information is low level.

The digitally controlled current source 230 is configured to receive the offset calibration code from the offset calibration logic unit 220 and output a compensation signal for the compensation signal according to the offset calibration code. For example, the compensation signal is used to compensate for the signal input to the multi-stage amplifier.

In one embodiment, the offset calibration logic 220 is further configured to continuously output the offset calibration code to the digitally controlled current source 230 before the polarity change occurs. The offset calibration logic unit 220 outputs the offset calibration code to the digitally controlled current source 230 once every certain time interval (for example, 0.1s), and the offset calibration code output each time is different before the polarity is changed. The certain time period may be determined according to the number of stages of the multi-stage amplifier, the length of the whole circuit, etc., for example, the more the number of stages of the multi-stage amplifier is, the longer the interval time may be set accordingly to ensure the accuracy of the offset calibration, but the certain time period is shorter, so that it may be considered to output the offset calibration code continuously or ceaselessly. Before the polarity is changed, the digitally controlled current source 230 generates and outputs different compensation signals according to different offset calibration codes.

In another embodiment, the offset calibration logic unit 220 is further configured to output the offset calibration code once every preset time interval. The difference from the previous embodiment is that the preset time for outputting the offset calibration code once at a preset time interval is longer in the present embodiment, and thus it is considered that the offset calibration code is intermittently output.

In another embodiment, the offset calibration logic unit 220 outputs the offset calibration code once in response to each receipt of the polarity sent by the offset polarity acquisition unit 210. In this embodiment, the offset calibration code is output only once when the polarity is changed, i.e. the output of the offset calibration code is triggered by the polarity change. Accordingly, although many offset calibration codes are not received, this does not mean that the digitally controlled current source 230 can only output the compensation signal once, but the digitally controlled current source 230 may be configured to continuously generate and output the compensation signal from after receiving the first offset calibration code until the next offset calibration code is received.

Optionally, in the above embodiment, the value of the offset calibration code output at each time is increased or decreased compared to the value of the offset calibration code output at the last time. The digitally controlled current source 230 may generate a compensation signal having an increased or decreased amplitude value in accordance with an increase or decrease in the value of the offset calibration code.

Further alternatively, the offset calibration code may be the same at each output before the polarity change, so that the compensation signal output is changed by the digitally controlled current source 230 after each receipt of the same offset calibration code.

Based on any of the above embodiments, the way of generating the offset calibration code and the compensation signal can be flexibly set according to the performance requirements of the digitally controlled current source 230 and the offset calibration logic unit 220.

Still optionally, in some embodiments, the polarities include positive and negative. In response to the polarity being positive, the value of the offset calibration code output at each time is reduced compared to the value of the offset calibration code output at the last time. In response to the polarity being negative, the value of the offset calibration code output at each time is increased compared to the offset calibration code output at the last time. For example, when the polarity is positive, by reducing the value of the offset calibration code, the amplitude value of the generated compensation signal is correspondingly reduced and/or the phase of the compensation signal is changed, so that the signal to be compensated and the compensation signal are cancelled, and finally the polarity of the signal received by the subsequent offset polarity acquiring unit 210 is changed.

In the present embodiment, the offset calibration circuit 200 omits the conventional error amplifier, and uses an improved offset polarity obtaining unit that does not introduce additional offset, so as to avoid the offset introduced by the error amplifier and ensure the accuracy of the offset calibration operation performed by the offset calibration circuit 200.

Fig. 3A illustrates a schematic diagram of an analog front end device provided in accordance with at least one embodiment of the present disclosure.

In fig. 3A, the analog front end 300 includes an offset calibration circuit 310, a multi-stage amplifier 320, and a clock data recovery circuit 330. For example, the analog front end device 300 also includes a voltage source 340, a switch 350, and a switch 360, respectively. The connection relationship inside the analog front-end device 300 can refer to the connection relationship of the analog front-end device 100 as described in fig. 1A, except that in the present embodiment, the offset calibration circuit 310 is, for example, the offset calibration circuit described in the above embodiments according to the present disclosure, such as the offset calibration circuit 200 in fig. 2, and the offset calibration circuit 310 receives only one output signal of the clock data recovery circuit 330 as an input.

Offset calibration circuit 310 is coupled to clock data recovery circuit 330 and multi-stage amplifier 320 and is configured to perform an offset calibration operation in response to an offset calibration indication. The offset calibration circuit 310 performs the offset calibration operation in a manner that is described in the related description of the offset calibration circuit 200 and is not repeated herein.

The multistage amplifier 320 includes a plurality of stages (e.g., N stages, N being a positive integer) and is configured to multistage-amplify an input signal received by a first stage of the plurality of stages and output the amplified input signal at a last stage.

The clock data recovery circuit 330 is configured to receive the amplified input signal and perform frequency and clock lock training based on the amplified output signal. For example, the analog front end 300 may perform a conventional misalignment calibration method as shown in FIG. 1C.

In this embodiment, by using the offset calibration circuit (e.g., the offset calibration circuit 200) provided by the embodiments of the present disclosure in an analog front-end device (e.g., the analog front-end device 300), it is possible to replace only the offset calibration circuit without changing the existing analog front-end device, and thus the accuracy of the analog front-end device performing the offset calibration operation is improved.

In one embodiment, the analog front end 300 may further include a processor (not shown in the figure), and the offset calibration indication is sent by the processor or by the clock data recovery circuit 330.

Optionally, the clock data recovery circuit 330 is configured to perform frequency locking and phase locking in sequence. For example, the clock data recovery circuit 330 performs frequency locking and then phase locking during the clock data recovery training.

Optionally, the offset calibration circuit 310 is further configured to perform an offset calibration operation in response to the clock data recovery circuit 330 completing the frequency lock training between the clock data recovery circuit 330 performing the frequency lock training and the phase lock training. For example, the clock data recovery circuit 330 sends the offset calibration instruction to the offset calibration circuit 310 after completing the frequency locking, so that the offset calibration circuit 310 performs the offset calibration operation.

Generally, in a receiver, the stability of the power supply voltage of the receiver is unknown, so that the optimal calibration effect cannot be ensured by performing offset calibration after the system is powered on. After the frequency locking of the clock data recovery circuit 330, the system of the receiver (and the transmitter as well) is already in a stable state, so that the present embodiment can improve the accuracy of performing the offset calibration operation.

Optionally, the offset calibration circuit 310 is further configured to perform an offset calibration operation in response to the clock data recovery circuit 330 completing the phase lock training. In addition to the clock data recovery circuit 330 completing the frequency locking training, the offset calibration circuit 310 may also choose to perform the offset calibration operation after the phase locking training is completed, which may also improve the accuracy of performing the offset calibration operation.

Optionally, the clock data recovery circuit 330 is further configured to output the clock signal and the data signal recovered based on the input signal in response to the offset calibration operation being performed and the frequency locking training and the phase locking training being both completed. That is, after the lock training of the clock data recovery circuit 330 is completed, if the offset calibration operation is also completed, the normal data transmission stage is entered, and the clock signal and the data signal recovered based on the input signal are output.

In some embodiments, the clock data recovery circuit 330 is further configured to: in response to the frequency or phase loss of lock, an indication of the offset calibration is sent to the offset calibration circuit 310.

After the clock data recovery circuit 330 is locked, if the error rate is too low or abnormal frequency drift occurs, the clock data recovery circuit 330 may be out of lock. In this embodiment, as long as the clock data recovery circuit 330 finds out the loss of lock, including the loss of frequency lock and/or the loss of phase lock, it sends an offset calibration instruction to the offset calibration circuit 310 to perform the offset calibration operation again. For example, the clock data recovery circuit 330 completes the frequency locking training and the offset calibration circuit 310 has also performed the offset calibration operation, and when the clock data recovery circuit 330 is performing the phase locking training process and finds that the phase locking cannot be completed or finds that the frequency is out of lock, the clock data recovery circuit 330 needs to perform the frequency locking training again and sends an offset calibration instruction to the offset calibration circuit 310 after the frequency locking training is completed again. For another example, the clock data recovery circuit 330 finds that at least one of the frequency and the phase is out-of-lock during normal data transmission, so as to perform the frequency locking training again, and sends the offset calibration instruction to the offset calibration circuit 310 after the frequency locking training is completed again.

By nesting the offset calibration operation in the frequency locking training and phase locking training processes, the clock data recovery circuit is responsible for repeated execution of the offset calibration operation, so that the offset of the analog front-end equipment caused by the loss of lock is unlocked.

The operating environment of the analog front-end device is not constant, and sometimes the analog front-end device needs to be set/updated with parameters, such as bias current and equalizer setting parameters. To ensure optimal offset calibration, in some embodiments, the clock data recovery circuit 330 is configured to send an offset calibration indication to the offset calibration circuit 310 in response to a change in configuration information of the analog front end device 330. For example, the clock data recovery circuit 330 resumes the frequency lock training and the phase lock training and sends the offset calibration indication to the offset calibration circuit 310. For another example, although the configuration information changes, the clock data recovery circuit 330 does not perform the frequency locking training and the phase locking training again, and only sends the offset calibration instruction to the offset calibration circuit 310, so that the offset calibration circuit 310 performs the offset calibration operation again.

Fig. 3B illustrates a schematic diagram of yet another analog front end device provided in accordance with at least one embodiment of the present disclosure.

In fig. 3B, analog front end 300' includes an offset calibration circuit 310, a multi-stage amplifier 320, and a clock data recovery circuit 330, similar to analog front end 300. For example, the analog front end 300' further includes a voltage terminal 340, a first switching unit 350, and a second switching unit 360.

The voltage terminal 340 is coupled to the second switching unit 350 and configured to provide a common voltage for offset calibration operation. For example, the voltage terminal 340 is a voltage source outputting two common voltages.

The first switching unit 350 is coupled to the offset calibration circuit 310 and the multi-stage amplifier 320, and configured to control an input signal to be input or not input to the first stage of the multi-stage amplifier 320 based on first information or second information sent by the offset calibration circuit 310, wherein the first information indicates entering the offset calibration mode, and the second information indicates leaving the offset calibration mode. The input signals are VIP and VIN in fig. 3B.

The second switching unit 360 is coupled to the offset calibration circuit 310 and the multi-stage amplifier 320, and configured to control or disable the common voltage input to the multi-stage amplifier 320 based on the first information or the second information. For example, when entering the offset calibration mode, the common voltage is controlled to be input to the multi-stage amplifier 320, and the input signal is disabled from being input to the multi-stage amplifier 320.

Optionally, the second switching unit 360 is coupled to a data input of a first stage (identified as "1" in fig. 3B) of the multi-stage amplifier 320 or to a data input of a second stage (identified as "2" in fig. 3B, otherwise similar) of the multi-stage amplifier 320. The first switching unit 350 is coupled to a data input terminal of a first stage of the multistage amplifier 320 or to a control signal input terminal of the first stage.

For example, similar to fig. 3A, the second switching unit 360 may be coupled with a data signal input terminal of the amplifier "1", and the first switching unit 350 is also coupled with a data signal input terminal of the amplifier "1". As another example, the second switching unit 360 may be coupled to a data signal input terminal of the amplifier "1", and the first switching unit 350 is coupled to a control signal input terminal of the amplifier "1" (e.g., the first switching unit 350 of fig. 3B). As another example, as shown in fig. 3B, the second switching unit 360 may be coupled to a data signal input terminal of the amplifier "2", and the first switching unit 350 is coupled to a control signal input terminal of the amplifier "1".

This embodiment provides multiple position setting mode for the switching unit, optionally keeps away from the solder joint of data input to under the little condition of accuracy influence to the maladjustment calibration, guarantee electrostatic protection circuit's protective capability. It is also possible to focus on ensuring the accuracy of the offset calibration in the case that the protection capability of the electrostatic protection circuit is sufficient. Therefore, more options are provided for the design of the analog front-end equipment.

Optionally, when the second switching unit 360 is coupled to the data input terminal of the second stage, the offset calibration circuit 310 is coupled to the data input terminal of the nth stage amplifier after the second stage. Alternatively, when the second switching unit 360 is coupled to the data input terminal of the first stage, the offset calibration circuit 310 is coupled to the data input terminal of the m-th stage amplifier after the first stage, where n is an integer greater than 2 and m is an integer greater than 1. For example, when the second switching unit 360 is coupled to the data input terminal of the amplifier "2", the output terminal of the offset calibration circuit 310 is coupled to the data input terminal of the amplifier "3".

Optionally, the first switching unit 350 is a logic and gate or a double-pole double-throw switch, and the second switching unit 360 is a double-pole double-throw switch. Note that the multi-stage amplifier 320 referred to in this disclosure is a two-way input, and if the input of the multi-stage amplifier is only a single-way input, the first and second switching units can adaptively select the single-pole single-throw switch.

Fig. 4A is a flowchart of a misalignment calibration method according to at least one embodiment of the present disclosure. As shown in fig. 4A, the offset calibration method may further include the following steps in addition to "power on or reset":

step S410, controlling a clock data recovery circuit of the analog front-end device to perform lock training, where the lock training includes phase lock training and frequency lock training.

And step S430, controlling the clock data recovery circuit to perform locking training again in response to the clock data recovery circuit losing lock.

The offset calibration method in this embodiment can be performed by the analog front-end device 100 shown in fig. 1A or the analog front-end device 300' provided in this embodiment of the disclosure, or can be performed by other devices that need to perform offset calibration operation and frequency and phase lock training.

After the analog front end device is powered on or reset, step S410 is performed. The clock data recovery circuit 330 is controlled to perform the lock training, for example, by sending a signal indicating to perform the lock training to the clock data recovery circuit 330. The clock data recovery circuit 330 performs frequency lock training and phase lock training in sequence.

Optionally, before performing step S430, the offset calibration circuit of the analog front-end device is further controlled to perform an offset calibration operation, which may be performed before performing S410, during performing S410, or after performing S410.

The step S430 is triggered by the loss of lock of the clock data recovery circuit, and if the clock data recovery circuit is lost of lock, the clock data recovery circuit is controlled to perform the lock training again, i.e., the step S410 is executed again. For example, if at least one of the frequency and the phase of the clock data recovery circuit 300 is out of lock, the clock data recovery circuit 330 is controlled to perform the frequency locking training and the phase locking training again.

FIG. 4B shows a more detailed flow chart of the misalignment calibration method shown in FIG. 4A.

As shown in fig. 4B, for example, step S410 includes:

step S411, the clock data recovery circuit is controlled to perform frequency locking training.

In step S413, the offset calibration circuit of the analog front-end device is controlled to perform an offset calibration operation in response to the frequency locking of the clock data recovery circuit.

In step S415, in response to the completion of the offset calibration operation, the clock data recovery circuit is controlled to perform phase lock training.

For example, the clock data recovery circuit 130 is controlled to perform a frequency locking training first, then the offset calibration circuit 110 is controlled to perform an offset calibration operation, and then the clock data recovery circuit 130 is controlled to perform a phase locking training, after the locking training of the clock data recovery circuit 130 is completed, if the clock data recovery circuit 130 is unlocked, the steps S411 to S415 are repeatedly performed.

Optionally, the misalignment calibration method further includes: and acquiring the error rate and/or the frequency drift of a data signal, wherein the data signal is acquired by the clock data recovery circuit based on the input signal of the analog front-end equipment. And controlling the clock data recovery circuit to unlock in response to the error rate being lower than the preset error rate and/or the frequency drift exceeding the preset frequency drift range.

Whether the clock data recovery circuit is in the out-of-lock state or not is determined according to the error rate and/or the frequency drift of the data signal, namely, when the error rate is lower than the preset error rate and the frequency drift exceeds the preset frequency drift range, the clock data recovery circuit is in the out-of-lock state substantially, but needs to be controlled to unlock. For example, when the clock data recovery circuit is in a locked state, information such as the bit error rate and/or the frequency drift of the data signal is continuously acquired.

Optionally, the offset calibration circuit is controlled to perform the offset calibration operation in response to a change in configuration information of the analog front-end device in the frequency-locked and phase-locked states. And when the configuration information of the analog front-end equipment is changed, triggering and controlling the offset calibration circuit to execute offset calibration operation. According to the execution relation between the offset calibration operation and the frequency locking training and the phase locking training of the clock data recovery circuit, the offset calibration circuit can be controlled to independently execute the offset calibration operation without performing phase locking and frequency locking again, or the frequency locking training, the offset calibration operation and the phase locking training are controlled to be performed in sequence, or the frequency locking training, the phase locking training and the offset calibration operation are controlled to be performed in sequence.

Optionally, the offset calibration circuit is controlled to perform an offset calibration operation, including: sending a signal indicating offset calibration operation to the offset calibration circuit; controlling the clock data recovery circuit to send a data signal to the offset calibration circuit so that the offset calibration circuit performs the following operations: receiving a data signal in response to receiving a signal indicating to perform a misalignment calibration operation; acquiring the polarity of a data signal; obtaining an offset calibration code corresponding to the polarity; and outputting a compensation signal for compensating the data signal according to the offset calibration code.

Taking the analog front end 300' in fig. 3B as an example, the controlling the offset calibration circuit 310 to perform the offset calibration operation includes: a signal indicating that the offset calibration operation is performed is sent to the offset calibration circuit 310, thereby entering the offset calibration mode. The clock data recovery circuit 330 is controlled to send a single data signal to the offset calibration circuit 310. The offset calibration circuit 310 receives the data signal, obtains the polarity of the data signal (e.g., using majority voting), obtains an offset calibration code relative to the polarity, and outputs a data input of a compensation signal value amplifier "3" that compensates the data signal.

Optionally, controlling the clock data recovery circuit to send a data signal to the offset calibration circuit includes: controlling a clock data recovery circuit to sample a data signal to obtain a plurality of sampling values; controlling the clock data recovery circuit to send a plurality of sampling values to the offset calibration circuit; wherein the offset calibration circuit performs the following operations: receiving a plurality of sample values in response to receiving a signal indicating to perform an offset calibration operation; performing a majority voting operation based on the plurality of sampling values to obtain a polarity of the data signal; obtaining an offset calibration code corresponding to the polarity; and outputting a compensation signal for compensating the data signal according to the offset calibration code.

Optionally, performing a majority voting operation based on the plurality of sample values comprises: executing majority voting operation once every preset time interval; alternatively, the majority voting operation is continuously performed on a fixed number of the most recently received sample values.

Optionally, obtaining the offset calibration code corresponding to the polarity includes: the offset calibration code is continuously acquired until the polarity is changed.

Optionally, the value of the offset calibration code obtained at each time is increased or decreased compared with the offset calibration code output last time.

Optionally, the polarity includes positive and negative; when the polarity is positive, the value of the offset calibration code obtained at each time is reduced compared with the value of the offset calibration code obtained at the last time; when the polarity is negative, the value of the offset calibration code obtained at each time is increased compared with the value of the offset calibration code obtained at the last time.

The operations performed by the clock data recovery circuit or the offset calibration circuit under control can be referred to the related descriptions of fig. 1A, fig. 3A and fig. 3B, and are not described again here.

Fig. 5 is a schematic diagram illustrating an apparatus for performing an offset calibration method for an analog front-end device according to at least one embodiment of the present disclosure.

As shown in fig. 5, the apparatus 500 for performing the offset calibration method for analog front-end devices includes a control unit 510.

The control unit 510 is configured to control the clock data recovery circuit of the analog front-end device to perform lock training, and to control the clock data recovery circuit to perform lock training again in response to the clock data recovery circuit losing lock. The lock training includes phase lock training and frequency lock training.

For example, the control unit 510 controls the clock data recovery circuit 130 of the analog front end device 100 to perform frequency lock training and phase lock training in sequence.

Controlling the clock data recovery circuit to perform lock training includes: and controlling the clock data recovery circuit to carry out frequency locking training. And controlling offset calibration circuits of the analog front-end equipment to execute offset calibration operation in response to the frequency locking of the clock data recovery circuit. And controlling the clock data recovery circuit to perform phase locking training in response to the completion of the offset calibration operation.

For example, the control unit 510 controls the clock data recovery circuit 130 to perform frequency locking training, controls the offset calibration circuit 110 to perform offset calibration after frequency locking, and controls the clock data recovery circuit 130 to perform phase locking training.

For example, in fig. 5, the control unit 510 controls the clock data recovery circuit 430 and the offset calibration circuit 410 of the analog front end device 400. The analog front end 400 may be, for example, the analog front end 100 of fig. 1A, the analog front end 300 of fig. 3A, and the analog front end 300' of fig. 3B. Although the apparatus 500 is shown external to the analog front end device 400 in fig. 5, the apparatus 500 itself may be the analog front end device 400 or a part of the analog front end device 400. For example, the apparatus 500 is a processor of the analog front end device 400, and the control unit 510 is a part of the processor. Still alternatively, the control unit 510 is a processor of the analog front-end device 400.

Optionally, the control unit 510 is further configured to control the offset calibration circuit to perform the offset calibration operation in response to a change in configuration information of the analog front-end device in the frequency-locked and phase-locked states.

Optionally, the control unit 510 is further configured to obtain a bit error rate and/or a frequency drift of a data signal, the data signal being obtained by the clock data recovery circuit based on an input signal of the analog front-end device; and controlling the clock data recovery circuit to unlock in response to the error rate being lower than the preset error rate and/or the frequency drift exceeding the preset frequency drift range.

Optionally, the offset calibration circuit is controlled to perform an offset calibration operation, including: and sending a signal indicating that the offset calibration operation is carried out to the offset calibration circuit. And controlling the clock data recovery circuit to send a data signal to the offset calibration circuit so that the offset calibration circuit performs the following operations. These operations include: receiving a data signal in response to receiving a signal indicating to perform a misalignment calibration operation; acquiring the polarity of a data signal; obtaining an offset calibration code corresponding to the polarity; and outputting a compensation signal for compensating the data signal according to the offset calibration code.

Optionally, controlling the clock data recovery circuit to send a data signal to the offset calibration circuit includes: controlling a clock data recovery circuit to sample a data signal to obtain a plurality of sampling values; controlling the clock data recovery circuit to send a plurality of sampling values to the offset calibration circuit; wherein the offset calibration circuit performs the following operations. These operations include: receiving a plurality of sample values in response to receiving a signal indicating to perform an offset calibration operation; performing a majority voting operation based on the plurality of sampling values to obtain a polarity of the data signal; obtaining an offset calibration code corresponding to the polarity; and outputting a compensation signal for compensating the data signal according to the offset calibration code.

According to the apparatus for executing the offset calibration method for the analog front-end device, the offset calibration method is executed by implementing the operation on the device in the analog front-end device through the control unit, and the problem that the offset calibration is inaccurate due to the fact that the clock data recovery circuit is unlocked or the configuration information of the analog front-end device is changed is solved, so that the accuracy of the offset calibration is improved, and more variable working environments can be met.

The following points need to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims

1. An offset calibration circuit comprising:

an offset polarity acquisition unit configured to receive a signal for offset calibration operation, and perform a majority voting operation based on a plurality of sample values of the signal to acquire a polarity of the signal;

the offset calibration logic unit is configured to receive the polarity of the signal from the offset polarity acquisition unit and send an offset calibration code corresponding to the polarity; and

a digitally controlled current source configured to receive the offset calibration code from the offset calibration logic unit and output a compensation signal for compensating the signal according to the offset calibration code.

2. The offset calibration circuit of claim 1, wherein,

the offset calibration logic is further configured to output first information indicating entry into an offset calibration mode in response to receiving the polarity and output second information indicating exit from the offset calibration mode in response to a change in the polarity.

3. The offset calibration circuit of claim 1, wherein,

the offset polarity acquisition unit is further configured to perform a majority voting operation once every a preset time interval or continuously perform a majority voting operation on a plurality of sampling values of a fixed number that are received most recently.

4. The offset calibration circuit of claim 1, wherein,

the offset calibration logic is further configured to continue outputting the offset calibration code to the digitally controlled current source until the polarity is changed.

5. The offset calibration circuit of claim 4, wherein,

the offset calibration logic unit is further configured to output an offset calibration code once every preset time interval, or output an offset calibration code once in response to receiving the polarity sent by the offset polarity acquisition unit each time;

wherein, the value of the offset calibration code output at each time is increased or decreased compared with the value of the offset calibration code output at the last time.

6. The offset calibration circuit of claim 4 or 5, wherein the polarities include positive and negative,

in response to the polarity being positive, the value of the offset calibration code output at each time is reduced compared to the offset calibration code output at the last time;

in response to the polarity being negative, the value of the offset calibration code output at each time is increased compared to the offset calibration code output at the last time.

7. An analog front end device comprising:

a multistage amplifier including a plurality of stages and configured to amplify an input signal received by a first stage of the plurality of stages in multiple stages and output the amplified input signal at a last stage;

a clock data recovery circuit configured to receive the amplified input signal and perform frequency and clock lock training based on the amplified output signal; and

the offset calibration circuit of any of claims 1-6, coupled with the clock data recovery circuit and the multi-stage amplifier, and configured to perform an offset calibration operation in response to an offset calibration indication.

8. The analog front end device of claim 7, further comprising a processor, wherein the offset calibration indication is transmitted by the processor or by the clock data recovery circuit.

9. The analog front-end device of claim 7,

the clock data recovery circuit is configured to perform frequency locking and phase locking in sequence.

10. The analog front-end device of claim 7,

the offset calibration circuit is further configured to perform the offset calibration operation in response to the clock data recovery circuit completing the frequency lock training between the clock data recovery circuit performing frequency lock training and phase lock training.

11. The analog front-end device of claim 9,

the offset calibration circuit is further configured to perform the offset calibration operation in response to the clock data recovery circuit completing phase lock training.

12. The analog front-end device of claim 7,

the clock data recovery circuit is further configured to output a clock signal and a data signal recovered based on the input signal in response to completion of the offset calibration operation and completion of both the frequency locking training and the phase locking training.

13. The analog front-end device of claim 7, wherein the clock data recovery circuit is further configured to:

sending the offset calibration indication to the offset calibration circuit in response to a frequency or phase loss of lock; alternatively, the first and second electrodes may be,

and sending the offset calibration indication to the offset calibration circuit in response to the change of the configuration information of the analog front-end equipment.

14. The analog front-end device according to any one of claims 7-13, wherein the analog front-end device further comprises:

a first switching unit coupled to the offset calibration circuit and the multi-stage amplifier, configured to control the input signal to be input or not input to the first stage based on first information or second information transmitted by the offset calibration circuit, wherein the first information indicates entering an offset calibration mode, and the second information indicates leaving the offset calibration mode;

a second switching unit coupled with the offset calibration circuit and the multi-stage amplifier, configured to control or disable a common voltage input to the multi-stage amplifier based on the first information or the second information; and

a voltage terminal coupled with the second switching unit and configured to provide the common voltage for the offset calibration operation.

15. The analog front-end device of claim 14, wherein the second switching unit is coupled with a data input of the first stage or with a data input of a second stage of the plurality of stages; or

The first switching unit is coupled to a data input of the first stage or to a control signal input of the first stage.

16. The analog front-end device of claim 15, wherein,

when the second switching unit is coupled with the data input end of the second stage, the offset calibration circuit is coupled with the data input end of the nth stage amplifier after the second stage; or

When the second switching unit is coupled with the data input end of the first stage, the offset calibration circuit is coupled with the data input end of the m-th stage amplifier after the first stage, wherein n is an integer larger than 2, and m is an integer larger than 1.

17. The analog front-end device of claim 14, wherein the first switching unit is a logical and gate or a double pole double throw switch and the second switching unit is a double pole double throw switch.