CN114070327A

CN114070327A - Compression and decompression method for FPGA code stream data

Info

Publication number: CN114070327A
Application number: CN202111373243.6A
Authority: CN
Inventors: 徐浩然; 夏金军
Original assignee: Ehiway Microelectronic Science And Technology Suzhou Co ltd
Current assignee: Ehiway Microelectronic Science And Technology Suzhou Co ltd
Priority date: 2021-11-19
Filing date: 2021-11-19
Publication date: 2022-02-18

Abstract

The invention discloses a compression and decompression method of FPGA code stream data, which comprises the following steps: firstly, acquiring the position of code stream data to be compressed in equipment; analyzing the position of the whole code stream data to be compressed in the equipment, and dividing the code stream data to be compressed into a plurality of data blocks in a row unit according to the position; thirdly, compressing the data block under two conditions that all the data in each row are the same and the individual data in each row are different; the decompression method comprises the following steps: analyzing whether the code stream data can be fully compressed or partially compressed in a segmentation mode, and when the full compression is enabled, decompressing by adopting a partial decompression method; when segmented portion compression is enabled, decompression is performed using a segmented portion decompression method. The invention has higher compression ratio to the code stream data with high repetition rate, can occupy less resources, greatly improves the configuration efficiency and can further carry out confidentiality to the user circuit.

Description

Compression and decompression method for FPGA code stream data

Technical Field

The invention belongs to the technical field of FPGA application, and particularly relates to a compression and decompression method of FPGA code stream data.

Background

In recent years, with the appearance of large-scale and high-performance FPGAs and the improvement of software and hardware design flows and design methods, the reconfigurable system based on the FPGA gradually becomes a new hot spot for the research in the field of computer systems. Hardware information in the reconfigurable system based on the FPGA, namely configuration information of the FPGA can be modified or dynamically called like software by using an advanced EDA tool, so that the system has high performance of hardware calculation and high flexibility of the software.

A reconfigurable system is utilized to realize a computational logic, and the running overhead of the computational logic comprises two parts: the first is the calculation time, i.e. the time used for the actual calculation; the second is the configuration time, i.e. the delay time generated by configuring the internal programmable device. However, with the continuous expansion of the FPGA scale and the continuous enrichment of internal resources, the configuration time becomes longer and longer, and the application of reconfigurable computing is severely restricted. One main part of the FPGA configuration time is consumed in the process of transferring the configuration file from the off-chip memory to the FPGA, so that the scale of the configuration file is reduced, and the FPGA configuration time can be shortened; in addition, the size of the off-chip memory can be reduced, thereby saving system cost.

The compression process of the FPGA code stream data is as shown in fig. 1, and the configuration file generated by the EDA tool is compressed first, and then the compressed configuration file is stored in an off-chip nonvolatile memory (such as a memory based on a Flash process).

The decompression process of the FPGA code stream data is as shown in fig. 2, when the FPGA system needs to configure the file, the system will immediately read the data of the configuration file from the off-chip nonvolatile memory, then obtain the original configuration data stream through on-chip decompression, and directly send the original configuration data stream into the FPGA for configuration.

In the prior art, a dictionary-based compression method is mostly adopted for FPGA code stream data. When a character or a string in the input data stream matches a character or a string in the dictionary, the compressor outputs an identification of the matching location in the dictionary. The purpose of compression can be achieved as long as the number of coded word bits used to represent the corresponding matching position is less than the number of bits of the corresponding matching string in the input data stream. If the design is carefully made, a quite good compression effect can be achieved. The dictionary can be divided into static dictionary compression and dynamic dictionary compression according to whether the dictionary can be updated in the compression process.

A static dictionary is a substantially fixed dictionary that sometimes allows strings to be added, but does not allow strings to be deleted. Dynamic dictionaries are generally based on the empty dictionary, and the content and size of the dictionary is variable during compression.

However, the general dictionary compression and decompression method has the following two defects:

(1) when most of repeated contents exist in the code stream, the compressed code needs to be generated every fixed byte number, and the compression rate is reduced.

(2) Only the storage size and the data transmission time can be reduced, and the configuration time cannot be reduced.

Disclosure of Invention

The technical problem to be solved by the present invention is to provide a compression method for FPGA code stream data, which has a higher compression ratio for code stream data with a high repetition rate and can occupy less resources, in view of the above-mentioned deficiencies in the prior art.

In order to solve the technical problems, the invention adopts the technical scheme that: a compression method of FPGA code stream data comprises the following steps:

step one, acquiring the position of code stream data to be compressed in equipment;

analyzing the position of the whole code stream data to be compressed in the equipment, and dividing the code stream data to be compressed into a plurality of data blocks in a row unit according to the position;

and step three, compressing the data block under two conditions that all the data in each row are the same and the individual data in each row are different.

In the third step, the specific method for compressing the data block under the two conditions that all the data in each row are the same and the individual data in each row are different comprises the following steps:

analyzing whether the data of each row of data blocks are all the same, and compressing the data blocks by adopting a method of skipping the whole row when the data of each row of data blocks are all the same; when the data of each row of data blocks are different from each other, compressing the data blocks by adopting a method of skipping in sections;

the method for compressing the data block by adopting the method of skipping the whole line comprises the following steps: when the data of each row of data blocks are all the same, replacing the whole data with a key representing skipping a row of data blocks at the end of the last data block; when the data blocks of the continuous rows of data are the same, replacing the data blocks of the rows of data by keywords representing the data blocks of the rows of data;

the method for compressing the data block by adopting the segment skipping method comprises the following steps: analyzing the data of each row of data blocks, using a certain number of data of each row of data blocks as a group, and replacing the previous groups of data with part of special keywords when the data continuously exceeding the certain group are the same.

The invention also discloses a method for decompressing the FPGA code stream data, which greatly improves the configuration efficiency and can further keep the user circuit secret, and the method comprises the following steps: analyzing whether the code stream data can be fully compressed or partially compressed in a segmentation mode, and when the full compression is enabled, decompressing by adopting a partial decompression method; when the segmented portion compression is enabled, decompressing by adopting a segmented portion decompression method;

the method for decompressing by adopting the partial decompression method comprises the following steps: analyzing a key word representing one row of data blocks and key words representing a plurality of row of data blocks in the code stream data, and controlling addresses and data needing to be skipped during configuration according to the key words and a decompression protocol;

the method for decompressing by adopting the segmented partial decompression method comprises the following steps: and analyzing part of special keywords in the code stream data, and configuring corresponding data and addresses according to the keywords and the decompression protocol.

Compared with the prior art, the invention has the following advantages:

1. compared with the traditional method, the method for compressing and decompressing the FPGA code stream data can compress the code stream with high repetition rate at a higher compression rate, and consumes less time when the FPGA is configured, thereby improving the configuration speed.

2. According to the FPGA code stream data compression method, the data values representing the same data in the uncompressed and non-encrypted code stream are replaced by the keywords of the relevant protocol, so that the purpose of compression is achieved; the size of the code stream file with high repetition rate can be compressed to be smaller, so that the compressed code stream is placed in the off-chip storage device, and less resources can be occupied.

3. According to the FPGA code stream data compression method, the code stream length of each compression is determined by the same data number, and the data with the fixed length does not need to be compressed according to a dictionary, so that the compression rate of code stream data with high repetition rate is higher.

4. According to the FPGA code stream data decompression method, the partial decompression method does not need to decompress the data and then configure the data, the data configuration can be directly skipped according to the decompression method, and the segmented partial decompression method decompresses the segmented compressed data of a certain part and then configures the data at one time, so that the configuration efficiency is greatly improved.

5. The FPGA code stream data decompression method has the advantages that partial contents do not need to be decompressed completely, and the possibility that a user circuit is cracked is reduced, so that the user circuit can be further kept secret.

The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.

Drawings

Fig. 1 is a schematic diagram of a compression process of FPGA code stream data.

Fig. 2 is a schematic diagram of a decompression process of FPGA code stream data.

Fig. 3 is a schematic flow chart of the compression method of the FPGA code stream data of the present invention.

Fig. 4 is a schematic flow chart of the decompression method of the FPGA code stream data according to the present invention.

Detailed Description

The following describes a compression method of FPGA code stream data according to the present invention with embodiment 1, and a decompression method of FPGA code stream data according to the present invention with embodiment 2.

Example 1

As shown in fig. 3, the method for compressing FPGA code stream data of this embodiment includes the following steps:

In this embodiment, the specific method for compressing the data block in the three steps under the two conditions that all the data in each row are the same and that individual data in each row are different includes:

The compression of FPGA code stream data is realized on a software level and divided into a full compression method and a segmented partial compression method, when the data block is compressed by adopting the full compression method, the data of the whole data block is directly skipped, and the address is directly skipped, namely, the skipping configuration is carried out; when the data block is compressed by adopting a method of segmented partial compression, the whole part cannot be skipped because individual data in the data block are different, the method of segmented partial compression is adopted for the part of data, and a certain group of identical data in the data block is replaced by a part of special keywords for compression. According to the FPGA code stream data compression method, the data values representing the same data in the uncompressed and non-encrypted code stream are replaced by the keywords of the relevant protocol, so that the purpose of compression is achieved; the size of the code stream file with high repetition rate can be compressed to be smaller, so that the compressed code stream is placed in the off-chip storage device, and less resources can be occupied.

The compression method of FPGA code stream data of the invention does not need a dictionary, and can compress a larger data volume with fewer keywords; moreover, the code stream length of each compression of the compression method is determined by the same data number, and the data with fixed length does not need to be compressed according to a dictionary, so that the compression rate of the code stream data with high repetition rate is higher; the invention not only reduces the configuration time from the file size and data transmission, but also reduces the configuration time from the internal configuration efficiency.

Example 2

As shown in fig. 4, the method for decompressing FPGA code stream data of this embodiment includes: analyzing whether the code stream data can be fully compressed or partially compressed in a segmentation mode, and when the full compression is enabled, decompressing by adopting a partial decompression method; when the segmented portion compression is enabled, decompressing by adopting a segmented portion decompression method;

The decompression of FPGA code stream data is realized on a software level, the decompression is carried out according to two conditions of full compression and segmented partial compression corresponding to a compression method, the partial decompression method does not need to carry out configuration after data decompression, the data configuration can be directly skipped according to the decompression method, and the segmented partial decompression method carries out one-time configuration after some part of segmented compressed data is decompressed, so that the configuration efficiency is greatly improved.

The decompression method in the invention has the advantages that partial content does not need to be decompressed completely, and the possibility of cracking the user circuit is reduced, so that the user circuit can be further kept secret.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims

1. A compression method of FPGA code stream data is characterized by comprising the following steps:

2. The method for compressing FPGA code stream data according to claim 1, characterized in that: in the third step, the specific method for compressing the data block under the two conditions that all the data in each row are the same and the individual data in each row are different is as follows:

3. A method for decompressing FPGA code stream data using the compression method according to claim 2, the method comprising: analyzing whether the code stream data can be fully compressed or partially compressed in a segmentation mode, and when the full compression is enabled, decompressing by adopting a partial decompression method; when the segmented portion compression is enabled, decompressing by adopting a segmented portion decompression method;