CN114069829B - Dual-path redundant power supply self-cutting and recovering circuit - Google Patents

Dual-path redundant power supply self-cutting and recovering circuit Download PDF

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Publication number
CN114069829B
CN114069829B CN202111382675.3A CN202111382675A CN114069829B CN 114069829 B CN114069829 B CN 114069829B CN 202111382675 A CN202111382675 A CN 202111382675A CN 114069829 B CN114069829 B CN 114069829B
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field effect
effect transistor
diode
channel field
input
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CN114069829A (en
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胡庚
解彦强
陈欢
徐云华
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Beijing Institute of Computer Technology and Applications
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Beijing Institute of Computer Technology and Applications
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J9/00—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting
    • H02J9/04—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source
    • H02J9/06—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems
    • H02J9/068—Electronic means for switching from one power supply to another power supply, e.g. to avoid parallel connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H9/00—Details of switching devices, not covered by groups H01H1/00 - H01H7/00
    • H01H9/54—Circuit arrangements not adapted to a particular application of the switching device and for which no provision exists elsewhere
    • H01H9/547—Combinations of mechanical switches and static switches, the latter being controlled by the former
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor

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  • Business, Economics & Management (AREA)
  • Emergency Management (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)

Abstract

The invention relates to a double-circuit redundant power supply self-switching and recovering circuit, and belongs to the field of power supply switching control. The invention comprises the following steps: the input EMI filter circuit, the ideal diode or the gate control circuit, the photo MOS and magnetic latching relay control circuit and the P channel MOS parallel switching main circuit. The output end of the input EMI filter circuit is connected with the input end of the ideal diode or gate control circuit and the input end of the photo MOS+magnetic latching relay control circuit, one branch output end of the ideal diode or gate control circuit is connected with the input end of the P-channel MOS parallel switching main circuit, the other branch output end of the ideal diode or gate control circuit is connected with the output end of the P-channel MOS parallel switching main circuit, and the output end of the photo MOS+magnetic latching relay control circuit is connected with the input end of the P-channel MOS parallel switching main circuit. The invention has the characteristics of small circuit pressure drop and heat power consumption, small volume, small EMI electromagnetic interference, strong vibration stress resistance and reliable control.

Description

Dual-path redundant power supply self-cutting and recovering circuit
Technical Field
The invention belongs to the field of power supply switching control, and particularly relates to a double-circuit redundant power supply self-switching and recovering circuit.
Background
The power supply of the on-board and on-board equipment generally comprises on-board battery power supply and ground power supply, ground power supply or on-board battery power supply is generally adopted in ground test, and on-board battery power supply is adopted in suspension flight test, so that the design of the double-circuit redundant power supply and switching circuit is particularly important. The traditional multipath power supply switching circuit adopts the mode of isolating and supplying power by a rectifier diode, assisting in controlling power supply and switching a high-power electromagnetic relay, the circuit voltage drop and heating power consumption of the rectifier diode in the circuit are large, the high-power electromagnetic relay has large volume, large electromagnetic interference and poor random vibration stress resistance, and the autonomous switching and recovery functions cannot be realized.
Disclosure of Invention
First, the technical problem to be solved
The invention aims to solve the technical problem of providing a double-circuit redundant power supply self-cutting and recovering circuit so as to solve the problems of large line voltage drop, large heating power consumption, large electromagnetic interference, incapability of self-switching and recovering and the like in the traditional power supply switching circuit scheme.
(II) technical scheme
In order to solve the technical problems, the invention provides a double-circuit redundant power supply self-switching and recovery circuit, which comprises an input EMI filter circuit, an ideal diode or gate control circuit, a photo MOS+magnetic latching relay control circuit and a P channel MOS parallel switching main circuit, wherein the output end of the input EMI filter circuit is connected with the input end of the ideal diode or gate control circuit, one path of the output end of the ideal diode or gate control circuit is connected with the input end of the P channel MOS parallel switching main circuit, the other path of the output end of the ideal diode or gate control circuit is connected with the output end of the P channel MOS parallel switching main circuit, the input end of the photo MOS+magnetic latching relay control circuit is connected with the output end of the input EMI filter circuit, and the output end of the photo MOS+magnetic latching relay control circuit is connected with the input end of the P channel MOS parallel switching main circuit.
Further, the input EMI filter circuit includes: common mode inductance L1, common mode inductance L3, differential mode inductance L2, differential mode inductance L4, differential mode capacitance C1, differential mode capacitance C2, differential mode capacitance C5, differential mode capacitance C6, common mode capacitance C3, common mode capacitance C4, common mode capacitance C7, and common mode capacitance C8.
Further, in the input EMI filter circuit, in the first branch, an input positive end of the common-mode inductor L1 is connected to the input high end Va1, one end of the differential-mode capacitor C1 is connected to the input high end Va1, the other end of the differential-mode capacitor C1 is connected to an input negative end of the common-mode inductor L1, an output positive end of the common-mode inductor L1 is connected to one end of the differential-mode inductor L2 and one end of the differential-mode capacitor C2, the other end of the differential-mode capacitor C2 is connected to an output negative end of the common-mode inductor L1, the other end of the differential-mode inductor L2 is connected to one end of the common-mode capacitor C3 and one end of the common-mode capacitor C4, and the other end of the common-mode capacitor C4 is connected to an output negative end of the common-mode inductor L1; in the second path, the input positive end of the common-mode inductor L3 is connected with the input high end Va2, one end of the differential-mode capacitor C5 is connected with the input high end Va2, the other end of the differential-mode capacitor C5 is connected with the input negative end of the common-mode inductor L3, the output positive end of the common-mode inductor L3 is respectively connected with one end of the differential-mode inductor L4 and one end of the differential-mode capacitor C6, the other end of the differential-mode inductor C6 is connected with the output negative end of the common-mode inductor L3, the other end of the differential-mode inductor L4 is respectively connected with one end of the common-mode capacitor C7 and the output high end Vb2, and the other end of the common-mode capacitor C7 is respectively connected with the ground of the casing and one end of the common-mode capacitor C8; the negative output end of the common-mode inductor L1 is connected with the negative output end of the common-mode inductor L3.
Further, the ideal diode or gate control circuit includes: ideal diode controller U1, ideal diode controller U2, N-channel field effect transistor S1, N-channel field effect transistor S2, N-channel field effect transistor S3, N-channel field effect transistor S4, transient voltage suppression diode D1, transient voltage suppression diode D2, gate drive resistor R1, gate drive resistor R2, gate drive resistor R4, gate drive resistor R5, current limiting resistor R3, current limiting resistor R6, filter capacitor C9, and filter capacitor C10.
Further, IN the ideal diode or GATE control circuit, IN the first branch, the cathode of the transient suppression diode D1 is connected to the input high terminal Vb1, the anode of the transient suppression diode D1 is connected to the Vss terminal of the ideal diode controller U1, the IN terminal and the input high terminal Vb1 of the ideal diode controller U1, the SOURCE terminal of the ideal diode controller U1 is connected to the input high terminal Vb1, the SOURCE terminal of the N-channel field effect transistor S2, the GATE of the N-channel field effect transistor S1 is connected to one end of the GATE driving resistor R1, the GATE of the N-channel field effect transistor S2 is connected to one end of the GATE driving resistor R2, the other end of the GATE driving resistor R1 is connected to the other end of the GATE driving resistor R2, the GATE terminal of the ideal diode controller U1, the drain terminal of the N-channel field effect transistor S1 is connected to the drain terminal of the N-channel field effect transistor S2, the OUT terminal of the ideal diode controller U1, one end of the current limiting resistor R3, the output high terminal Vc, the other end of the current limiting resistor R3 is connected to one end of the ideal diode C9 of the filter capacitor of the ideal diode controller U1, and the other end of the filter capacitor C9 of the ideal diode controller U1; IN the second path, the cathode of the transient suppression diode D2 is connected to the input high terminal Vb2, the anode of the transient suppression diode D2 is connected to the Vss terminal of the ideal diode controller U2, the IN terminal of the ideal diode controller U2 is connected to the input high terminal Vb2, the SOURCE terminal of the N-channel field effect transistor S3, and the SOURCE terminal of the N-channel field effect transistor S4, the GATE of the N-channel field effect transistor S3 is connected to one terminal of the GATE driving resistor R4, the GATE of the N-channel field effect transistor S4 is connected to one terminal of the GATE driving resistor R5, the other terminal of the GATE driving resistor R4 is connected to the other terminal of the GATE driving resistor R5, the GATE terminal of the ideal diode controller U2, the drain terminal of the N-channel field effect transistor S3 is connected to the drain terminal of the N-channel field effect transistor S4, the OUT terminal of the ideal diode controller U2, one terminal of the current limiting resistor R6, and the output high terminal Ve, and the other terminal of the current limiting resistor R6 are connected to one terminal of the ideal diode controller U2, and the capacitor C10 is connected to the other terminal of the ideal diode 2, and the capacitor C10 is connected to the other terminal of the filter Vss.
Further, the "photomos+magnetic latching" relay control circuit includes: the photo MOS relay JG1, the magnetic latching relay JB1, the rectifying diode D3, the rectifying diode D4, the rectifying diode D5, the rectifying diode D6, the freewheel diode D7, the freewheel diode D8, the current limiting resistor R7, the current limiting resistor R8, the current limiting resistor R9, the current limiting resistor R10, the filter capacitor C11 and the filter capacitor C12.
Further, in the 'photo MOS+magnetic latching' relay control circuit, an output high end Vd is respectively connected with a contact K1-1 end of a magnetic latching relay JB1 and a contact K2-1 end of the magnetic latching relay JB1, the contact K1-1 end of the magnetic latching relay JB1 is connected with a contact K1-2 end of the magnetic latching relay JB1 and a signal ground, and the contact K2-1 end of the magnetic latching relay JB1 is connected with the contact K2-2 end of the magnetic latching relay JB1 and the signal ground, and the contacts K1-3 and K2-3 of the magnetic latching relay JB1 are respectively suspended; the coil control end 1IN+ of the magnetic latching relay JB1 is respectively connected with one end of a current limiting resistor R7 and the cathode of a freewheeling diode D8, the coil control end 2IN+ of the magnetic latching relay JB1 is respectively connected with one end of the current limiting resistor R8 and the cathode of the freewheeling diode D7, the other end of the current limiting resistor R7 is respectively connected with the cathode of a rectifying diode D3 and the cathode of a rectifying diode D4, the other end of the current limiting resistor R8 is respectively connected with the cathode of a rectifying diode D5 and the cathode of a rectifying diode D6, the anode of the rectifying diode D3 is connected with the anode of the rectifying diode D5 and the input Vb1 end, the anode of the rectifying diode D4 is connected with the anode of the rectifying diode D6 and the input Vb2 end, the anode of the freewheeling diode D7 is connected with the coil control end 2IN-, the output 2OUT+ end of the photo MOS relay JG1 of the magnetic latching relay JB1, and the anode of the freewheeling diode D8 is connected with the coil control end 1IN-, the output 1OUT+ end of the photo MOS relay JG1 of the magnetic latching relay JB 1; the output 1 OUT-end of the photo MOS relay JG1 is connected with the output 2 OUT-end of the photo MOS relay JG1 and signal ground; one end of the current limiting resistor R9 is connected with a control signal Ctrl-ON+ end, the other end of the current limiting resistor R9 is connected with one end of a filter capacitor C11, the other end of the filter capacitor C11 is connected with a control signal Ctrl-ON-end, the input control end 1 IN-of the light MOS relay JG1, one end of the current limiting resistor R10 is connected with a control signal Ctrl-OFF+ end, the other end of the current limiting resistor R10 is connected with one end of a filter capacitor C12, the input control end 2IN+ of the light MOS relay JG1, and the other end of the filter capacitor C12 is connected with the control signal Ctrl-OFF-end and the input control end 2 IN-of the light MOS relay JG 1.
Further, the "P-channel MOS parallel connection" switching main circuit includes a P-channel field effect transistor S5, a P-channel field effect transistor S6, a P-channel field effect transistor S7, a P-channel field effect transistor S8, a zener diode D9, an energy storage filter capacitor C13, a voltage dividing resistor R11, a voltage dividing resistor R12, a gate driving resistor R13, a gate driving resistor R14, a gate driving resistor R15, and a gate driving resistor R16.
Further, in the "P-channel MOS parallel connection" switching main circuit, the input high end Vc is connected to the cathode of the zener diode D9, one end of the voltage dividing resistor R11, one end of the energy storage filter capacitor C13, the source of the P-channel fet S5, the source of the P-channel fet S6, the source of the P-channel fet S7, the source of the P-channel fet S8, the anode of the zener diode D9 is connected to the other end of the voltage dividing resistor R11, one end of the voltage dividing resistor R12, the other end of the energy storage filter capacitor C13, one end of the gate driving resistor R14, one end of the gate driving resistor R15, one end of the gate driving resistor R16, the other end of the gate driving resistor R13 is connected to the gate of the P-channel fet S5, the other end of the gate driving resistor R15 is connected to the gate of the P-channel fet S7, the other end of the gate driving resistor R16 is connected to the gate of the P-channel fet S8, the drain of the P-channel fet S5 is connected to the drain of the P-channel fet S6, and the drain of the drain fet v-channel fet S8 is connected to the drain of the P-channel fet S12, respectively.
Further, the circuit is used for powering on-board and on-board equipment.
(III) beneficial effects
The invention provides a double-channel redundant power supply self-switching and recovering circuit, which adopts an ideal diode or gate control circuit and a photo MOS+magnetic latching relay control circuit to control the on and off of a P-channel MOS parallel switching main circuit, realizes the double-channel redundant power supply self-switching and recovering function, and has the characteristics of small volume, low circuit voltage drop and heat consumption, low EMI electromagnetic interference, strong vibration stress resistance, reliable control and the like.
Drawings
FIG. 1 is a schematic block diagram of a dual redundancy power supply autonomous switching and restoration circuit;
FIG. 2 is a diagram of an input EMI filter circuit for a dual redundancy power supply autonomous switching and restoration circuit;
FIG. 3 is a diagram of an ideal diode or gate control circuit for a dual redundancy power supply autonomous switching and restoration circuit;
FIG. 4 is a diagram of a circuit for controlling a "photo MOS+magnetic latching" relay of a dual redundancy power supply autonomous switching and restoration circuit;
fig. 5 is a diagram of a main circuit of a "P-channel MOS parallel" switching circuit for a dual redundancy power supply autonomous switching and restoration circuit.
Detailed Description
To make the objects, contents and advantages of the present invention more apparent, the following detailed description of the present invention will be given with reference to the accompanying drawings and examples.
The invention aims to provide a double-circuit redundant power supply self-cutting and recovering circuit, which solves the problems of large line voltage drop, large heating power consumption, large electromagnetic interference, incapability of self-switching and recovering and the like in the traditional power supply switching circuit scheme.
The invention discloses a double-circuit redundant power supply autonomous switching and recovering circuit, which comprises: the input EMI filter circuit (1), the ideal diode or the gate control circuit (2), the photo MOS and magnetic latching relay control circuit (3) and the P channel MOS parallel switching main circuit (4). The output end of the input EMI filter circuit (1) is connected with the input end of an ideal diode or gate control circuit (2) and the input end of a 'photo MOS+magnetic latching' relay control circuit (3), the output end of one branch (2 a) of the ideal diode or gate control circuit (2) is connected with the input end of a 'P-channel MOS parallel' switching main circuit (4), the output end of the other branch (2 b) of the ideal diode or gate control circuit (2) is connected with the output end of the 'P-channel MOS parallel' switching main circuit (4), and the output end of the 'photo MOS+magnetic latching' relay control circuit (3) is connected with the input end of the 'P-channel MOS parallel' switching main circuit (4).
The invention adopts an ideal diode or gate control circuit and a photo MOS+magnetic latching relay control circuit to control the on and off of a P channel MOS parallel switching main circuit, thereby realizing the functions of automatic switching and recovery of double-path redundant power supply. The circuit solves the defects of large circuit conduction voltage drop, large heating power consumption, large volume of a high-power electromagnetic relay, large electromagnetic interference, poor random vibration stress resistance and the like in the traditional multi-channel power supply switching circuit, and has the characteristics of small circuit voltage drop and heat power consumption, small volume, small electromagnetic interference (EMI), strong vibration stress resistance, reliable control and the like.
A dual redundant power supply autonomous switching and restoration circuit comprising: the input EMI filter circuit, the ideal diode or the gate control circuit, the photo MOS and magnetic latching relay control circuit and the P channel MOS parallel switching main circuit.
Wherein the input EMI filter circuit comprises: common mode inductance L1, common mode inductance L3, differential mode inductance L2, differential mode inductance L4, differential mode capacitance C1, differential mode capacitance C2, differential mode capacitance C5, differential mode capacitance C6, common mode capacitance C3, common mode capacitance C4, common mode capacitance C7, common mode capacitance C8.
An ideal diode or gate control circuit comprising: the diode comprises an ideal diode controller U1, an ideal diode controller U2, an N-channel field effect transistor S1, an N-channel field effect transistor S2, an N-channel field effect transistor S3, an N-channel field effect transistor S4, a transient voltage suppression diode D1, a transient voltage suppression diode D2, a gate driving resistor R1, a gate driving resistor R2, a gate driving resistor R4, a gate driving resistor R5, a current limiting resistor R3, a current limiting resistor R6, a filter capacitor C9 and a filter capacitor C10.
An optical MOS+magnetic latching relay control circuit, comprising: the photo MOS relay JG1, the magnetic latching relay JB1, the rectifying diode D3, the rectifying diode D4, the rectifying diode D5, the rectifying diode D6, the freewheel diode D7, the freewheel diode D8, the current limiting resistor R7, the current limiting resistor R8, the current limiting resistor R9, the current limiting resistor R10, the filter capacitor C11 and the filter capacitor C12.
The P-channel MOS parallel switching main circuit comprises a P-channel field effect transistor S5, a P-channel field effect transistor S6, a P-channel field effect transistor S7, a P-channel field effect transistor S8, a voltage stabilizing diode D9, an energy storage filter capacitor C13, a voltage dividing resistor R11, a voltage dividing resistor R12, a gate driving resistor R13, a gate driving resistor R14, a gate driving resistor R15 and a gate driving resistor R16.
The output end of the input EMI filter circuit is connected with the input end of the ideal diode or the gate control circuit, one path of the output end of the ideal diode or the gate control circuit is connected with the input end of the P-channel MOS parallel switching main circuit, the other path of the output end of the input EMI filter circuit is connected with the output end of the input EMI filter circuit, and the output end of the optical MOS+magnetic latching relay control circuit is connected with the input end of the P-channel MOS parallel switching main circuit.
In the input EMI filter circuit, in a first branch, an input positive end of a common-mode inductor L1 is connected to an input high end Va1, one end of a differential-mode capacitor C1 is connected to the input high end Va1, the other end of the differential-mode capacitor C1 is connected to an input negative end of the common-mode inductor L1, an output positive end of the common-mode inductor L1 is connected to one end of a differential-mode inductor L2 and one end of the differential-mode capacitor C2, the other end of the differential-mode capacitor C2 is connected to an output negative end of the common-mode inductor L1, the other end of the differential-mode inductor L2 is connected to one end of a common-mode capacitor C3 and an output high end Vb1, the other end of the common-mode capacitor C3 is connected to one end of a casing ground and the common-mode capacitor C4, and the other end of the common-mode capacitor C4 is connected to the output negative end of the common-mode inductor L1. In the second path, the input positive end of the common-mode inductor L3 is connected with the input high end Va2, one end of the differential-mode capacitor C5 is connected with the input high end Va2, the other end of the differential-mode capacitor C5 is connected with the input negative end of the common-mode inductor L3, the output positive end of the common-mode inductor L3 is connected with one end of the differential-mode inductor L4 and one end of the differential-mode capacitor C6 respectively, the other end of the differential-mode inductor C6 is connected with the output negative end of the common-mode inductor L3, the other end of the differential-mode inductor L4 is connected with one end of the common-mode capacitor C7 and the output high end Vb2 respectively, and the other end of the common-mode capacitor C7 is connected with the ground of the casing and one end of the common-mode capacitor C8 respectively, and the other end of the common-mode capacitor C8 is connected with the output negative end of the common-mode inductor L3. The negative output end of the common-mode inductor L1 is connected with the negative output end of the common-mode inductor L3.
IN the ideal diode or GATE control circuit, IN the first branch, the cathode of the transient suppression diode D1 is connected to the input high terminal Vb1, the anode of the transient suppression diode D1 is connected to the Vss terminal of the ideal diode controller U1, the IN terminal of the ideal diode controller U1 is connected to the input high terminal Vb1, the SOURCE terminal of the N-channel field effect transistor S2, the GATE of the N-channel field effect transistor S1 is connected to one terminal of the GATE driving resistor R1, the GATE of the N-channel field effect transistor S2 is connected to one terminal of the GATE driving resistor R2, the other terminal of the GATE driving resistor R1 is connected to the other terminal of the GATE driving resistor R2, the GATE terminal of the ideal diode controller U1, the drain terminal of the N-channel field effect transistor S1 is connected to the drain terminal of the N-channel field effect transistor S2, the OUT terminal of the ideal diode controller U1, one terminal of the current limiting resistor R3, the other terminal of the output high terminal of the current limiting resistor R3, and the other terminal of the current limiting resistor R3 are connected to the other terminal of the ideal diode controller U9, and the filter capacitor C9 of the ideal diode is connected to one terminal of the filter capacitor C1. IN the second path, the cathode of the transient suppression diode D2 is connected to the input high terminal Vb2, the anode of the transient suppression diode D2 is connected to the Vss terminal of the ideal diode controller U2, the IN terminal of the ideal diode controller U2 is connected to the input high terminal Vb2, the SOURCE terminal of the N-channel field effect transistor S3, and the SOURCE terminal of the N-channel field effect transistor S4, the GATE of the N-channel field effect transistor S3 is connected to one terminal of the GATE driving resistor R4, the GATE of the N-channel field effect transistor S4 is connected to one terminal of the GATE driving resistor R5, the other terminal of the GATE driving resistor R4 is connected to the other terminal of the GATE driving resistor R5, the GATE terminal of the ideal diode controller U2, the drain terminal of the N-channel field effect transistor S3 is connected to the drain terminal of the N-channel field effect transistor S4, the OUT terminal of the ideal diode controller U2, one terminal of the current limiting resistor R6, and the output high terminal Ve, and the other terminal of the current limiting resistor R6 are connected to one terminal of the ideal diode controller U2, and the capacitor C10 is connected to the other terminal of the ideal diode 2, and the capacitor C10 is connected to the other terminal of the filter Vss.
In the 'photo MOS+magnetic latching' relay control circuit, an output high end Vd is respectively connected with a contact K1-1 end of a magnetic latching relay JB1 and a contact K2-1 end of the magnetic latching relay JB1, the contact K1-1 end of the magnetic latching relay JB1 is connected with a contact K1-2 end of the magnetic latching relay JB1 and a signal ground, the contact K2-1 end of the magnetic latching relay JB1 is connected with a contact K2-2 end of the magnetic latching relay JB1 and the signal ground, and the contacts K1-3 and K2-3 of the magnetic latching relay JB1 are respectively suspended; the coil control end 1IN+ of the magnetic latching relay JB1 is respectively connected with one end of a current limiting resistor R7 and the cathode of a freewheeling diode D8, the coil control end 2IN+ of the magnetic latching relay JB1 is respectively connected with one end of the current limiting resistor R8 and the cathode of the freewheeling diode D7, the other end of the current limiting resistor R7 is respectively connected with the cathode of a rectifying diode D3 and the cathode of a rectifying diode D4, the other end of the current limiting resistor R8 is respectively connected with the cathode of a rectifying diode D5 and the cathode of a rectifying diode D6, the anode of the rectifying diode D3 is connected with the anode of the rectifying diode D5 and the input Vb1 end, the anode of the rectifying diode D4 is connected with the anode of the rectifying diode D6 and the input Vb2 end, the anode of the freewheeling diode D7 is connected with the coil control end 2IN-, the output 2OUT+ end of the photo MOS relay JG1 of the magnetic latching relay JB1, and the anode of the freewheeling diode D8 is connected with the coil control end 1IN-, the output 1OUT+ end of the photo MOS relay JG1 of the magnetic latching relay JB 1; the output 1 OUT-end of the photo MOS relay JG1 is connected with the output 2 OUT-end of the photo MOS relay JG1 and signal ground; one end of the current limiting resistor R9 is connected with a control signal Ctrl-ON+ end, the other end of the current limiting resistor R9 is connected with one end of a filter capacitor C11, the other end of the filter capacitor C11 is connected with a control signal Ctrl-ON-end, the input control end 1 IN-of the light MOS relay JG1, one end of the current limiting resistor R10 is connected with a control signal Ctrl-OFF+ end, the other end of the current limiting resistor R10 is connected with one end of a filter capacitor C12, the input control end 2IN+ of the light MOS relay JG1, and the other end of the filter capacitor C12 is connected with the control signal Ctrl-OFF-end and the input control end 2 IN-of the light MOS relay JG 1.
In the P-channel MOS parallel switching main circuit, an input high end Vc is respectively connected with a cathode of a voltage stabilizing diode D9, one end of a voltage dividing resistor R11, one end of a storage filter capacitor C13, a source of a P-channel field effect transistor S5, a source of a P-channel field effect transistor S6, a source of a P-channel field effect transistor S7 and a source of a P-channel field effect transistor S8, an anode of the voltage stabilizing diode D9 is respectively connected with the other end of the voltage dividing resistor R11, one end of the voltage dividing resistor R12, the other end of the storage filter capacitor C13, one end of a gate driving resistor R14, one end of a gate driving resistor R15 and one end of a gate driving resistor R16, the other end of the gate driving resistor R13 is connected with a gate of the P-channel field effect transistor S5, the other end of the gate driving resistor R14 is connected with a gate of the P-channel field effect transistor S6, the other end of the gate driving resistor R15 is connected with a gate of the P-channel field effect transistor S7, the other end of the gate driving resistor R16 is connected with a gate of the P-channel field effect transistor S8, and the drain of the P-channel field effect transistor S6 is respectively connected with the drain electrode of the drain of the P-channel field effect transistor S8.
When the double-circuit redundant power supply autonomous switching and recovering circuit works, the sprung battery power supply Va1 and the ground power supply Va2 respectively enter the input EMI filter circuit 1a and the input EMI filter circuit 1b to carry out input common mode signal and differential mode signal filtering. The EMI filter circuit filters external electromagnetic interference introduced on the incoming line on one hand, and suppresses the electromagnetic interference emitted to the outside by the high-frequency signal circuit on the other hand, so as not to influence the normal operation of other electronic equipment in the same electromagnetic environment. The sprung battery power supply Va1 outputs a voltage Vb1 through the input EMI filter circuit 1a, and the ground power supply Va2 outputs a voltage Vb2 through the input EMI filter circuit 1 b.
The output voltages Vb1 and Vb2 of the EMI input filter circuit are respectively sent to an ideal diode or GATE control circuit, the ideal diode controller U1 keeps the voltage between GATE and SOURCE pins about 12V through detection of the input voltage Vb1 and charge pumping, and the N-channel field effect transistor S1 and the N-channel field effect transistor S2 are respectively driven to be saturated and conducted through the GATE driving resistor R1 and the GATE driving resistor R2, and then output Vc. The ideal diode controller U1 adjusts and controls the on-resistance of the N-channel field effect transistor S1 and the N-channel field effect transistor S2 by detecting the voltage difference between the IN end and the OUT end of the ideal diode controller U, so that the low voltage drop of the circuit is ensured. Similarly, the ideal diode controller U2 keeps the voltage between GATE and SOURCE pins at about 12V by detecting the input voltage Vb2 and by the charge pump, and drives the N-channel field effect transistor S3 and the N-channel field effect transistor S4 to be saturated and turned on respectively through the GATE driving resistor R4 and the GATE driving resistor R5, and then outputs Ve. The parallel connection of the N-channel field effect transistor S1 and the N-channel field effect transistor S2 and the parallel connection of the N-channel field effect transistor S3 and the N-channel field effect transistor S4 in the circuit can increase the current carrying capacity of each branch, reduce the voltage drop of the circuit and automatically balance the current so as to improve the reliability.
In the 'photo MOS+magnetic latching' relay control circuit, a coil control end J1 and a coil control end J2 of a magnetic latching relay JB1 are respectively pulled up to direct current input voltages Vb1 and Vb2 through a current limiting resistor R7 and a current limiting resistor R8, and a rectifying diode D3, a rectifying diode D4, a rectifying diode D5 and a rectifying diode D6 play roles in isolation and clamping. The freewheel diode D7 and the freewheel diode D8 are respectively connected in anti-parallel to the two ends of the coil control end J2 and the coil control end J1 of the magnetic latching relay JB1, so that the reverse peak electromotive force of the coil can be eliminated, and the electromagnetic radiation interference can be reduced. The output ends 1OUT and 2OUT of the photo MOS relay JG1 are respectively connected with a coil control end J1 and a coil control end J2 of the control magnetic latching relay JB1, an input control signal Ctrl-ON is connected with an input control end 1IN of the photo MOS relay JG1 after passing through a current limiting resistor R9 and a filter capacitor C11,
the input control signal Ctrl-OFF is connected with the input control end 2IN of the photo MOS relay JG1 after passing through the current limiting resistor R10 and the filter capacitor C12. The magnetic latching relay has the initial state of rear excitation that the end of a contact K1-1 is connected with the end of a contact K1-2, the end of the contact K2-1 is connected with the end of the contact K2-2, and at the moment, an input Vd is pulled to the ground level; when the input control signal Ctrl-OFF is 200mS high pulse level effective, the coil control end J2 of the magnetic latching relay JB1 is powered on, the contact state of the magnetic latching relay is overturned, the contact K1-1 end is connected with the contact K1-3 end, the contact K2-1 end is connected with the contact K2-3 end, and the input Vd is suspended at the moment; when the input control signal Ctrl-ON is 200mS high pulse level effective, the coil control end J1 of the magnetic latching relay JB1 is powered ON, the contact state of the magnetic latching relay is turned over again to be restored to the back excitation initial state, the contact K1-1 end is connected with the contact K1-2 end, the contact K2-1 end is connected with the contact K2-2 end, and the input Vd is pulled to the ground level at the moment. The two groups of contacts K1 and K2 of the magnetic latching relay adopt a parallel redundancy design, so that the reliability of a control system can be improved.
In the 'P-channel MOS parallel switching main circuit', input voltage Vc is divided and limited by a voltage dividing resistor R11 and a voltage dividing resistor R12, and then is sent to a P-channel field effect transistor S5, a P-channel field effect transistor S6, a P-channel field effect transistor S7 and a P-channel field effect transistor S8 after being subjected to voltage stabilizing and pressure filtering by a voltage stabilizing diode D9 and an energy storage filter capacitor C13, so that the gate-source voltages of the P-channel field effect transistor S7 and the P-channel field effect transistor S8 are controlled to be turned on and off. When the input Vd is pulled to the ground level, the P-channel field effect transistor S5, the P-channel field effect transistor S6, the P-channel field effect transistor S7 and the P-channel field effect transistor S8 are turned on, and when the input Vd is suspended, the P-channel field effect transistor S5, the P-channel field effect transistor S6, the P-channel field effect transistor S7 and the P-channel field effect transistor S8 are turned off.
When the device is subjected to ground test, the battery power supply Va1 and the ground power supply Va2 are effective at the same time, after the input EMI filter circuit and the ideal diode or the gate control circuit, the ground power supply Va2 directly supplies power to the output voltage Ve, and the battery power supply Va1 is switched to the main circuit through the P-channel MOS in parallel and then supplies power to the output voltage Ve. When the voltage of the battery power supply Va1 is larger than the voltage of the ground power supply Va2, the output voltage Ve is supplied to the back-end equipment by the battery power supply Va1, and when the voltage of the battery power supply Va1 is smaller than the voltage of the ground power supply Va2, the output voltage Ve is supplied to the back-end equipment by the ground power supply Va 2. When the battery supply Va1 voltage is equal to the ground supply Va2 voltage, the output voltage Ve is supplied to the backend device by both the battery supply Va1 and the ground supply Va 2.
When the device performs a suspension flight test, the battery power Va1 is switched to the main circuit in parallel through the P-channel MOS at the initial state and then is supplied to the output voltage Ve, and after the test is finished, the input control signal Ctrl-OFF is effective,
the states of two groups of contacts K1 and K2 of the magnetic latching relay JB1 are overturned, the input Vd is suspended, the P-channel field effect transistor is cut off, the output power supply Ve is cut off, and the power supply of the rear-end equipment realizes the self-cutting function.
When the equipment returns to the ground, the ground power supply Va2 is effective, the ground power supply Va2 directly supplies power to the output voltage Ve for supplying power to the rear-end equipment, the input control signal Ctrl-ON is effective, the states of the two groups of contacts K1 and K2 of the magnetic latching relay JB1 are turned over and reset, the input Vd is pulled to the ground level, the P-channel field effect transistor is conducted, and the power supply state of the output voltage Ve is restored to the state that the battery power supply Va1 and the ground power supply Va2 are simultaneously powered.
The invention adopts an ideal diode or gate control circuit and a photo MOS and magnetic latching relay control circuit to control the on and off of a P channel MOS parallel switching main circuit, realizes the automatic switching and recovery functions of double-path redundant power supply, and has the characteristics of small volume, low line voltage drop and heat power consumption, low EMI electromagnetic interference, strong vibration stress resistance, reliable control and the like.
Example 1
A dual redundant power supply autonomous switching and restoration circuit comprising: the input EMI filter circuit, the ideal diode or the gate control circuit, the photo MOS and magnetic latching relay control circuit and the P channel MOS parallel switching main circuit. Wherein the input EMI filter circuit comprises: common mode inductance L1, common mode inductance L2, differential mode inductance L4, differential mode capacitance C1, differential mode capacitance C2, differential mode capacitance C5, differential mode capacitance C6, common mode capacitance C3, common mode capacitance 4, common mode capacitance C7, common mode capacitance C8. An ideal diode or gate control circuit comprising: the diode comprises an ideal diode controller U1, an ideal diode controller U2, an N-channel field effect transistor S1, an N-channel field effect transistor S2, an N-channel field effect transistor S3, an N-channel field effect transistor S4, a transient voltage suppression diode D1, a transient voltage suppression diode D2, a gate driving resistor R1, a gate driving resistor R2, a gate driving resistor R4, a gate driving resistor R5, a current limiting resistor R3, a current limiting resistor R6, a filter capacitor C9 and a filter capacitor C10. An optical MOS+magnetic latching relay control circuit, comprising: the photo MOS relay JG1, the magnetic latching relay JB1, the rectifying diode D3, the rectifying diode D4, the rectifying diode D5, the rectifying diode D6, the freewheel diode D7, the freewheel diode D8, the current limiting resistor R7, the current limiting resistor R8, the current limiting resistor R9, the current limiting resistor R10, the filter capacitor C11 and the filter capacitor C12. The P-channel MOS parallel switching main circuit comprises a P-channel field effect transistor S5, a P-channel field effect transistor S6, a P-channel field effect transistor S7, a P-channel field effect transistor S8, a voltage stabilizing diode D9, an energy storage filter capacitor C13, a voltage dividing resistor R11, a voltage dividing resistor R12, a gate driving resistor R13, a gate driving resistor R14, a gate driving resistor R15 and a gate driving resistor R16.
The output end of the input EMI filter circuit is connected with the input end of the ideal diode or the gate control circuit, one path of the output end of the ideal diode or the gate control circuit is connected with the input end of the P-channel MOS parallel switching main circuit, the other path of the output end of the input EMI filter circuit is connected with the output end of the input EMI filter circuit, and the output end of the optical MOS+magnetic latching relay control circuit is connected with the input end of the P-channel MOS parallel switching main circuit.
In the input EMI filter circuit, in a first branch, an input positive end of a common-mode inductor L1 is connected to an input high end Va1, one end of a differential-mode capacitor C1 is connected to the input high end Va1, the other end of the differential-mode capacitor C1 is connected to an input negative end of the common-mode inductor L1, an output positive end of the common-mode inductor L1 is connected to one end of a differential-mode inductor L2 and one end of the differential-mode capacitor C2, the other end of the differential-mode capacitor C2 is connected to an output negative end of the common-mode inductor L1, the other end of the differential-mode inductor L2 is connected to one end of a common-mode capacitor C3 and an output high end Vb1, the other end of the common-mode capacitor C3 is connected to one end of a casing ground and the common-mode capacitor C4, and the other end of the common-mode capacitor C4 is connected to the output negative end of the common-mode inductor L1. In the second path, the input positive end of the common-mode inductor L3 is connected with the input high end Va2, one end of the differential-mode capacitor C5 is connected with the input high end Va2, the other end of the differential-mode capacitor C5 is connected with the input negative end of the common-mode inductor L3, the output positive end of the common-mode inductor L3 is connected with one end of the differential-mode inductor L4 and one end of the differential-mode capacitor C6 respectively, the other end of the differential-mode inductor C6 is connected with the output negative end of the common-mode inductor L3, the other end of the differential-mode inductor L4 is connected with one end of the common-mode capacitor C7 and the output high end Vb2 respectively, and the other end of the common-mode capacitor C7 is connected with the ground of the casing and one end of the common-mode capacitor C8 respectively, and the other end of the common-mode capacitor C8 is connected with the output negative end of the common-mode inductor L3. The negative output end of the common-mode inductor L1 is connected with the negative output end of the common-mode inductor L3.
IN the ideal diode or GATE control circuit, IN the first branch, the cathode of the transient suppression diode D1 is connected to the input high terminal Vb1, the anode of the transient suppression diode D1 is connected to the Vss terminal of the ideal diode controller U1, the IN terminal of the ideal diode controller U1 is connected to the input high terminal Vb1, the SOURCE terminal of the N-channel field effect transistor S2, the GATE of the N-channel field effect transistor S1 is connected to one terminal of the GATE driving resistor R1, the GATE of the N-channel field effect transistor S2 is connected to one terminal of the GATE driving resistor R2, the other terminal of the GATE driving resistor R1 is connected to the other terminal of the GATE driving resistor R2, the GATE terminal of the ideal diode controller U1, the drain terminal of the N-channel field effect transistor S1 is connected to the drain terminal of the N-channel field effect transistor S2, the OUT terminal of the ideal diode controller U1, one terminal of the current limiting resistor R3, the other terminal of the output high terminal of the current limiting resistor R3, and the other terminal of the current limiting resistor R3 are connected to the other terminal of the ideal diode controller U9, and the filter capacitor C9 of the ideal diode is connected to one terminal of the filter capacitor C1. IN the second path, the cathode of the transient suppression diode D2 is connected to the input high terminal Vb2, the anode of the transient suppression diode D2 is connected to the Vss terminal of the ideal diode controller U2, the IN terminal of the ideal diode controller U2 is connected to the input high terminal Vb2, the SOURCE terminal of the N-channel field effect transistor S3, and the SOURCE terminal of the N-channel field effect transistor S4, the GATE of the N-channel field effect transistor S3 is connected to one terminal of the GATE driving resistor R4, the GATE of the N-channel field effect transistor S4 is connected to one terminal of the GATE driving resistor R5, the other terminal of the GATE driving resistor R4 is connected to the other terminal of the GATE driving resistor R5, the GATE terminal of the ideal diode controller U2, the drain terminal of the N-channel field effect transistor S3 is connected to the drain terminal of the N-channel field effect transistor S4, the OUT terminal of the ideal diode controller U2, one terminal of the current limiting resistor R6, and the output high terminal Ve, and the other terminal of the current limiting resistor R6 are connected to one terminal of the ideal diode controller U2, and the capacitor C10 is connected to the other terminal of the ideal diode 2, and the capacitor C10 is connected to the other terminal of the filter Vss.
IN the 'photo MOS+magnetic latching' relay control circuit, an input high end Vd is respectively connected with a contact K1-1 end of a magnetic latching relay JB1 and a contact K2-1 end of the magnetic latching relay JB1, the contact K1-1 end of the magnetic latching relay JB1 is connected with a contact K2-2 end of the magnetic latching relay JB1 and a signal ground, contacts K1-3 and K2-3 of the magnetic latching relay JB1 are respectively suspended, a coil control end 1IN+ of the magnetic latching relay JB1 is respectively connected with one end of a current limiting resistor R7 and a cathode of a freewheeling diode D8, a coil control end 2IN+ of the magnetic latching relay JB1 is respectively connected with one end of a current limiting resistor R8 and a cathode of a freewheeling diode D7, the other end of the current limiting resistor R7 is respectively connected with a cathode of a rectifying diode D3 and a cathode of a rectifying diode D4, the other end of the current limiting resistor R8 is respectively connected with a cathode of a rectifying diode D5 and a cathode of a rectifying diode D6, the anode of the rectifying diode D3 is connected with the anode of the rectifying diode D5 and the input Vb1 end, the anode of the rectifying diode D4 is connected with the anode of the rectifying diode D6 and the input Vb2 end, the anode of the freewheeling diode D7 is connected with the coil control end 2 IN-of the magnetic latching relay JB1, the output 2OUT+ end of the photo MOS relay JG1, the anode of the freewheeling diode D8 is connected with the coil control end 1 IN-of the magnetic latching relay JB1, the output 1OUT+ end of the photo MOS relay JG1, the output 1 OUT-end of the photo MOS relay JG1 is connected with the output 2 OUT-end of the photo MOS relay JG1 and the signal ground, one end of the current limiting resistor R9 is connected with the control signal Ctrl-ON+ end, the other end of the current limiting resistor R9 is connected with one end of the filter capacitor C11, the other end of the filter capacitor C11 is connected with the control signal Ctrl-ON-end, one end of a current limiting resistor R10 is connected with a control signal Ctrl-OFF+ end, the other end of the current limiting resistor R10 is connected with one end of a filter capacitor C12, an input control end 2IN+ of the photo MOS relay JG1, and the other end of the filter capacitor C12 is connected with a control signal Ctrl-OFF-end and an input control end 2 IN-of the photo MOS relay JG 1.
In the P-channel MOS parallel switching main circuit, an input high end Vc is respectively connected with a cathode of a voltage stabilizing diode D9, one end of a voltage dividing resistor R11, one end of a storage filter capacitor C13, a source of a P-channel field effect transistor S5, a source of a P-channel field effect transistor S6, a source of a P-channel field effect transistor S7 and a source of a P-channel field effect transistor S8, an anode of the voltage stabilizing diode D9 is respectively connected with the other end of the voltage dividing resistor R11, one end of the voltage dividing resistor R12, the other end of the storage filter capacitor C13, one end of a gate driving resistor R14, one end of a gate driving resistor R15 and one end of a gate driving resistor R16, the other end of the gate driving resistor R13 is connected with a gate of the P-channel field effect transistor S5, the other end of the gate driving resistor R14 is connected with a gate of the P-channel field effect transistor S6, the other end of the gate driving resistor R15 is connected with a gate of the P-channel field effect transistor S7, the other end of the gate driving resistor R16 is connected with a gate of the P-channel field effect transistor S8, and the drain of the P-channel field effect transistor S6 is respectively connected with the drain electrode of the drain of the P-channel field effect transistor S8.
When the double-circuit redundant power supply autonomous switching and recovering circuit works, the sprung battery power supply Va1 and the ground power supply Va2 respectively enter the input EMI filter circuit 1a and the input EMI filter circuit 1b to carry out input two-stage common mode signal and differential mode signal filtering. In the input EMI filter circuit 1a, the common-mode inductance L1, the differential-mode capacitance C1 and the differential-mode capacitance C2 form a first-stage common-mode differential-mode signal filter circuit, the differential-mode inductance L2, the common-mode capacitance C3 and the common-mode capacitance C4 form a second-stage common-mode differential-mode signal filter circuit, and the input voltage Va1 is output by the input EMI filter circuit 1 a; in the input EMI filter circuit 1b, the common-mode inductance L3, the differential-mode capacitance C5 and the differential-mode capacitance C6 form a first-stage common-mode differential-mode signal filter circuit, the differential-mode inductance L4, the common-mode capacitance C7 and the common-mode capacitance C8 form a second-stage common-mode differential-mode signal filter circuit, and the input voltage Va2 is output by the input EMI filter circuit 1 b.
Output voltages Vb1 and Vb2 of the EMI input filter circuit are supplied to the ideal diode or gate control circuit 2a and the ideal diode control circuit 2b, respectively. In the ideal diode or GATE control circuit 2a, the ideal diode controller U1 detects the input voltage Vb1 and keeps the voltage between the GATE and SOURCE pins at about 12V under the charge pump action, and drives the N-channel field effect transistor S1 and the N-channel field effect transistor S2 to be saturated and turned on respectively through the GATE driving resistor R1 and the GATE driving resistor R2, and then outputs Vc. The ideal diode controller U1 adjusts and controls the on-resistances of the N-channel field effect transistor S1 and the N-channel field effect transistor S2 by detecting the voltage difference between the IN terminal and the OUT terminal thereof. When the voltage difference is smaller than a certain value (tens mV), the gate-source driving voltage is reduced so as to improve the on-resistance; when the voltage is larger than a certain value (tens mV), the gate-source driving voltage is increased so as to reduce the on-resistance; when a reverse voltage drop occurs, the gate-source drive voltage is immediately turned off. By dynamic feedback regulation, it is ensured that the voltage drop (tens of mV) is kept low when the line is conducting. Similarly, the ideal diode controller U2 keeps the voltage between GATE and SOURCE pins at about 12V by detecting the input voltage Vb2 and by the charge pump, and drives the N-channel field effect transistor S3 and the N-channel field effect transistor S4 to be saturated and turned on respectively through the GATE driving resistor R4 and the GATE driving resistor R5, and then outputs Ve. The parallel connection of the N-channel field effect transistor S1 and the N-channel field effect transistor S2 and the parallel connection of the N-channel field effect transistor S3 and the N-channel field effect transistor S4 in the circuit can increase the current carrying capacity of each branch circuit, reduce the voltage drop of the circuit, and automatically balance the current to improve the reliability.
In the 'photo MOS+magnetic latching' relay control circuit, a coil control end J1 and a coil control end J2 of a magnetic latching relay JB1 are respectively pulled up to direct current input voltages Vb1 and Vb2 through a current limiting resistor R7 and a current limiting resistor R8, and a rectifying diode D3, a rectifying diode D4, a rectifying diode D5 and a rectifying diode D6 play roles in isolation and clamping. The freewheel diode D7 is reversely connected in parallel with the coil control end J2 of the magnetic latching relay JB1
And the flywheel diode D8 is reversely connected IN parallel with the 1IN+ and 1IN-ends of the coil control end J1 of the magnetic latching relay JB1, so that the reverse peak electromotive force of the coil control end J1 and the coil control end J2 can be eliminated, and the electromagnetic radiation interference can be reduced. The output ends 1OUT and 2OUT of the photo MOS relay JG1 are respectively connected with a coil control end J1 and a coil control end J2 of the control magnetic latching relay JB1, an input control signal Ctrl-ON is connected with the input control end 1IN of the photo MOS relay JG1 after passing through a current limiting resistor R9 and a filter capacitor C11, and the input control signal Ctrl-OFF is connected with the input control end 2IN of the photo MOS relay JG1 after passing through a current limiting resistor R10 and a filter capacitor C12. The magnetic latching relay has the initial state of rear excitation that the end of a contact K1-1 is connected with the end of a contact K1-2, the end of the contact K2-1 is connected with the end of the contact K2-2, and at the moment, an input Vd is pulled to the ground level; when the input control signal Ctrl-OFF is 200mS high pulse level effective, the coil control end J2 of the magnetic latching relay JB1 is powered on, the contact state of the magnetic latching relay is overturned, the contact K1-1 end is connected with the contact K1-3 end, the contact K2-1 end is connected with the contact K2-3 end, and the input Vd is suspended at the moment; when the input control signal Ctrl-ON is 200mS high pulse level effective, the coil control end J1 of the magnetic latching relay JB1 is powered ON, the contact state of the magnetic latching relay is turned over again to be restored to the back excitation initial state, the contact K1-1 end is connected with the contact K1-2 end, the contact K2-1 end is connected with the contact K2-2 end, and the input Vd is pulled to the ground level at the moment. The two groups of contacts K1 and K2 of the magnetic latching relay adopt a parallel redundancy design, so that the reliability of a control system can be improved.
In the 'P-channel MOS parallel switching main circuit', input voltage Vc is divided and limited by a voltage dividing resistor R11 and a voltage dividing resistor R12, and then is sent to a P-channel field effect transistor S5, a P-channel field effect transistor S6, a P-channel field effect transistor S7 and a P-channel field effect transistor S8 after being subjected to voltage stabilizing and pressure filtering by a voltage stabilizing diode D9 and an energy storage filter capacitor C13, so that the gate-source voltages of the P-channel field effect transistor S7 and the P-channel field effect transistor S8 are controlled to be turned on and off. When the input voltage Vc is high and the input Vd is pulled to the ground level, the voltage difference between two ends of the voltage stabilizing diode D9 is 12V, at the moment, the gate source voltages of the P-channel field effect transistor S5, the P-channel field effect transistor S6, the P-channel field effect transistor S7 and the P-channel field effect transistor S8 are-12V, the source and drain electrodes of the P-channel field effect transistor S5, the P-channel field effect transistor S6, the P-channel field effect transistor S7 and the P-channel field effect transistor S8 are respectively conducted, and when the input Vd is suspended, the voltage difference between two ends of the voltage stabilizing diode D9 is 0V, and the source and drain electrodes of the P-channel field effect transistor S5, the P-channel field effect transistor S6, the P-channel field effect transistor S7 and the P-channel field effect transistor S8 are cut off. The parallel design of the P-channel field effect transistor S5, the P-channel field effect transistor S6, the P-channel field effect transistor S7 and the P-channel field effect transistor S8 can increase the current carrying capacity, reduce the line conduction voltage drop, and automatically balance the current to improve the reliability.
When the device is subjected to ground test, the battery power supply Va1 and the ground power supply Va2 are effective at the same time, after the input EMI filter circuit and the ideal diode or the gate control circuit, the ground power supply Va2 directly supplies power to the output voltage Ve, and the battery power supply Va1 is switched to the main circuit through the P-channel MOS in parallel and then supplies power to the output voltage Ve. When the voltage of the battery power supply Va1 is larger than the voltage of the ground power supply Va2, the output voltage Ve is supplied to the back-end equipment by the battery power supply Va1, and when the voltage of the battery power supply Va1 is smaller than the voltage of the ground power supply Va2, the output voltage Ve is supplied to the back-end equipment by the ground power supply Va 2. When the battery supply Va1 voltage is equal to the ground supply Va2 voltage, the output voltage Ve is supplied to the backend device by both the battery supply Va1 and the ground supply Va 2.
When the device performs a suspension flight test, the battery power Va1 is switched to the main circuit in parallel through the P-channel MOS at the initial state and then is supplied to the output voltage Ve, and after the test is finished, the input control signal Ctrl-OFF is effective,
the states of two groups of contacts K1 and K2 of the magnetic latching relay JB1 are overturned, the input Vd is suspended, the P-channel field effect transistor is cut off, the output power supply Ve is cut off, and the power supply of the rear-end equipment realizes the self-cutting function.
When the equipment returns to the ground, the ground power supply Va2 is effective, the ground power supply Va2 directly supplies power to the output voltage Ve for supplying power to the rear-end equipment, the input control signal Ctrl-ON is effective, the states of the two groups of contacts K1 and K2 of the magnetic latching relay JB1 are turned over and reset, the input Vd is pulled to the ground level, the P-channel field effect transistor is conducted, and the power supply state of the output voltage Ve is restored to the state that the battery power supply Va1 and the ground power supply Va2 are simultaneously powered.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and variations should also be regarded as being within the scope of the invention.

Claims (6)

1. The double-path redundant power supply self-cutting and recovering circuit is characterized by comprising an input EMI filter circuit, an ideal diode or gate control circuit, a photo MOS+magnetic latching relay control circuit, a P-channel MOS parallel switching main circuit, wherein the output end of the input EMI filter circuit is connected with the input end of the ideal diode or gate control circuit, one path of the output end of the ideal diode or gate control circuit is connected with the input end of the P-channel MOS parallel switching main circuit, the other path of the output end of the ideal diode or gate control circuit is connected with the output end of the P-channel MOS parallel switching main circuit, the input end of the photo MOS+magnetic latching relay control circuit is connected with the output end of the input EMI filter circuit, and the output end of the photo MOS+magnetic latching relay control circuit is connected with the input end of the P-channel MOS parallel switching main circuit;
wherein,,
an optical MOS+magnetic latching relay control circuit, comprising: the photo MOS relay JG1, the magnetic latching relay JB1, the rectifying diode D3, the rectifying diode D4, the rectifying diode D5, the rectifying diode D6, the freewheel diode D7, the freewheel diode D8, the current limiting resistor R7, the current limiting resistor R8, the current limiting resistor R9, the current limiting resistor R10, the filter capacitor C11 and the filter capacitor C12;
In the 'photo MOS+magnetic latching' relay control circuit, an output high end Vd is respectively connected with a contact K1-1 end of a magnetic latching relay JB1 and a contact K2-1 end of the magnetic latching relay JB1, the contact K1-1 end of the magnetic latching relay JB1 is connected with a contact K1-2 end of the magnetic latching relay JB1 and a signal ground, the contact K2-1 end of the magnetic latching relay JB1 is connected with a contact K2-2 end of the magnetic latching relay JB1 and the signal ground, and the contacts K1-3 and K2-3 of the magnetic latching relay JB1 are respectively suspended; the coil control end 1IN+ of the magnetic latching relay JB1 is respectively connected with one end of a current limiting resistor R7 and the cathode of a freewheeling diode D8, the coil control end 2IN+ of the magnetic latching relay JB1 is respectively connected with one end of the current limiting resistor R8 and the cathode of the freewheeling diode D7, the other end of the current limiting resistor R7 is respectively connected with the cathode of a rectifying diode D3 and the cathode of a rectifying diode D4, the other end of the current limiting resistor R8 is respectively connected with the cathode of a rectifying diode D5 and the cathode of a rectifying diode D6, the anode of the rectifying diode D3 is connected with the anode of the rectifying diode D5 and the input Vb1 end, the anode of the rectifying diode D4 is connected with the anode of the rectifying diode D6 and the input Vb2 end, the anode of the freewheeling diode D7 is connected with the coil control end 2IN-, the output 2OUT+ end of the photo MOS relay JG1 of the magnetic latching relay JB1, and the anode of the freewheeling diode D8 is connected with the coil control end 1IN-, the output 1OUT+ end of the photo MOS relay JG1 of the magnetic latching relay JB 1; the output 1 OUT-end of the photo MOS relay JG1 is connected with the output 2 OUT-end of the photo MOS relay JG1 and signal ground; one end of a current limiting resistor R9 is connected with a control signal Ctrl-ON+ end, the other end of the current limiting resistor R9 is connected with one end of a filter capacitor C11, the other end of the filter capacitor C11 is connected with a control signal Ctrl-ON-end and an input control end 1 IN-of the photo MOS relay JG1, one end of a current limiting resistor R10 is connected with a control signal Ctrl-OFF+ end, the other end of the current limiting resistor R10 is connected with one end of a filter capacitor C12, the input control end 2IN+ of the photo MOS relay JG1, and the other end of the filter capacitor C12 is connected with the control signal Ctrl-OFF-end and an input control end 2 IN-of the photo MOS relay JG 1;
The P-channel MOS parallel switching main circuit comprises a P-channel field effect transistor S5, a P-channel field effect transistor S6, a P-channel field effect transistor S7, a P-channel field effect transistor S8, a voltage stabilizing diode D9, an energy storage filter capacitor C13, a divider resistor R11, a divider resistor R12, a gate driving resistor R13, a gate driving resistor R14, a gate driving resistor R15 and a gate driving resistor R16;
in the P-channel MOS parallel switching main circuit, an input high end Vc is respectively connected with a cathode of a voltage stabilizing diode D9, one end of a voltage dividing resistor R11, one end of a storage filter capacitor C13, a source of a P-channel field effect transistor S5, a source of a P-channel field effect transistor S6, a source of a P-channel field effect transistor S7 and a source of a P-channel field effect transistor S8, an anode of the voltage stabilizing diode D9 is respectively connected with the other end of the voltage dividing resistor R11, one end of the voltage dividing resistor R12, the other end of the storage filter capacitor C13, one end of a gate driving resistor R14, one end of a gate driving resistor R15 and one end of a gate driving resistor R16, the other end of the gate driving resistor R13 is connected with a gate of the P-channel field effect transistor S5, the other end of the gate driving resistor R14 is connected with a gate of the P-channel field effect transistor S6, the other end of the gate driving resistor R15 is connected with a gate of the P-channel field effect transistor S7, the other end of the gate driving resistor R16 is connected with a gate of the P-channel field effect transistor S8, and the drain of the P-channel field effect transistor S6 is respectively connected with the drain electrode of the drain of the P-channel field effect transistor S8.
2. The dual redundant power supply self-cutting and restoration circuit of claim 1, wherein the input EMI filter circuit comprises: common mode inductance L1, common mode inductance L3, differential mode inductance L2, differential mode inductance L4, differential mode capacitance C1, differential mode capacitance C2, differential mode capacitance C5, differential mode capacitance C6, common mode capacitance C3, common mode capacitance C4, common mode capacitance C7, and common mode capacitance C8.
3. The dual-redundancy power supply self-cutting and recovering circuit according to claim 2, wherein in the input EMI filter circuit, in the first branch, an input positive end of the common-mode inductor L1 is connected to the input high end Va1, one end of the differential-mode capacitor C1 is connected to the input high end Va1, the other end of the differential-mode capacitor C1 is connected to an input negative end of the common-mode inductor L1, an output positive end of the common-mode inductor L1 is connected to one end of the differential-mode inductor L2 and one end of the differential-mode capacitor C2, the other end of the differential-mode capacitor C2 is connected to an output negative end of the common-mode inductor L1, the other end of the differential-mode inductor L2 is connected to one end of the common-mode capacitor C3 and to one end of the common-mode capacitor C4, and the other end of the common-mode capacitor C4 is connected to an output negative end of the common-mode inductor L1; in the second path, the input positive end of the common-mode inductor L3 is connected with the input high end Va2, one end of the differential-mode capacitor C5 is connected with the input high end Va2, the other end of the differential-mode capacitor C5 is connected with the input negative end of the common-mode inductor L3, the output positive end of the common-mode inductor L3 is respectively connected with one end of the differential-mode inductor L4 and one end of the differential-mode capacitor C6, the other end of the differential-mode inductor C6 is connected with the output negative end of the common-mode inductor L3, the other end of the differential-mode inductor L4 is respectively connected with one end of the common-mode capacitor C7 and the output high end Vb2, and the other end of the common-mode capacitor C7 is respectively connected with the ground of the casing and one end of the common-mode capacitor C8; the negative output end of the common-mode inductor L1 is connected with the negative output end of the common-mode inductor L3.
4. A dual redundant power supply self-cutting and restoration circuit as set forth in claim 2 or 3 wherein the ideal diode or gate control circuit comprises: ideal diode controller U1, ideal diode controller U2, N-channel field effect transistor S1, N-channel field effect transistor S2, N-channel field effect transistor S3, N-channel field effect transistor S4, transient voltage suppression diode D1, transient voltage suppression diode D2, gate drive resistor R1, gate drive resistor R2, gate drive resistor R4, gate drive resistor R5, current limiting resistor R3, current limiting resistor R6, filter capacitor C9, and filter capacitor C10.
5. The circuit of claim 4, wherein IN the ideal diode or GATE control circuit, IN the first branch, the cathode of the transient suppression diode D1 is connected to the input high terminal Vb1, the anode of the transient suppression diode D1 is connected to the Vss terminal of the ideal diode controller U1, the IN terminal and the input high terminal Vb1 of the ideal diode controller U1, the SOURCE terminal of the ideal diode controller U1 is connected to the input high terminal Vb1, the SOURCE of the N-channel field effect transistor S2, the GATE of the N-channel field effect transistor S1 is connected to one end of the GATE drive resistor R1, the other end of the GATE drive resistor R1 is connected to the other end of the GATE drive resistor R2, the GATE terminal of the ideal diode controller U1 is connected to the drain of the N-channel field effect transistor S2, the OUT terminal of the ideal diode controller U1, the current limiting resistor R3, the current limiting resistor C9, and the filter capacitor C1 are connected to one end of the ideal diode control resistor U1, the other end of the filter, and the other end of the output capacitor C9; IN the second path, the cathode of the transient suppression diode D2 is connected to the input high terminal Vb2, the anode of the transient suppression diode D2 is connected to the Vss terminal of the ideal diode controller U2, the IN terminal of the ideal diode controller U2 is connected to the input high terminal Vb2, the SOURCE terminal of the N-channel field effect transistor S3, and the SOURCE terminal of the N-channel field effect transistor S4, the GATE of the N-channel field effect transistor S3 is connected to one terminal of the GATE driving resistor R4, the GATE of the N-channel field effect transistor S4 is connected to one terminal of the GATE driving resistor R5, the other terminal of the GATE driving resistor R4 is connected to the other terminal of the GATE driving resistor R5, the GATE terminal of the ideal diode controller U2, the drain terminal of the N-channel field effect transistor S3 is connected to the drain terminal of the N-channel field effect transistor S4, the OUT terminal of the ideal diode controller U2, one terminal of the current limiting resistor R6, and the output high terminal Ve, and the other terminal of the current limiting resistor R6 are connected to one terminal of the ideal diode controller U2, and the capacitor C10 is connected to the other terminal of the ideal diode 2, and the capacitor C10 is connected to the other terminal of the filter Vss.
6. The dual redundant power supply self-cutting and restoration circuit of claim 1, wherein the dual redundant power supply self-cutting and restoration circuit is used for power supply of on-board and off-board equipment.
CN202111382675.3A 2021-11-22 2021-11-22 Dual-path redundant power supply self-cutting and recovering circuit Active CN114069829B (en)

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