CN114068633A - Low-refraction layer and display device - Google Patents

Abstract

The present application relates to a low refractive layer and a display device. The display device includes: a plurality of light emitting elements, a color conversion layer on the light emitting elements, and a low refractive layer on the color conversion layer, wherein the low refractive layer includes a monomer represented by formula 1. In formula 1, R₁And R₃May each independently be a substituted or unsubstituted alkyl group or hydrogen, R₂May be a substituted or unsubstituted alkylene group having two or more carbon atoms, X_a、X_bAnd X_cMay each independently be a curable functional group, and n and m may each independently be a natural number of 1 to 5. Formula 1

Description

Low-refraction layer and display device

Cross Reference to Related Applications

This application claims priority and benefit of korean patent application No. 10-2020-0095354, filed on 30.7.2020 to the korean intellectual property office, the entire contents of which are hereby incorporated by reference.

Technical Field

Embodiments of the present disclosure relate to a low refractive layer and a display device.

Background

In recent years, interest in information display has increased. Accordingly, research and development on display devices are continuously being conducted.

Disclosure of Invention

Exemplary embodiments of the present disclosure provide a low refractive layer capable of improving display quality and light efficiency, and a display device.

Objects of embodiments of the present disclosure are not limited to the objects described above, and other objects not described above will be apparent to those of ordinary skill in the art from the following description.

A display device according to an exemplary embodiment of the present disclosure includes: a plurality of light emitting elements, a color conversion layer on the light emitting elements, and a low refractive layer on the color conversion layer, wherein the low refractive layer includes a monomer represented by formula 1 below:

formula 1

Wherein, in formula 1, R₁And R₃May each independently be substituted or unsubstitutedAlkyl radical of (2) or hydrogen, R₂May be a substituted or unsubstituted alkylene group having two or more carbon atoms, X_a、X_bAnd X_cMay each independently be a curable functional group, and n and m may each independently be a natural number of 1 to 5.

The monomer may be included in a content of 3 wt% to 10 wt% with respect to 100 wt% of the solid content of the low refractive layer.

The low refractive layer may further include hollow particles.

The hollow particles may be included in an amount of 10 wt% to 80 wt% with respect to 100 wt% of the solid content of the low refractive layer.

The curable functional group may include at least one selected from a methacrylate group, an acrylate group, a vinyl group, and an epoxy group.

The display device may further include an inorganic layer between the color conversion layer and the low refractive layer.

The display device may further include a color filter layer overlapping the color conversion layer, and the low refractive layer may be between the color conversion layer and the color filter layer.

The display device may further include an inorganic layer between the color filter layer and the low refractive layer.

The inorganic layer may comprise a material selected from silicon oxide (SiO)_xWhere x is a real number of 0.5 to 4), silicon nitride (SiN)_xWhere x is a real number of 0.5 to 4), silicon oxynitride (SiO)_xN_yWherein x is a real number of 0.5 to 4 and y is a real number of 0.1 to 2), aluminum oxide (AlO)_xWherein x is a real number of 0.5 to 4) and titanium oxide (TiO)_xWhere x is a real number of 0.5 to 4).

The color conversion layer may include a matrix resin and quantum dots dispersed in the matrix resin.

Each of the light emitting elements may include a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer.

The low refractive layer according to an exemplary embodiment of the present disclosure includes a monomer represented by formula 1 below:

formula 1

Wherein, in formula 1, R₁And R₃May each independently be a substituted or unsubstituted alkyl group or hydrogen, R₂May be a substituted or unsubstituted alkylene group having two or more carbon atoms, X_a、X_bAnd X_cMay each independently be a curable functional group, and n and m may each independently be a natural number of 1 to 5.

The monomer may be included in a content of 3 wt% to 10 wt% with respect to 100 wt% of the solid content of the low refractive layer.

The low refractive layer may further include hollow particles.

The hollow particles may be included in an amount of 10 wt% to 80 wt% with respect to 100 wt% of the solid content of the low refractive layer.

The hollow particle may have a diameter of 10nm to 200nm, and the shell of the hollow particle may have a thickness of 5nm to 50 nm.

The hollow particles may comprise hollow silica particles.

The hollow particle may include at least one selected from the group consisting of an acrylic polymer, a polyimide polymer, a urethane polymer, a styrene polymer, a siloxane polymer, and an epoxy polymer on a surface thereof.

The low refractive layer may further include at least one selected from a curing agent, a photopolymerization initiator, and an ultraviolet absorber.

The curable functional group may include at least one selected from a methacrylate group, an acrylate group, a vinyl group, and an epoxy group.

Other features of the exemplary embodiments are included in the detailed description and the accompanying drawings.

Drawings

The drawings illustrate embodiments of the subject matter of the present disclosure, together with the description, and together with the description serve to explain the principles of embodiments of the subject matter of the present disclosure.

Fig. 1 and 2 are a perspective view and a cross-sectional view illustrating a light emitting element according to an exemplary embodiment.

Fig. 3 is a plan view illustrating a display device according to an exemplary embodiment.

Fig. 4 to 6 are circuit diagrams illustrating a pixel according to an exemplary embodiment.

Fig. 7 is a cross-sectional view illustrating a display device according to an exemplary embodiment.

Fig. 8 and 9 are cross-sectional views illustrating the pixel of fig. 7.

Fig. 10 is a cross-sectional view illustrating a display device according to another exemplary embodiment.

Fig. 11 is a cross-sectional view illustrating a display device according to still another exemplary embodiment.

Detailed Description

The features of the present disclosure and methods of accomplishing the same will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are shown. However, the present disclosure is not limited to the exemplary embodiments set forth herein and may be embodied in various forms. The exemplary embodiments are provided only to complete the disclosure of the present disclosure and to enable those of ordinary skill in the art to fully understand the scope of the present disclosure. The scope of the disclosure is to be defined only by the claims appended hereto, and by their equivalents.

The terminology used in the description is for the purpose of describing the exemplary embodiments and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," "including" and/or "including," if used herein, specify the presence of stated components, steps, operations, and/or elements, but do not preclude the presence or addition of one or more other components, steps, operations, and/or elements.

Furthermore, the terms "connected" or "coupled" may mean physically and/or electrically connected or coupled. Further, the term can mean direct or indirect connection or coupling and integral or non-integral connection or coupling.

It will be understood that when an element or layer is referred to as being "on" or "over" another element or layer, it can be directly on or over the other element or layer or intervening elements or layers may be present. Like reference numerals refer to like elements throughout the specification.

It should be understood that although terms such as "first," "second," etc. may be used herein to describe various components, these components are not limited by these terms. These terms are only used to distinguish one element or component from another element or component. Accordingly, a first component described below may be referred to as a second component without departing from the scope and spirit of the present disclosure.

Hereinafter, exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

Fig. 1 and 2 are a perspective view and a cross-sectional view illustrating a light emitting element according to an exemplary embodiment. A rod-shaped light emitting element LD having a circular columnar shape is illustrated in fig. 1 and 2, but the type (or kind) and/or shape of the light emitting element LD is not limited thereto.

Referring to fig. 1 and 2, the light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. As an example, when the extending direction of the light emitting element LD is regarded as the direction of the length L, the light emitting element LD may include the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 sequentially stacked in the direction of the length L.

The light emitting element LD may be provided in a bar shape extending in one direction. The light emitting element LD may include a first end EP1 and a second end EP 2. One selected from the first semiconductor layer 11 and the second semiconductor layer 13 may be at the first end EP1 of the light emitting element LD. The other of the first semiconductor layer 11 and the second semiconductor layer 13 may be at the second end EP2 of the light emitting element LD.

According to an exemplary embodiment, the light emitting element LD may be a rod-shaped light emitting element (also referred to as a "rod-shaped light emitting diode") manufactured in a rod shape by an etching method or the like. In the present specification, the term "rod-like shape" includes all rod-like shapes and bar-like shapes, such as circular columns and polygonal columns, which are long in the direction of the length L (e.g., have an aspect ratio of more than 1). The shape of the cross section of the rod shape is not particularly limited. For example, the length L of the light emitting element LD may be larger than the diameter D (or the width of the cross section).

The light emitting element LD may have a small size of a nanometer scale to a micrometer scale. As an example, the light emitting element LD may have a diameter D (or width) and/or a length L, each of which is from the nano-scale to the micro-scale. However, the size of the light emitting element LD is not limited thereto. The size of the light emitting element LD may be variously changed according to design conditions of various devices (for example, a display device using a light emitting device including the light emitting element LD as a light source).

The first semiconductor layer 11 may be a first conductive type semiconductor layer. For example, the first semiconductor layer 11 may include an N-type semiconductor layer. As an example, the first semiconductor layer 11 may include an N-type semiconductor layer including any one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a first conductive type dopant such as silicon (Si), germanium (Ge), tin (Sn), and the like. However, the material constituting the first semiconductor layer 11 is not limited thereto, and the first semiconductor layer 11 may be made of various materials.

The active layer 12 may be on the first semiconductor layer 11 and may be formed to have a single quantum well structure or a multiple quantum well structure. The position of the active layer 12 may be variously changed according to the type (or kind) of the light emitting element LD.

A cladding layer doped with a conductive dopant may be formed on and/or under the active layer 12. As an example, the cladding layer may be formed as an AlGaN layer and/or an InAlGaN layer. According to example embodiments, materials such as AlGaN and/or InAlGaN may be used to form the active layer 12, and in addition, various materials may constitute the active layer 12.

The second semiconductor layer 13 may be on the active layer 12 and may include a semiconductor layer having a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include a P-type semiconductor layer. As an example, the second semiconductor layer 13 may include a P-type semiconductor layer including any one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a second conductivity type dopant such as magnesium (Mg). However, the material constituting the second semiconductor layer 13 is not limited thereto, and the second semiconductor layer 13 may be made of various materials.

In one illustrative example, the first semiconductor layer 11 and the second semiconductor layer 13 may have different lengths (or thicknesses) in the direction of the length L of the light emitting element LD. As an example, the first semiconductor layer 11 may have a length (or thickness) relatively greater than that of the second semiconductor layer 13 in the direction of the length L of the light emitting element LD. Therefore, when the second semiconductor layer 13 is at the first end EP1 and the first semiconductor layer 11 is at the second end EP2, the active layer 12 of the light emitting element LD may be positioned closer to the first end EP1 than the second end EP 2.

When a voltage greater than or equal to a threshold voltage is applied to both end portions of the light emitting element LD, electrons and holes are combined with each other in the active layer 12, and thus, the light emitting element LD emits light. By controlling light emission of the light emitting element LD using such a principle, the light emitting element LD can be used as a light source of various light emitting devices, for example, a light source of a pixel of a display device.

The light emitting element LD may further include an insulating film INF provided on a surface thereof. The insulating film INF may be formed on the surface of the light emitting element LD so as to surround at least the outer circumferential (e.g., circumferential) surface of the active layer 12. In addition, the insulating film INF may further surround one region of each of the first semiconductor layer 11 and the second semiconductor layer 13.

According to an exemplary embodiment, the insulating film INF may expose both end portions of the light emitting element LD having different polarities. For example, the insulating film INF may expose one end portion of each of the second semiconductor layer 13 and the first semiconductor layer 11 positioned at the first end portion EP1 and the second end portion EP2 of the light emitting element LD. In another exemplary embodiment, the insulating film INF may expose side portions of the first and second semiconductor layers 11 and 13 adjacent to the second and first end portions EP2 and EP1 of the light emitting element LD having different polarities.

According to an exemplary embodiment, the insulating film INF may be formed to include a material selected from silicon oxide (SiO)_x) Silicon nitride (SiN)_x) Aluminum oxide (AlO)_x) And titanium oxide (TiO)_x) Of at least one insulating material (e.g., made of aluminum oxide (AlO)_x) And silicon oxide (SiO)_x) A double layer made) the present disclosure need not be so limited. According to an exemplary embodiment, the insulating film INF may be removed or omitted.

When the insulating film INF is provided to cover a surface of the light emitting element LD, such as an outer peripheral (e.g., circumferential) surface of the active layer 12, short-circuiting of the active layer 12 with the first pixel electrode or the second pixel electrode, which will be described further below, can be prevented or reduced. Therefore, the electrical stability of the light emitting element LD can be ensured.

Further, when the insulating film INF is provided on the surface of the light emitting element LD, surface defects of the light emitting element LD can be minimized or reduced, thereby improving the life and efficiency of the light emitting element LD. Further, even when a plurality of light emitting elements LD are close to each other, occurrence of an undesired short circuit between the light emitting elements LD can be prevented or reduced.

In one exemplary embodiment, the light emitting element LD may further include additional components in addition to the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and/or the insulating film INF surrounding the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13. For example, the light emitting element LD may additionally include at least one fluorescent layer, active layer, semiconductor layer and/or electrode layer at one end side of the first semiconductor layer 11, the active layer 12 and/or the second semiconductor layer 13. As an example, the electrode layer may be at the first end EP1 and the second end EP2 of the light emitting element LD. The electrode layer may be an ohmic contact electrode, but the present disclosure is not necessarily limited thereto. The electrode layer may be a schottky contact electrode (e.g., an electrode at a metal-semiconductor junction). In some embodiments, in fig. 1 and 2, a rod-shaped light emitting element LD is illustrated, but the type (or kind), structure, and/or shape of the light emitting element LD may be variously changed. For example, the light emitting element LD may be formed as a core-shell structure having a polygonal pyramid shape.

The light-emitting device including the light-emitting element LD described above can be used for various types (or kinds) of devices including a display device that requires a light source. For example, a plurality of light emitting elements LD may be in each pixel of the display panel, and the light emitting elements LD may be used as a light source for each pixel. However, the application field of the light emitting element LD is not limited to the above-described examples. For example, the light emitting element LD may be used for other types (or kinds) of devices requiring a light source, such as a lighting device.

Fig. 3 is a plan view illustrating a display device according to an exemplary embodiment.

As an example of an electronic device that can use the light emitting element LD described in the exemplary embodiments of fig. 1 and 2 as a light source, a display device such as a display panel PNL included in a display apparatus is illustrated in fig. 3. However, the present disclosure is not necessarily limited thereto, and the display panel PNL may use various light emitting elements such as an Organic Light Emitting Diode (OLED) including an organic light emitting layer as a light source.

Each pixel unit PXU of the display panel PNL and each pixel constituting the pixel unit PXU may include one or more light emitting elements LD. For convenience, the structure of the display panel PNL is schematically illustrated based on the display area DA in fig. 3. However, according to an exemplary embodiment, at least one driving circuit unit (e.g., at least one selected from a scan driver and a data driver), a line, and a pad may be further in the display panel PNL.

Referring to fig. 3, the display panel PNL may include a substrate SUB and a pixel unit PXU on the substrate SUB. The pixel unit PXU may include the first pixel PXL1, the second pixel PXL2, and/or the third pixel PXL 3. Hereinafter, when at least one pixel among the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 is arbitrarily described, the pixel will be referred to as "pixel PXL", or when at least two pixels thereof are collectively described, the pixel will be referred to as "pixel PXL".

The substrate SUB may constitute a base member of the display panel PNL, and may be a rigid and/or flexible substrate and/or film. As an example, the substrate SUB may be a rigid substrate made of glass and/or tempered glass, a flexible substrate (or film) made of plastic and/or metal, or at least one insulating layer. The material and/or physical properties of the substrate SUB are not particularly limited.

In an exemplary embodiment, the substrate SUB may be substantially transparent. Here, the term "substantially transparent" may mean that light may be transmitted at a set or predetermined transmittance or a transmittance higher than the set or predetermined transmittance. In another exemplary embodiment, the substrate SUB may be translucent or opaque. Further, the substrate SUB may contain a reflective material according to an exemplary embodiment.

The display panel PNL and the substrate SUB for forming the display panel PNL may include a display area DA for displaying an image and a non-display area NDA other than the display area DA.

The pixels PXL may be in the display area DA. Various lines, pads, and/or embedded circuit units coupled to the pixels PXL of the display area DA may be in the non-display area NDA. The pixels PXL may be in the form of stripes and/or

Arrangement of (

Is a registered trademark of Samsung Display co., Ltd.) is regularly arranged. However, the arrangement structure of the pixels PXL is not limited thereto, and the pixels PXL may be arranged in the display area DA in various structures and/or manners.

According to an exemplary embodiment, two or more types (or kinds) of pixels PXL emitting light having different colors may be in the display area DA. As an example, the first pixel PXL1 emitting the first color light, the second pixel PXL2 emitting the second color light, and the third pixel PXL3 emitting the third color light may be arranged in the display area DA. The at least one first pixel PXL1, the at least one second pixel PXL2, and the at least one third pixel PXL3 adjacent to each other may constitute one pixel unit PXU capable of emitting light having various colors. For example, the first to third pixels (PXL1, PXL2, and PXL3) may be subpixels each emitting light having a set or predetermined color. According to an exemplary embodiment, the first pixel PXL1 may be a red pixel emitting red light, the second pixel PXL2 may be a green pixel emitting green light, and the third pixel PXL3 may be a blue pixel emitting blue light, but the disclosure is not limited thereto.

In one exemplary embodiment, the first, second, and third pixels PXL1, PXL2, and PXL3 may include an element emitting a first color light, an element emitting a second color light, and an element emitting a third color light, respectively, as light sources to emit the first, second, and third color lights, respectively. In another exemplary embodiment, the first, second, and third pixels PXL1, PXL2, and PXL3 may include light emitting elements that emit the same (e.g., substantially the same) color light. In addition, the first, second, and third pixels PXL1, PXL2, and PXL3 may include color conversion layers and/or color filters having different colors on the light emitting element, thereby emitting the first, second, and third color lights. However, the color, type (or kind) and/or number of the pixels PXL constituting each pixel unit PXU are not particularly limited. For example, the color of light emitted by each pixel PXL may be variously changed.

The pixels PXL may include at least one light source driven by a set or predetermined control signal (e.g., a scan signal and a data signal) and/or a set or predetermined power source (e.g., a first power source and a second power source). In one exemplary embodiment, the light source may include one or more than one light emitting element LD according to any one of the exemplary embodiments of fig. 1 and 2, for example, a micro light emitting element LD having a small size of a nano-scale to a micro-scale. However, the present disclosure is not necessarily limited thereto, and furthermore, various types (or kinds) of light emitting elements LD may be used as the light source of the pixels PXL.

In one exemplary embodiment, each pixel PXL may be formed as an active pixel. However, the type (or kind), structure, and/or driving method of the pixel PXL applicable to the display device are not particularly limited. For example, each of the pixels PXL having various structures and/or driving methods may be formed as a pixel of a passive light emitting display device or an active light emitting display device.

Fig. 4 to 6 are circuit diagrams illustrating a pixel according to an exemplary embodiment. For example, fig. 4 to 6 illustrate an embodiment of a pixel PXL suitable for an active display device. However, the type (or kind) of the pixel PXL and the display device is not limited thereto.

According to an exemplary embodiment, the pixel PXL illustrated in fig. 4 to 6 may be any one selected from among the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 provided in the display panel PNL of fig. 3. The first, second, and third pixels PXL1, PXL2, and PXL3 may have substantially the same or similar structures.

Referring to fig. 4, the pixel PXL may include a light source unit LSU for generating light at a luminance corresponding to a data signal and a pixel circuit PXC for driving the light source unit LSU.

The light source unit LSU may include one or more light emitting elements LD coupled between a first power source VDD and a second power source VSS. For example, the light source unit LSU may include a first electrode ELT1 (or also referred to as a "first pixel electrode" or a "first alignment electrode") coupled to a first power source VDD through the pixel circuit PXC and a first power line PL1, a second electrode ELT2 (or also referred to as a "second pixel electrode" or a "second alignment electrode") coupled to a second power source VSS through a second power line PL2, and a plurality of light emitting elements LD coupled in the same (e.g., substantially the same) direction between the first electrode ELT1 and the second electrode ELT 2. In one exemplary embodiment, the first electrode ELT1 may be an anode, and the second electrode ELT2 may be a cathode.

Each of the light emitting elements LD may include a first terminal (e.g., a P-type terminal) coupled to the first power source VDD through the first electrode ELT1 and/or the pixel circuit PXC and a second terminal (e.g., an N-type terminal) coupled to the second power source VSS through the second electrode ELT 2. For example, the light emitting elements LD may be coupled in parallel in the forward direction between the first electrode ELT1 and the second electrode ELT 2. Each of the light emitting elements LD coupled in the forward direction between the first power supply VDD and the second power supply VSS constitutes each effective light source, and the effective light sources may be gathered to form the light source unit LSU of the pixel PXL.

The first power supply VDD and the second power supply VSS may have different potentials so that the light emitting element LD emits light. As an example, the first power supply VDD may be set to a high potential power supply, and the second power supply VSS may be set to a low potential power supply. In this case, the potential difference between the first power supply VDD and the second power supply VSS may be set to be greater than or equal to the threshold voltage of the light emitting element LD during the emission period of the pixel PXL.

One end portion (e.g., P-type end portion) of the light emitting element LD constituting each light source unit LSU may be commonly coupled to the pixel circuit PXC through one electrode (e.g., the first electrode ELT1 of each pixel PXL) of the light source unit LSU, and may be coupled to the first power supply VDD through the pixel circuit PXC and the first power supply line PL 1. The other end portion (e.g., N-type end portion) of the light emitting element LD may be commonly coupled to the second power source VSS through the other electrode (e.g., the second electrode ELT2 of each pixel PXL) of the light source unit LSU and the second power source line PL 2.

The light emitting element LD may emit light at a luminance corresponding to the driving current supplied through the corresponding pixel circuit PXC. For example, during each frame period, the pixel circuits PXC may supply the light source units LSU with driving currents corresponding to gray-scale values expressed in the respective frames. The driving current supplied to the light source unit LSU may be divided to flow to the light emitting elements LD coupled in the forward direction. Therefore, when each light emitting element LD emits light at a luminance corresponding to a current flowing thereto, the light source unit LSU may emit light at a luminance corresponding to a driving current.

The pixel circuit PXC may be coupled between the first power source VDD and the first electrode ELT 1. The pixel circuits PXC may be coupled to the scan lines Si and the data lines Dj of the respective pixels PXL. As an example, when the pixels PXL are in the ith horizontal line (row) and the jth vertical line (column) of the display area DA (where i is a natural number and j is a natural number), the pixel circuits PXC of the pixels PXL may be coupled to the ith scan line Si and the jth data line Dj in the display area DA.

According to an exemplary embodiment, the pixel circuit PXC may include a plurality of transistors and at least one capacitor. For example, the pixel circuit PXC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

The first transistor T1 is coupled between the first power supply VDD and the light source unit LSU. For example, a first electrode (e.g., a source electrode) of the first transistor T1 may be coupled to the first power source VDD, and a second electrode (e.g., a drain electrode) of the first transistor T1 may be coupled to the first electrode ELT 1. A gate electrode of the first transistor T1 is coupled to the first node N1. The first transistor T1 controls a driving current supplied to the light source unit LSU in response to the voltage of the first node N1. For example, the first transistor T1 may be a driving transistor that controls a driving current of the pixel PXL.

The second transistor T2 is coupled between the data line Dj and the first node N1. For example, a first electrode (e.g., a source electrode) of the second transistor T2 may be coupled to the data line Dj, and a second electrode (e.g., a drain electrode) of the second transistor T2 may be coupled to the first node N1. The gate electrode of the second transistor T2 is coupled to the scan line Si. When a scan signal SSi having a gate-on voltage (e.g., a low voltage) is supplied from the scan line Si, the second transistor T2 is turned on to electrically couple the data line Dj and the first node N1.

During each frame period, the data signal DSj of a corresponding frame is supplied to the data line Dj, and the data signal DSj is transmitted to the first node N1 through the second transistor T2 turned on during a period in which the scan signal SSi having the gate-on voltage is supplied. For example, the second transistor T2 may be a switching transistor for transmitting each data signal DSj to the pixel PXL.

One electrode of the storage capacitor Cst is coupled to the first power source VDD, and the other electrode thereof is coupled to the first node N1. During each frame period, the storage capacitor Cst is charged with a voltage corresponding to the data signal DSj supplied to the first node N1.

In fig. 4, the transistors (e.g., all of the first transistor T1 and the second transistor T2) included in the pixel circuit PXC are illustrated as P-type transistors, but the present disclosure is not necessarily limited thereto. At least one selected from the first transistor T1 and the second transistor T2 may be changed to an N-type transistor. In addition, the pixel circuit PXC may be provided with pixel circuits having various structures and/or driving methods.

Referring to fig. 5, the pixel circuit PXC may be further coupled to the sensing control line SCLi and the sensing line SLj. As an example, the pixel circuits PXC of the pixels PXL in the ith horizontal line and the jth vertical line of the display area DA may be coupled to the ith sensing control line SCLi and the jth sensing line SLj of the display area DA. The pixel circuit PXC may further include a third transistor T3. In another exemplary embodiment, the sensing line SLj may be removed or omitted, and the characteristic of the pixel PXL may also be detected by detecting the sensing signal SENj passing through the data line Dj of the pixel PXL (or an adjacent pixel).

The third transistor T3 is coupled between the first transistor T1 and the sensing line SLj. For example, one electrode of the third transistor T3 may be coupled to a first electrode (e.g., a source electrode) of the first transistor T1 coupled to the first electrode ELT1, and the other electrode of the third transistor T3 may be coupled to the sensing line SLj. In some embodiments, when the sensing line SLj is removed or omitted, the other electrode of the third transistor T3 may be coupled to the data line Dj.

The gate electrode of the third transistor T3 is coupled to the sensing control line SCLi. When the sensing control line SCLi is removed or omitted, the gate electrode of the third transistor T3 may be coupled to the scan line Si. The third transistor T3 is turned on by a sensing control signal SCSi having a gate-on voltage (e.g., a high level voltage) supplied to the sensing control line SCLi during a set or predetermined sensing period, thereby electrically coupling the sensing line SLj and the first transistor T1.

According to an exemplary embodiment, the sensing period may be a period in which the characteristic (e.g., the threshold voltage of the first transistor T1) of each pixel PXL in the display area DA is extracted. During the sensing period described above, a set or predetermined reference voltage that may turn on the first transistor T1 may be supplied to the first node N1 through the data line Dj and the second transistor T2, or each pixel PXL may be coupled to a current source or the like to turn on the first transistor T1. In addition, the sensing control signal SCSi having the gate-on voltage may be supplied to the third transistor T3 to turn on the third transistor T3, thereby coupling the first transistor T1 to the sensing line SLj. Thereafter, the sensing signal SENj is obtained through the sensing line SLj, and the characteristic of each pixel PXL (including the threshold voltage of the first transistor T1) may be detected using the sensing signal SENj. The characteristic information of each pixel PXL may be used to convert image data so that a characteristic difference between pixels PXL in the display area DA may be compensated.

In fig. 5, all of the first to third transistors T1 to T3 are illustrated as N-type transistors, but the present disclosure is not necessarily limited thereto. For example, at least one selected from the first to third transistors T1 to T3 may be changed to a P-type transistor.

Further, in fig. 4 and 5, the effective light sources constituting each light source unit LSU, i.e., the light emitting elements LD are all coupled in parallel, but the present disclosure is not necessarily limited thereto. For example, as illustrated in fig. 6, the light source unit LSU of each pixel PXL may be formed in a serial structure including at least two stages. In describing the exemplary embodiment of fig. 6, detailed descriptions of components that are the same as or similar to those of the exemplary embodiment of fig. 4 and 5 (e.g., the pixel circuit PXC) will not be repeated.

Referring to fig. 6, the light source unit LSU may include at least two light emitting elements coupled in series with each other. As an example, the light source unit LSU may include a first light emitting element LD1, a second light emitting element LD2, and a third light emitting element LD3 coupled in series between a first power source VDD and a second power source VSS. The first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 may constitute an effective light source.

Hereinafter, when a setting or a specific light emitting element among the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 is described, the corresponding light emitting element will be referred to as "the first light emitting element LD 1", "the second light emitting element LD 2", or "the third light emitting element LD 3". When at least one of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 is arbitrarily described, the light-emitting element will be referred to as "light-emitting element LD", or when the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 are collectively described, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 will be referred to as "light-emitting element LD".

A first end portion (e.g., a P-type end portion) of the first light emitting element LD1 is coupled to a first power source VDD through a first electrode ELT1 (e.g., a first pixel electrode) of the light source unit LSU and the like. A second end (e.g., an N-type end) of the first light emitting element LD1 is coupled to a first end (e.g., a P-type end) of the second light emitting element LD2 through a first intermediate electrode IET 1.

The first end of the second light emitting element LD2 is coupled to the second end of the first light emitting element LD 1. A second end (e.g., an N-type end) of the second light emitting element LD2 is coupled to a first end (e.g., a P-type end) of the third light emitting element LD3 through a second intermediate electrode IET 2.

The first end of the third light emitting element LD3 is coupled to the second end of the second light emitting element LD 2. A second end portion (e.g., an N-type end portion) of the third light emitting element LD3 may be coupled to the second power source VSS through the second electrode ELT2 (e.g., a second pixel electrode) of the light source unit LSU and the like. In the above-described manner, the first, second, and third light emitting elements LD1, LD2, and LD3 may be sequentially coupled in series between the first and second electrodes ELT1 and ELT2 of the light source unit LSU.

Fig. 6 illustrates an exemplary embodiment in which the light emitting elements LD are coupled in a three-stage series structure, but the present disclosure is not necessarily limited thereto. Two light emitting elements LD may be coupled in a two-stage series structure, or four or more light emitting elements LD may be coupled in a four-stage or more-than-four-stage series structure.

Assuming that the same luminance is expressed using the light emitting elements LD under the same condition (e.g., the same size and/or number), the voltage applied between the first electrode ELT1 and the second electrode ELT2 may be increased and the magnitude of the driving current flowing in the light source unit LSU may be reduced in the light source unit LSU having the structure in which the light emitting elements LD are coupled in series, as compared to the light source unit LSU having the structure in which the light emitting elements LD are coupled in parallel. Therefore, when the light source unit LSU of each pixel PXL is formed by applying the series structure, the panel current flowing in the display panel PNL may be reduced.

As in the above-described exemplary embodiments, each light source unit LSU may include a plurality of light emitting elements LD coupled in a forward direction between the first power source VDD and the second power source VSS to constitute an effective light source. In addition, the connection structure between the light emitting elements LD may be variously changed according to the exemplary embodiment. For example, the light emitting elements LD may be coupled only in series or in parallel, or may be coupled in a series-parallel hybrid structure.

Fig. 7 is a cross-sectional view illustrating a display device according to an exemplary embodiment. Fig. 8 and 9 are cross-sectional views illustrating the pixel of fig. 7.

In fig. 7, a cross section of a display apparatus, for example, a cross section of a display panel PNL provided in the display apparatus is exemplified based on an area in which one pixel unit PXU including a first pixel PXL1, a second pixel PXL2, and a third pixel PXL3 adjacent to each other is positioned.

Further, fig. 8 and 9 schematically illustrate the structure of each pixel PXL based on one light emitting element LD. In order to illustrate various circuit elements constituting the pixel circuit PXC, a transistor T (e.g., the first transistor T1 of fig. 4, etc.) and a storage capacitor Cst, which are coupled to the first electrode ELT1, are illustrated. Hereinafter, when it is not necessary to distinguish and designate the first transistor T1, the first transistor T1 will also be collectively referred to as "transistor T".

In some embodiments, the structure and/or position on each layer of the transistor T and the storage capacitor Cst are not limited to the exemplary embodiments illustrated in fig. 8 and 9, and may be variously changed according to the exemplary embodiments. Further, in an exemplary embodiment, the transistor T constituting each pixel circuit PXC may have substantially the same or similar structure, but the disclosure is not limited thereto. For example, in another exemplary embodiment, at least one of the transistors T constituting each pixel circuit PXC may have a different cross-sectional structure from the other transistors T and/or may be on a different layer from the other transistors T.

Referring to fig. 7 to 9, the pixel PXL and the display device including the pixel PXL may include a substrate SUB, a circuit layer PCL on one surface of the substrate SUB, a display layer DPL, a color conversion layer CCL, a low refractive layer LRL, and/or a color filter layer CFL.

The circuit layer PCL may include circuit elements constituting the pixel circuit PXC of each pixel PXL and various lines coupled to the circuit elements. The display layer DPL may include electrodes (e.g., the first and second electrodes ELT1 and ELT2 and/or the first and second contact electrodes CNE1 and CNE2) and a light emitting element LD constituting the light source unit LSU of each pixel PXL.

The circuit layer PCL may include at least one circuit element electrically coupled to the light emitting element LD of each pixel PXL. For example, the circuit layer PCL may include a plurality of transistors T and storage capacitors Cst in each pixel area PXA and constituting the pixel circuit PXC of the corresponding pixel PXL. In addition, the circuit layer PCL may further include at least one power line and/or signal line coupled to each pixel circuit PXC and/or the light source unit LSU. For example, the circuit layer PCL may include the first power line PL1, the second power line PL2, and the scan line Si and the data line Dj of each pixel PXL. In some embodiments, when the pixel circuits PXC are removed or omitted and the light source unit LSU of each pixel PXL is directly coupled to the first and second power supply lines PL1 and PL2 (or set or predetermined signal lines), the circuit layer PCL may be removed or omitted.

In addition, the circuit layer PCL may include a plurality of insulating layers. For example, the circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, a first interlayer insulating layer ILD1, a second interlayer insulating layer ILD2, and/or a passivation layer PSV, which are sequentially stacked on one surface of the substrate SUB. In addition, the circuit layer PCL may optionally further include at least one light blocking pattern or the like under at least some of the transistors T.

The buffer layer BFL may prevent or reduce diffusion of impurities into each circuit element. The buffer layer BFL may be formed as a single layer, but may also be formed as a multi-layer including at least two layers. When the buffer layer BFL is provided as a plurality of layers, the respective layers may be made of the same (e.g., substantially the same) material or may be made of different materials. Various circuit elements such as the transistor T and the storage capacitor Cst, and various lines coupled to the circuit elements may be on the buffer layer BFL. In some embodiments, buffer layer BFL may be removed or omitted according to example embodiments. In this case, at least one circuit element and/or line may be directly on one surface of the substrate SUB.

Each transistor T includes a semiconductor pattern SCP (also referred to as a "semiconductor layer" or an "active layer"), a gate electrode GE, and first and second transistor electrodes TE1 and TE 2. Fig. 8 and 9 illustrate an exemplary embodiment in which each transistor T includes a first transistor electrode TE1 and a second transistor electrode TE2 formed separately from the semiconductor pattern SCP, but the present disclosure is not necessarily limited thereto. For example, in another exemplary embodiment, the first transistor electrode TE1 and/or the second transistor electrode TE2 provided in the at least one transistor T may be integrated with each semiconductor pattern SCP.

The semiconductor pattern SCP may be on the buffer layer BFL. As an example, the semiconductor pattern SCP may be between the gate insulating layer GI and the substrate SUB on which the buffer layer BFL is formed. The semiconductor pattern SCP may include a first region in contact (e.g., physical contact) with each of the first transistor electrodes TE1, a second region in contact (e.g., physical contact) with each of the second transistor electrodes TE2, and a channel region positioned between the first and second regions. According to an exemplary embodiment, one selected from the first region and the second region may be a source region, and the other thereof may be a drain region.

According to an exemplary embodiment, the semiconductor pattern SCP may be a semiconductor pattern made of polysilicon, amorphous silicon, an oxide semiconductor, or the like. Further, the channel region of the semiconductor pattern SCP may be a semiconductor pattern not doped with impurities, for example, an intrinsic semiconductor, and the first and second regions of the semiconductor pattern SCP may each be a semiconductor pattern doped with set or predetermined impurities.

In an exemplary embodiment, the semiconductor pattern SCP constituting the transistor T of each pixel circuit PXC may be made of substantially the same or similar materials. For example, the semiconductor pattern SCP of the transistor T may be made of the same (e.g., substantially the same) material selected from the group consisting of polysilicon, amorphous silicon, and an oxide semiconductor.

In another exemplary embodiment, some of the transistors T and the remaining transistors T may include a semiconductor pattern SCP made of different materials. For example, the semiconductor patterns SCP of some of the transistors T may be made of polysilicon and/or amorphous silicon, and the semiconductor patterns SCP of the remaining transistors T may be made of an oxide semiconductor.

The gate insulating layer GI may be on the semiconductor pattern SCP. As an example, the gate insulating layer GI may be between the semiconductor pattern SCP and the gate electrode GE. The gate insulating layer GI may be formed in a single layer or a plurality of layers, and may contain various types (or kinds) of organic/inorganic insulating materials including silicon nitride (SiN)_x) And/or silicon oxide (SiO)_x)。

The gate electrode GE may be on the gate insulating layer GI. For example, the gate electrode GE may overlap the semiconductor pattern SCP with the gate insulating layer GI interposed therebetween. In fig. 8 and 9, the transistor T having the top gate structure is illustrated, but in another exemplary embodiment, the transistor T may have a bottom gate structure. In this case, the gate electrode GE may be under the semiconductor pattern SCP to overlap the semiconductor pattern SCP.

The first interlayer insulating layer ILD1 may be on the gate electrode GE. As an example, the first interlayer insulating layer ILD1 may be between the gate electrode GE and the first and second transistor electrodes TE1 and TE 2. The first interlayer insulating layer ILD1 may be formed as a single layer or a plurality of layers, and may include at least one inorganic insulating material and/or organic insulating material. For example, the first interlayer insulating layer ILD1 may comprise various types (or kinds) of organic/inorganic insulating materials including silicon nitride (SiN)_x) Silicon oxide (SiO)_x) And/or silicon oxynitride (SiO)_xN_y) And the structural material of the first interlayer insulating layer ILD1 is not particularly limited.

The first and second transistor electrodes TE1 and TE2 may be on each semiconductor pattern SCP with at least one first interlayer insulating layer ILD1 interposed therebetween. For example, the first transistor electrode TE1 and the second transistor electrode TE2 may be on different ends of the semiconductor pattern SCP with the gate insulating layer GI and the first interlayer insulating layer ILD1 interposed therebetween. The first and second transistor electrodes TE1 and TE2 may be electrically coupled to each semiconductor pattern SCP. For example, the first and second transistor electrodes TE1 and TE2 may be coupled to the first and second regions of the semiconductor pattern SCP through respective contact holes passing through the gate insulating layer GI and the first interlayer insulating layer ILD 1. According to an exemplary embodiment, one selected from the first transistor electrode TE1 and the second transistor electrode TE2 may be a source electrode, and the other may be a drain electrode.

At least one transistor T provided in the pixel circuit PXC may be coupled to at least one pixel electrode. As an example, the transistor T may be electrically coupled to the first electrode ELT1 of the corresponding pixel PXL through a contact hole (e.g., the first contact hole CH1) passing through the passivation layer PSV and/or the bridge pattern BRP.

The storage capacitor Cst includes the first and second capacitive electrodes CE1 and CE2 that overlap each other. Each of the first and second capacitance electrodes CE1 and CE2 may be formed as a single layer or a plurality of layers. Further, at least one selected from the first and second capacitance electrodes CE1 and CE2 may be on the same layer as at least one electrode or semiconductor pattern SCP constituting the first transistor T1.

For example, the first capacitor electrode CE1 may be formed as a multi-layered electrode including the lower electrode LE on the same layer as the semiconductor pattern SCP of the first transistor T1, and the upper electrode UE on the same layer as the first electrode TE1 and the second electrode TE2 of the first transistor T1 and electrically coupled to the lower electrode LE. The second capacitance electrode CE2 may be formed as a single layer electrode on the same layer as the gate electrode of the first transistor T1 and between the lower electrode LE and the upper electrode UE of the first capacitance electrode CE 1. However, the structure and/or position of each of the first and second capacitance electrodes CE1 and CE2 may be variously changed. For example, one selected from the first and second capacitor electrodes CE1 and CE2 may include a conductive pattern on a layer different from the electrodes (e.g., the gate electrode GE and the first and second transistor electrodes TE1 and TE2) constituting the first transistor T1 and the semiconductor pattern SCP. As an example, the first and/or second capacitor electrodes CE1 and CE2 may have a single-layer structure or a multi-layer structure including a conductive pattern on the second interlayer insulating layer ILD 2.

In one exemplary embodiment, at least one signal line and/or power supply line coupled to each pixel PXL may be on the same layer as one electrode of a circuit element constituting the pixel circuit PXC. As an example, the scan line Si of each pixel PXL may be on the same layer as the gate electrode GE of the transistor T, and the data line Dj of each pixel PXL may be on the same layer as the first and second transistor electrodes TE1 and TE2 of the transistor T.

The first power supply line PL1 and/or the second power supply line PL2 may be on the same layer as the gate electrode GE of the transistor T or the first transistor electrode TE1 and the second transistor electrode TE2 or on a different layer. As an example, the second power line PL2 for supplying power of the second power source VSS may be on the second interlayer insulating layer ILD2, and thus, at least a portion thereof may be covered by the passivation layer PSV. The second power line PL2 may be electrically coupled to the second electrode ELT2 of the light source unit LSU on the passivation layer PSV through a second contact hole CH2 passing through the passivation layer PSV. However, the position and/or structure of the first power supply line PL1 and/or the second power supply line PL2 may be variously changed. For example, the second power line PL2 may be on the same layer as the gate electrode GE of the transistor T or the first and second transistor electrodes TE1 and TE2, and thus electrically coupled to the second electrode ELT2 through at least one bridge pattern and/or the second contact hole CH 2.

The second interlayer insulating layer ILD2 may be on the first interlayer insulating layer ILD1 and may cover the first and second transistor electrodes TE1 and TE2 and/or the storage capacitor Cst positioned on the first interlayer insulating layer ILD 1. The second interlayer insulating layer ILD2 may be formed as a single layer or a plurality of layers, and may include at least one inorganic insulating material and/or organic insulating material. For example, the second interlayer insulating layer ILD2 may include various types (or kinds) of organic/inorganic insulating materials including silicon nitride (SiN)_x) Silicon oxide (SiO)_x) And/or silicon oxynitride (SiO)_xN_y) However, the present disclosure is not necessarily limited thereto.

A bridge pattern BRP for coupling at least one circuit element (e.g., the first transistor T1) provided in the pixel circuit PXC to the first electrode ELT1, the first power supply line PL1, and/or the second power supply line PL2 may be on the second interlayer insulating layer ILD 2. However, the second interlayer insulating layer ILD2 may be removed or omitted according to an exemplary embodiment. In this case, the bridge pattern BRP or the like of fig. 8 and 9 may be removed or omitted, and the second power supply line PL2 may be on a layer in which one electrode of the transistor T is positioned.

The passivation layer PSV may be on circuit elements such as the transistor T and the storage capacitor Cst and/or lines such as the first and second power supply lines PL1 and PL 2. The passivation layer PSV may be formed in a single layer or a plurality of layers, and may include at least one inorganic insulating material and/or organic insulating material. As an example, the passivation layer PSV may include at least an organic insulating layer, and may serve to substantially planarize a surface of the circuit layer PCL.

The display layer DPL may be on the passivation layer PSV of the circuit layer PCL. The display layer DPL may include a first electrode ELT1 and a second electrode ELT2 in the emission area EMA of each pixel PXL and constituting at least one pair of each light source unit LSU, and one or more light emitting elements LD coupled between the first electrode ELT1 and the second electrode ELT 2. In fig. 7 to 9, one light emitting element LD in each pixel PXL is illustrated, but as in the exemplary embodiment of fig. 4 and the like, each pixel PXL may include a plurality of light emitting elements LD coupled between the first electrode ELT1 and the second electrode ELT 2. Therefore, each exemplary embodiment will be described below assuming that the pixel PXL includes a plurality of light emitting elements LD.

In addition, the display layer DPL may further include first and second contact electrodes CNE1 and CNE2 for more stably coupling the light emitting element LD between the first and second electrodes ELT1 and ELT2, a first bank BNK1 for protruding one region of each of the first and second electrodes ELT1 and ELT2 and/or the first and second contact electrodes CNE1 and CNE2 upward, and a second bank BNK2 surrounding each emission area EMA. In addition, the display layer DPL may further include at least one conductive layer and/or insulating layer.

The first bank BNK1 may be on the circuit layer PCL. The first bank BNK1 may be formed in a separation type or an integral type pattern. The first bank BNK1 may protrude in the height direction of the substrate SUB.

The first bank BNK1 may have various shapes according to exemplary embodiments. In an exemplary embodiment, the first bank BNK1 may be a bank structure having a positive tapered structure. For example, as illustrated in fig. 7 to 9, the first bank BNK1 may be formed to have an inclined surface inclined at a set or predetermined angle with respect to the substrate SUB. However, the present disclosure is not necessarily limited thereto, and the first bank BNK1 may have a sidewall having a curved or stepped shape. As an example, the first dike BNK1 may have a cross-section with a semi-circular or semi-elliptical shape.

The electrode and the insulating layer on the first bank BNK1 may have a shape corresponding to the first bank BNK 1. As an example, the first and second electrodes ELT1 and ELT2 and the first and second contact electrodes CNE1 and CNE2 may be on one region of the first bank BNK1 and may have an inclined surface or a curved surface having a shape corresponding to the shape of the first bank BNK 1. Similarly, the first insulating layer INS1, the third insulating layer INS3, and/or the fourth insulating layer INS4 may be on the first bank BNK1, and may have an inclined surface or a curved surface having a shape corresponding to the shape of the first bank BNK 1.

The first bank BNK1 may comprise an insulating material comprising at least one inorganic material and/or organic material. As an example, the first bank BNK1 may include at least one layer of an inorganic film containing, for example, silicon nitride (SiN)_x) And/or silicon oxide (SiO)_x) Various inorganic insulating materials. In some embodiments, the first bank BNK1 may include an organic film and/or a photoresist film including at least one layer of various types (or kinds) of organic insulating materials, and/or may include a single layer or a multilayer insulator including a combination of organic and inorganic materials. For example, the structural material and/or pattern shape of the first bank BNK1 may be variously changed.

In an exemplary embodiment, the first bank BNK1 may serve as a reflective member. As an example, the first bank BNK1 may serve as a reflective member that improves light efficiency of the pixel PXL by guiding light emitted from each light emitting element LD in a suitable or desired direction (e.g., an upper direction of the pixel PXL) together with the first electrode ELT1 and the second electrode ELT2 provided thereon.

The first electrode ELT1 and the second electrode ELT2 constituting the pixel electrode of each pixel PXL may be on the first bank BNK 1. The first electrode ELT1 and the second electrode ELT2 may be provided and/or formed in each pixel area PXA of each pixel PXL therein. For example, the first electrode ELT1 and the second electrode ELT2 may be in the emission area EMA of each pixel PXL. The first electrode ELT1 and the second electrode ELT2 may be spaced apart from each other. For example, the first electrode ELT1 and the second electrode ELT2 may be spaced apart from each other by a set or predetermined interval in each emission area EMA, and may be side by side.

According to an example embodiment, the first electrode ELT1 and/or the second electrode ELT2 may have a pattern separated for each pixel PXL or may have a pattern commonly coupled to a plurality of pixels PXL. In some embodiments, before the process of forming the pixels PXL, for example, the process of aligning the light emitting elements LD is completed, the first electrodes ELT1 of the pixels PXL in the display area DA may be coupled to each other, and the second electrodes ELT2 of the pixels PXL may be coupled to each other. For example, before the alignment of the light emitting element LD is completed, the first electrodes ELT1 of the pixels PXL may be integrally or non-integrally formed with each other and may be electrically coupled to each other, and the second electrodes ELT2 of the pixels PXL may be integrally or non-integrally formed with each other and may be electrically coupled to each other. When the first electrode ELT1 or the second electrode ELT2 of the pixel PXL are non-integrally coupled to each other, the first electrode ELT1 or the second electrode ELT2 may be electrically coupled to each other through at least one contact hole and/or a bridge pattern.

In the alignment operation of the light emitting element LD, the first electrode ELT1 and the second electrode ELT2 may each receive a first alignment signal (or a first alignment voltage) and/or a second alignment signal (or a second alignment voltage). As an example, one selected from the first electrode ELT1 and the second electrode ELT2 may receive an Alternating Current (AC) alignment signal, and the other one of the first electrode ELT1 and the second electrode ELT2 may receive an alignment voltage (e.g., a ground voltage) having a constant voltage level. In some embodiments, in the alignment operation of the light emitting element LD, a set or predetermined alignment signal may be applied to the first electrode ELT1 and the second electrode ELT 2. Accordingly, an electric field may be formed between the first electrode ELT1 and the second electrode ELT 2. The light emitting element LD provided in each pixel region (e.g., the emission region EMA of each pixel PXL) may be self-aligned between the first electrode ELT1 and the second electrode ELT2 by an electric field. After the alignment of the light emitting element LD is completed, at least the first electrode ELT1 may be disconnected between the pixels PXL, and thus, the pixels PXL may be formed to be driven individually.

The first electrode ELT1 may be electrically coupled to a set or predetermined circuit element (e.g., at least one transistor constituting the pixel circuit PXC), a power supply line (e.g., the first power supply line PL1), and/or a signal line (e.g., the scan line Si, the data line Dj, or a set or predetermined control line) through the first contact hole CH 1. In one exemplary embodiment, the first electrode ELT1 may be electrically coupled to the bridge pattern BRP through the first contact hole CH1 and may be electrically coupled to the transistor T through the bridge pattern BRP. However, the present disclosure is not necessarily limited thereto, and the first electrode ELT1 may be directly coupled to a set or predetermined power line or signal line.

The second electrode ELT2 may be electrically coupled to a set or predetermined circuit element (e.g., at least one transistor constituting the pixel circuit PXC), a power supply line (e.g., the second power supply line PL2), and/or a signal line (e.g., the scan line Si, the data line Dj, or a set or predetermined control line) through the second contact hole CH 2. In one exemplary embodiment, the second electrode ELT2 may be electrically coupled to the second power line PL2 through the second contact hole CH 2. However, the present disclosure is not necessarily limited thereto, and the second electrode ELT2 may be directly coupled to a set or predetermined power line or signal line.

Each of first electrode ELT1 and second electrode ELT2 can include at least one conductive material (e.g., an electrically conductive material). As an example, each of the first electrode ELT1 and the second electrode ELT2 may include at least one metal selected from various metal materials including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), and copper (Cu), or an alloy including the at least one metal, or may include at least one conductive material selected from a conductive oxide (e.g., Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Indium Tin Zinc Oxide (ITZO), zinc oxide (ZnO), Aluminum Zinc Oxide (AZO), Gallium Zinc Oxide (GZO), Zinc Tin Oxide (ZTO), Gallium Tin Oxide (GTO), and/or Fluorine Tin Oxide (FTO)) and a conductive polymer (e.g., poly (3, 4-ethylenedioxythiophene) (PEDOT)), the present disclosure is not so limited. For example, each of first electrode ELT1 and second electrode ELT2 can include other conductive materials (e.g., conductive materials), such as carbon nanotubes and/or graphene. In addition, each of the first electrode ELT1 and the second electrode ELT2 may be formed as a single layer or a plurality of layers. As an example, each of the first electrode ELT1 and the second electrode ELT2 may include a reflective electrode layer including a reflective conductive material (e.g., a reflective conductive material). In addition, each of the first electrode ELT1 and the second electrode ELT2 may optionally further include at least one transparent electrode layer on and/or under the reflective electrode layer and at least one conductive cover layer covering the upper portion of the reflective electrode layer and/or the transparent electrode layer.

The first insulating layer INS1 may be on one region of each of the first electrode ELT1 and the second electrode ELT 2. For example, the first insulating layer INS1 may be formed to cover one region of each of the first and second electrodes ELT1 and ELT2, and may include an opening exposing the other region of each of the first and second electrodes ELT1 and ELT 2. As an example, the first insulating layer INS1 may include an opening formed on an upper surface of the first bank BNK 1. The first electrode ELT1 and the second electrode ELT2 may be electrically coupled to the first contact electrode CNE1 and the second contact electrode CNE2, respectively, in a region in which the first insulating layer INS1 is opened. In some embodiments, the first insulating layer INS1 may be removed or omitted according to example embodiments. In this case, the light emitting element LD may be directly on the passivation layer PSV and/or one end portion of the first electrode ELT1 and the second electrode ELT 2.

In one exemplary embodiment, the first insulating layer INS1 may be formed to mainly and completely cover the first electrode ELT1 and the second electrode ELT 2. After the light emitting element LD is provided and aligned on the first insulating layer INS1, the first insulating layer INS1 may be partially opened to expose one region of the first electrode ELT1 and the second electrode ELT 2. For example, the first insulating layer INS1 may have an opening exposing one region of the first and second electrodes ELT1 and ELT2 on the upper surface of the first bank BNK1, and may cover at least a portion of the inclined surfaces and/or the curved surfaces of the first and second electrodes ELT1 and ELT 2. In another exemplary embodiment, after the provision and alignment of the light emitting elements LD are completed, the first insulating layer INS1 may be patterned in the form of an individual pattern that is only partially under the light emitting elements LD. After the first and second electrodes ELT1 and ELT2 are formed, a first insulating layer INS1 may be formed to cover the first and second electrodes ELT1 and ELT 2. Accordingly, damage to the first electrode ELT1 and the second electrode ELT2 in a subsequent process may be prevented or reduced.

The first interlayer insulating layer ILD1 may be formed as a single layer or a plurality of layers, and may include at least one inorganic insulating material and/or organic insulating material. For example, the first interlayer insulating layer ILD1 may comprise various types (or kinds) of organic/inorganic insulating materials including silicon nitride (SiN)_x) Silicon oxide (SiO)_x) And/or aluminum oxide (AlO)_x)。

The light emitting element LD may be provided and aligned on the first and second electrodes ELT1 and ELT2 and the first insulating layer INS 1. In some embodiments, the second bank BNK2 may be formed around the emission area EMA before the light emitting element LD is provided. For example, the second bank BNK2 may be formed in the display area DA to surround each of the emission areas EMA.

The second bank BNK2 may be a structure defining the emission area EMA of each pixel PXL, and may be, for example, a pixel defining layer. For example, the second bank BNK2 may be in a border area of each pixel area PXA in which each pixel PXL is provided and/or in an area between adjacent pixels PXL so as to surround the emission area EMA of each pixel area PXA. Hereinafter, when at least one pixel area among the first pixel area PXA1, the second pixel area PXA2, and the third pixel area PXA3 is arbitrarily described, the pixel area will be referred to as "pixel area PXA", or when at least two pixel areas thereof are collectively described, the pixel area will be referred to as "pixel area PXA".

The second bank BNK2 may contain at least one light blocking and/or reflecting material to prevent or reduce light leakage between adjacent pixels PXL. For example, the second bank BNK2 may comprise at least one black matrix material (e.g., at least one suitable light blocking material commonly used in the art) selected from various types (or kinds) of black matrix materials and/or color filter materials having a set or specific color. For example, the second bank BNK2 may be formed in a black opaque pattern to block or reduce light transmission. In an exemplary embodiment, a reflective layer may be formed on the surface (e.g., sidewalls) of the second bank BNK2 to further increase the optical efficiency of the pixel PXL.

Further, in the operation of providing the light emitting element LD to each pixel PXL, the second bank BNK2 may function as a dam structure defining each emission area EMA to which the light emitting element LD should be supplied. For example, since each emission area EMA is divided by the second bank BNK2, a desired type (or kind) and/or amount of light emitting element ink can be supplied to the emission area EMA.

In an exemplary embodiment, in forming the first bank BNK1 of the pixel PXL, the second bank BNK2 may be formed on the same layer in parallel (e.g., simultaneously) with the first bank BNK 1. In another exemplary embodiment, the second bank BNK2 may be formed on the same layer as the first bank BNK1 or a different layer through a process separate from the process of forming the first bank BNK 1. As an example, the second bank BNK2 may be formed on the first bank BNK 1. For example, the second bank BNK2 may be formed on the first insulating layer INS1, but the present disclosure is not limited thereto.

The light emitting element LD may be provided to each pixel region PXA in which the first bank BNK1, the first and second electrodes ELT1 and ELT2, the first insulating layer INS1, and the second bank BNK2 are formed, and may be aligned between the first electrode ELT1 and the second electrode ELT 2. As an example, the plurality of light emitting elements LD may be provided to the emission area EMA of each pixel PXL by an ink-jet method, a slit coating method, and/or various other methods. The light emitting element LD may be aligned to have directivity between the first electrode ELT1 and the second electrode ELT2 by a set or predetermined alignment signal (or alignment voltage) applied to each of the first electrode ELT1 and the second electrode ELT 2.

In one exemplary embodiment, at least some of the light emitting elements LD may be between the pair of first and second electrodes ELT1 and ELT2 such that both ends thereof (e.g., the first and second ends EP1 and EP2) overlap the pair of first and second electrodes ELT1 and ELT 2. In another exemplary embodiment, at least some of the light emitting elements LD may be between a pair of adjacent first and second electrodes ELT1 and ELT2 so as not to overlap the first and/or second electrodes ELT1 and/or ELT2, and may be electrically coupled to the pair of first and second electrodes ELT1 and ELT2 through the first and second contact electrodes CNE1 and CNE 2. Each light emitting element LD electrically coupled between the first electrode ELT1 and the second electrode ELT2 may constitute an effective light source of the corresponding pixel PXL. The effective light sources may constitute the light source units LSU of the respective pixels PXL.

The second insulating layer INS2 may be on one region of the light emitting element LD. For example, the second insulating layer INS2 may be on one region of each light emitting element LD so as to expose the first and second end portions EP1 and EP2 of each light emitting element LD. As an example, the second insulating layer INS2 may be locally on one region including the central region of each light emitting element LD. When the second insulating layer INS2 is formed on the light emitting element LD after the alignment of the light emitting element LD is completed, the separation of the light emitting element LD from its alignment position can be prevented or reduced.

The second insulating layer INS2 may be formed as a separate pattern in the emission area EMA of each pixel PXL, but the present disclosure is not limited thereto. The second insulating layer INS2 may be removed or omitted according to an exemplary embodiment, and in this case, one end portion of each of the first and second contact electrodes CNE1 and CNE2 may be positioned directly on (e.g., physically contacted with) the upper surface of the light emitting element LD.

The second insulating layer INS2 may be formed as a single layer or a plurality of layers and may include at least one inorganic insulating material and/or organic insulating material. For example, the second insulating layer INS2 may include various types (or kinds) of organic/inorganic insulating materials including silicon nitride (SiN)_x) Silicon oxide (SiO)_x) Aluminum oxide (AlO)_x) And/or a Photoresist (PR) material.

Both ends of the light emitting element LD, i.e., the first end EP1 and the second end EP2, which are not covered with the second insulating layer INS2, may be covered with the first contact electrode CNE1 and the second contact electrode CNE2, respectively. The first contact electrode CNE1 and the second contact electrode CNE2 are formed to be spaced apart from each other. For example, the first and second contact electrodes CNE1 and CNE2 adjacent to each other may be spaced apart from each other on the first and second ends EP1 and EP2 of at least one adjacent light emitting element LD with the second insulating layer INS2 interposed therebetween.

In addition, the first and second contact electrodes CNE1 and CNE2 may be on the first and second electrodes ELT1 and ELT2 so as to cover exposed regions of the first and second electrodes ELT1 and ELT 2. For example, the first and second contact electrodes CNE1 and CNE2 may be on one region of each of the first and second electrodes ELT1 and ELT2 so as to be in direct or indirect contact with the first and second electrodes ELT1 and ELT2, respectively, on or around the first bank BNK 1. Accordingly, the first and second contact electrodes CNE1 and CNE2 may be electrically coupled to the first and second electrodes ELT1 and ELT2, respectively. For example, the first electrode ELT1 and the second electrode ELT2 may be electrically coupled to the first end EP1 and the second end EP2 of at least one adjacent light emitting element LD through the first contact electrode CNE1 and the second contact electrode CNE2, respectively.

In one exemplary embodiment, as illustrated in fig. 8, the first contact electrode CNE1 and the second contact electrode CNE2 may be sequentially formed on different layers on one surface of the substrate SUB. In this case, the third insulating layer INS3 may be between the first contact electrode CNE1 and the second contact electrode CNE 2. In some embodiments, the order of forming the first contact electrode CNE1 and the second contact electrode CNE2 may be changed. For example, in another exemplary embodiment, the second contact electrode CNE2 may be first formed before forming the first contact electrode CNE1, and the first contact electrode CNE1 may be formed on one end portion of the third insulating layer INS3 after forming the third insulating layer INS3 to cover the second contact electrode CNE2 and the second insulating layer INS 2. However, the present disclosure is not necessarily limited thereto, and as illustrated in fig. 9, the first contact electrode CNE1 and the second contact electrode CNE2 may be on the same layer. For example, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed as the same conductive layer on one surface of the substrate SUB. In this case, since the first contact electrode CNE1 and the second contact electrode CNE2 may be formed at the same (e.g., substantially the same) time in the same (e.g., substantially the same) process, the manufacturing process of the pixel PXL and the display device including the pixel PXL may be simplified. However, the present disclosure is not necessarily limited thereto, and the first and second contact electrodes CNE1 and CNE2 may be sequentially formed.

The first and second contact electrodes CNE1 and CNE2 may be made of various transparent conductive materials. As an example, the first and second contact electrodes CNE1 and CNE2 may include at least one selected from various transparent conductive materials, such as transparent conductive materials, for example, Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Indium Tin Zinc Oxide (ITZO), zinc oxide (ZnO), Aluminum Zinc Oxide (AZO), Gallium Zinc Oxide (GZO), Zinc Tin Oxide (ZTO), Gallium Tin Oxide (GTO), and/or Fluorine Tin Oxide (FTO), and may be substantially transparent or translucent to satisfy suitable or desired transmittance. Accordingly, light emitted from the light emitting element LD through the first and second ends EP1 and EP2 thereof may pass through the first and second contact electrodes CNE1 and CNE2 to be emitted to the outside of the display panel PNL.

The third insulating layer INS3 may be on the first contact electrode CNE1 so as to cover the first contact electrode CNE 1. For example, the third insulating layer INS3 may be on the second insulating layer INS2 and the first contact electrode CNE1 such that one end of the third insulating layer INS3 is interposed between the first contact electrode CNE1 and the second contact electrode CNE 2. One end portion of the second contact electrode CNE2 may be on one end portion of the third insulating layer INS 3.

As described above, when the second insulating layer INS2 and the third insulating layer INS3 are formed on the light emitting element LD, electrical stability may be ensured between the first end EP1 and the second end EP2 of the light emitting element LD. For example, the first contact electrode CNE1 and the second contact electrode CNE2 may be stably separated by the second insulating layer INS2 and the third insulating layer INS 3. Therefore, it is possible to effectively prevent or reduce the occurrence of the short-circuit defect between the first end EP1 and the second end EP2 of the light-emitting element LD.

The third insulating layer INS3 may be formed as a single layer or a plurality of layers and may include at least one inorganic insulating material and/or organic insulating material. For example, the third insulating layer INS3 may includeOrganic/inorganic insulating materials of the type (or kind) including silicon nitride (SiN)_x) Silicon oxide (SiO)_x) Aluminum oxide (AlO)_x) And/or a PR material.

The fourth insulating layer INS4 may be on the first and second contact electrodes CNE1 and CNE2 and/or the third insulating layer INS 3. For example, the fourth insulating layer INS4 may cover the first and second banks BNK1 and BNK2, the first and second electrodes ELT1 and ELT2, and the first, second, and/or third insulating layers INS1, INS2, and INS3, the light emitting element LD, and the first and second contact electrodes CNE1 and CNE 2. The fourth insulation layer INS4 may include at least one layer of an inorganic film and/or an organic film.

The fourth insulating layer INS4 may be formed as a single layer or a plurality of layers and may include at least one inorganic insulating material and/or organic insulating material. For example, the fourth insulating layer INS4 may include various types (or kinds) of organic/inorganic insulating materials including silicon nitride (SiN)_x) Silicon oxide (SiO)_x) And/or aluminum oxide (AlO)_x)。

In one exemplary embodiment, the fourth insulation layer INS4 may include a thin film encapsulation layer having a multi-layer structure. For example, the fourth insulation layer INS4 may include a thin film encapsulation layer having a multilayer structure including at least two inorganic insulation layers and at least one organic insulation layer interposed between the at least two inorganic insulation layers. However, the present disclosure is not necessarily limited thereto, and the structural material and/or structure of the fourth insulating layer INS4 may variously be changed.

The color conversion layer CCL may be on the display layer DPL. The color conversion layer CCL may be in a region partitioned by the second bank BNK 2.

The color conversion layer CCL may include a first color conversion layer CCL1 on the first pixel PXL1, a second color conversion layer CCL2 on the second pixel PXL2, and a light scattering layer LSL on the third pixel PXL 3.

In one exemplary embodiment, the first to third pixels (PXL1, PXL2, and PXL3) may include light emitting elements LD emitting light having the same (e.g., substantially the same) color. For example, the first to third pixels (PXL1, PXL2, and PXL3) may include a light emitting element LD that emits a third color light (e.g., color light in a wavelength band of about 400nm to about 500 nm). The color conversion layer CCL including the color conversion particles is on at least some of the first to third pixels (PXL1, PXL2, and PXL3) PXL, thereby displaying a full-color image. However, the present disclosure is not necessarily limited thereto, and the first to third pixels (PXL1, PXL2, and PXL3) may include light emitting elements LD emitting light having different colors. For example, the first pixel PXL1 may include an element LD emitting light of a first color (e.g., red), and the second pixel PXL2 may include an element LD emitting light of a second color (e.g., green), and the third pixel PXL3 may include an element LD emitting light of a third color (e.g., blue).

The first color conversion layer CCL1 may include first color conversion particles that convert third color light emitted from the light emitting elements LD into first color light. For example, when the light emitting element LD is a blue light emitting element emitting blue light and the first pixel PXL1 is a red pixel, the first color conversion layer CCL1 may include first quantum dots QDr converting the blue light emitted from the blue light emitting element into red light. For example, the first color conversion layer CCL1 may include a plurality of first quantum dots QDr dispersed in a set or predetermined matrix material (e.g., a matrix resin). The first quantum dot QDr may absorb blue light and change a wavelength according to energy conversion to emit red light in a wavelength band of about 620nm to about 780 nm. In some embodiments, when the first pixel PXL1 is a different color pixel, the first color conversion layer CCL1 may include first quantum dots corresponding to a color of the first pixel PXL 1.

The second color conversion layer CCL2 may include second color conversion particles that convert third color light emitted from the light emitting elements LD into second color light. As an example, when the light emitting element LD is a blue light emitting element emitting blue light and the second pixel PXL2 is a green pixel, the second color conversion layer CCL2 may include second quantum dots QDg converting blue light emitted from the blue light emitting element into green light. For example, the second color conversion layer CCL2 may include a plurality of second quantum dots QDg dispersed in a set or predetermined matrix material (e.g., a matrix resin). The second quantum dots QDg may absorb blue light and change wavelength according to energy conversion to emit green light in a wavelength band of about 500nm to about 570 nm. In some embodiments, when the second pixel PXL2 is a different color pixel, the second color conversion layer CCL2 may include second quantum dots corresponding to a color of the second pixel PXL 2.

Each of the first quantum dot QDr and the second quantum dot QDg may be selected from group II-IV compounds, group IV-VI compounds, group IV elements, group VI compounds, and combinations thereof, but the present disclosure is not limited thereto.

The first and second quantum dots QDr and QDg may have a Full Width Half Maximum (FWHM) of an emission wavelength spectrum of about 45nm or less than 45nm, and light emitted through the first and second quantum dots QDr and QDg may be emitted in all directions (e.g., in substantially each direction). Accordingly, the viewing angle of the display device can be improved.

In some embodiments, the first quantum dot QDr and the second quantum dot QDg may be: spherical, pyramidal, multi-arm, and/or cubic nanoparticles, nanotubes, nanowires, nanofibers, and/or nanoplate particles, although the disclosure is not necessarily limited thereto. The shapes of the first quantum dot QDr and the second quantum dot QDg may be variously changed.

In one exemplary embodiment, when blue light having a relatively short wavelength in the visible light region is incident on each of the first and second quantum dots QDr and QDg, absorption coefficients of the first and second quantum dots QDr and QDg may be increased. Therefore, the efficiency of light emitted from the first and second pixels PXL1 and PXL2 may be increased finally, and excellent color reproducibility may also be ensured. Further, when the light source units LSU of the first, second, and third pixels PXL1, PXL2, and PXL3 are formed using the elements LD (e.g., the elements LD that emit blue light) that emit the same (e.g., substantially the same) color light, the manufacturing efficiency of the display device may be increased.

The light scattering layer LSL may be optionally provided in order to effectively use the third color light emitted from the light emitting element LD. As an example, when the light emitting element LD is a blue light emitting element that emits blue light and the third pixel PXL3 is a blue pixel, the light scattering layer LSL may contain at least one type (or kind) of light scattering particles SCT in order to effectively use light emitted from the light emitting element LD.

For example, the light scattering layer LSL may comprise a plurality of light scattering particles SCT dispersed in a set or predetermined matrix material (e.g., a matrix resin). As an example, the light scattering layer LSL may comprise titanium dioxide (TiO)₂) And/or light-scattering particles SCT of silica, but the structural material of the light-scattering particles SCT is not limited thereto. In some embodiments, the light scattering particles SCT are not necessarily only in the third pixel region PXA3 in which the third pixels PXL3 are formed. As an example, the light scattering particles SCT may optionally be comprised in the first color conversion layer CCL1 and/or the second color conversion layer CCL 2.

The low refractive layer LRL may be on the color conversion layer CCL. The low refractive layer LRL may be over the first to third pixels (PXL1, PXL2, and PXL 3). The low refractive layer LRL may have a relatively low refractive index compared to the color conversion layer CCL. For example, the difference between the refractive index of the low refractive layer LRL and the refractive index of the color conversion layer CCL may be 0.3 or more than 0.3, but is not limited thereto.

In some embodiments, in the process of forming the color conversion layer CCL as described above, the thickness distribution of the color conversion layer CCL may increase due to a difference in polarity between the second bank BNK2 and the ink of the color conversion layer CCL. When a step difference is formed due to the color conversion layer CCL or the like, display quality such as a color difference may be reduced due to a difference in volume of the color filter layer CFL thereon, which will be described further below. Accordingly, in the display device according to an exemplary embodiment, the spreadability of the low refractive layer LRL may be ensured to minimize or reduce a step difference due to the color conversion layer CCL or the like.

In some embodiments, the low refractive layer LRL may include a monomer represented by formula 1 below.

Formula 1

In formula 1, R₁And R₃May each independently be a substituted or unsubstituted alkyl group or hydrogen, R₂May be a substituted or unsubstituted alkylene group having two or more carbon atoms, X_a、X_bAnd X_cMay each independently be a curable functional group, and n and m may each independently be a natural number of 1 to 5. In one exemplary embodiment, the curable functional group may include at least one selected from a methacrylate group, an acrylate group, a vinyl group, and an epoxy group, but the present disclosure is not necessarily limited thereto.

When the low refractive layer LRL includes the monomer represented by formula 1, silicon (Si) atoms having low surface tension may be linearly arranged to improve spreadability on the surface thereof, and compatibility with a matrix material such as a resin may be ensured in parallel due to the T-shaped branch. The monomer may be included in a content (e.g., amount or weight) of 3 wt% to 10 wt% with respect to the solid content of the low refractive layer LRL of 100 wt%. When the monomer is contained at a content (e.g., amount or weight) of less than 3 wt%, the effect of reducing the step difference due to the low-refractive layer LRL may not be significant. In addition, when the monomer is contained at a content (e.g., amount or weight) exceeding 10 wt%, the hardness of the low-refractive layer LRL and the adhesion to a member therebelow may be reduced.

Hereinafter, the effect of reducing the step difference of the comparative examples and the examples will be described with reference to table 1. The comparative example corresponds to the case where the low refractive layer LRL does not contain a monomer, and examples 1 to 4 correspond to the cases where the low refractive layer LRL contains a monomer. In this case, example 1 corresponds to the case where the monomer may be contained in a content (e.g., amount or weight) of 1 wt% with respect to the solid content of the low refractive layer LRL of 100 wt%. Example 2 corresponds to a case where the monomer may be contained in a content (e.g., amount or weight) of 3 wt% with respect to the solid content of the low refractive layer LRL of 100 wt%. Example 3 corresponds to the case where the monomer may be contained in a content (e.g., amount or weight) of 5 wt% with respect to the solid content of the low refractive layer LRL of 100 wt%. Example 4 corresponds to the case where the monomer may be contained in a content (e.g., amount or weight) of 7 wt% with respect to the solid content of the low refractive layer LRL of 100 wt%.

TABLE 1

	Monomer content (wt%)	Step difference (mum)	Effect of reducing step Difference (%)
				Comparative example	0	2.604	-
Example 1	1	2.218	14.8
				Example 2	3	0.950	63.5
Example 3	5	0.672	74.2
				Example 4	7	0.626	76.0

The step difference was measured based on the upper surface LRLs of the low-refractive layer LRL. The expression "upper surface LRLs of the low refractive layer LRL" as used herein may mean a surface opposite to one surface covering the color conversion layer CCL. In some embodiments, heights in a third direction (Z-axis direction) from the substrate SUB to the upper surface LRLs of the low refractive layer LRL are compared with each other to measure a step difference.

As can be seen in table 1, the step difference of the low refractive layer LRL of example 1 is 2.218 μm, which is improved by about 14.8% compared to the comparative example; the step difference of example 2 was 0.950 μm, which is an improvement of about 63.5% compared to the comparative example; and the step difference for example 3 was 0.672 μm, which is an improvement of about 74.2%; and example 4 has a step difference of 0.626 μm, which is an improvement of about 76.0%. For example, according to embodiments 2 to 4, when the low refractive layer LRL includes a set or predetermined content (e.g., amount or weight) of the monomer, the spreadability of the low refractive layer LRL may be ensured to reduce the step difference thereunder.

According to an exemplary embodiment, the low refractive layer LRL may include a matrix resin and hollow particles HP dispersed in the matrix resin. The hollow particles HP may comprise hollow silica particles. According to an exemplary embodiment, the hollow particle HP may include at least one selected from the group consisting of an acrylic polymer, a polyimide polymer, a urethane polymer, a styrene polymer, a siloxane polymer, and an epoxy polymer on a surface thereof. In addition, the low refractive layer LRL may include particles selected from zinc oxide (ZnO), titanium dioxide (TiO)₂) At least one of particles, nanosilicate particles, and porogen particles, although the present disclosure is not necessarily limited thereto.

In an exemplary embodiment, the hollow particles HP may be included in a content (e.g., amount or weight) of 10 wt% to 80 wt% with respect to a solid content of the low refractive layer LRL of 100 wt%. The hollow particles HP may have a diameter of 10nm to 200nm, and the shell of the hollow particles HP may have a thickness of 5nm to 50nm, but the present disclosure is not necessarily limited thereto. According to exemplary embodiments, the low refractive layer LRL may further include at least one selected from a curing agent, a photopolymerization initiator, and an ultraviolet absorber.

As described above, when the low refractive layer LRL includes the monomer represented by formula 1 in a set or predetermined content (e.g., amount or weight), the spreadability of the low refractive layer LRL may be ensured to minimize or reduce a step difference due to the member thereunder. For example, color difference due to the thickness distribution of the color conversion layer CCL and/or the color filter layer CFL may be improved, thereby improving display quality of the display panel PNL. In addition, a separate planarization layer for reducing the step difference may be removed or omitted, thereby minimizing or reducing the thickness of the display panel PNL to improve light efficiency.

The color filter layer CFL may be on the low refractive layer LRL. The color filter layer CFL may include a color filter corresponding to a color of each pixel PXL. For example, the color filter layer CFL may include a first color filter CF1 on the first pixel PXL1 to selectively transmit light generated in the first pixel PXL1, a second color filter CF2 on the second pixel PXL2 to selectively transmit light generated in the second pixel PXL2, and a third color filter CF3 on the third pixel PXL3 to selectively transmit light generated in the third pixel PXL 3. In one exemplary embodiment, the first, second, and third color filters CF1, CF2, and CF3 may be red, green, and blue color filters, respectively, but are not limited thereto. Hereinafter, when at least one of the first color filter CF1, the second color filter CF2, and the third color filter CF3 is arbitrarily described, the color filter will be referred to as a "color filter CF", or when at least two of the color filters are collectively described, the color filter will be referred to as a "color filter CF".

The first color filter CF1 may overlap the emission area EMA of the first pixel PXL1 and may include a color filter material that selectively transmits the first color light. For example, when the first pixel PXL1 is a red color pixel, the first color filter CF1 may include a red color filter material.

The second color filter CF2 may overlap the emission area EMA of the second pixel PXL2 and may include a color filter material selectively transmitting the second color light. For example, when the second pixel PXL2 is a green color pixel, the second color filter CF2 may include a green color filter material.

The third color filter CF3 may overlap the emission area EMA of the third pixel PXL3 and may include a color filter material that selectively transmits the third color light. For example, when the third pixel PXL3 is a blue color pixel, the third color filter CF3 may include a blue color filter material.

The black matrix BM may be between the color filters CF. The black matrix BM may be in the boundary area between the pixel areas PXA so as not to overlap each emission area EMA. For example, the black matrix BM may overlap the second bank BNK 2.

The black matrix BM may contain at least one black matrix material (e.g., at least one suitable light blocking material commonly used in the art) selected from various types (or kinds) of black matrix materials and/or color filter materials having set or specific colors. Further, the black matrix BM may be made of the same (e.g., substantially the same) material as the second bank BNK2, but the disclosure is not limited thereto. For example, the black matrix BM and the second bank BNK2 may comprise the same (e.g., substantially the same) material or different materials. In some embodiments, the black matrix BM may be removed or omitted according to exemplary embodiments. In this case, the first to third color filters (CF1, CF2, and CF3) may overlap each other at the boundary between the pixel areas PXA.

The encapsulation layer ENC may be on the color filter layer CFL. The encapsulation layer ENC may cover the color filter layer CFL, the color conversion layer CCL, the display layer DPL, and the circuit layer PCL thereunder. The encapsulation layer ENC may prevent or reduce the penetration of moisture and/or air into the components below it as described above. To this end, the encapsulation layer ENC may comprise at least one inorganic layer. For example, the inorganic layer may comprise a material selected from siliconNitride (SiN)_x) Aluminum nitride (AlN)_x) Titanium nitride (TiN)_x) Silicon oxide (SiO)_x) Aluminum oxide (AlO)_x) Titanium oxide (TiO)_x) And silicon oxynitride (SiO)_xN_y) But the present disclosure is not necessarily limited thereto. Further, the encapsulation layer ENC may protect the above-described components thereunder from foreign substances such as dust. To this end, the encapsulation layer ENC may comprise at least one organic layer. For example, the organic layer may be made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, and/or polyimide resin, but the present disclosure is not necessarily limited thereto. As described above, when the encapsulation layer ENC is on the color filter layer CFL, since a separate upper substrate may be removed or omitted, the thickness of the display panel PNL may be minimized or reduced to improve light efficiency.

According to an exemplary embodiment, cover layers (CP1 and CP2) may be further on one surface and the other surface of the low refractive layer LRL, respectively. The capping layers (CP1 and CP2) may include a first capping layer CP1 and a second capping layer CP2 on one surface and the other surface of the low refractive layer LRL, respectively.

The first cover layer CP1 may be between the color conversion layer CCL and the low refractive layer LRL. The first capping layer CP1 may be over the first to third pixels (PXL1, PXL2 and PXL 3). The first cover layer CP1 may seal the color conversion layer CCL. Accordingly, it may be possible to prevent or reduce foreign substances such as external moisture and/or air from penetrating into the color conversion layer CCL to damage or contaminate the color conversion layer CCL. The first capping layer CP1 may be an inorganic layer and may be made of silicon nitride (SiN)_x) Aluminum nitride (AlN)_x) Titanium nitride (TiN)_x) Silicon oxide (SiO)_x) Aluminum oxide (AlO)_x) Titanium oxide (TiO)_x) And silicon oxynitride (SiO)_xN_y) At least one of (a).

The second cover layer CP2 may be between the low refractive layer LRL and the color filter layer CFL. The second capping layer CP2 may be over the first to third pixels (PXL1, PXL2 and PXL 3). The second capping layer CPL2 may prevent or reduce foreign substances such as external moisture and/or air from penetrating into the color filter layer CFL and/or the color conversion layer CCL to damage or contaminate the color filter layer CFL and/or the color conversion layer CCL. In addition, the second overcoat layer CP2 may prevent or reduce the colorant contained in the color filter layer CFL from diffusing into other components. The second capping layer CP2 may be an inorganic layer, and may be made of the same (e.g., substantially the same) material as the first capping layer CP1, or may contain at least one selected from materials exemplified as a structural material of the first capping layer CP 1.

According to the display device according to the exemplary embodiment described above, since the low refractive layer LRL includes the monomer represented by formula 1 in a set or predetermined content (e.g., amount or weight), the spreadability of the low refractive layer LRL may be ensured to minimize or reduce the step difference due to the member thereunder. For example, color difference due to the thickness distribution of the color conversion layer CCL and/or the color filter layer CFL may be improved, thereby improving display quality of the display panel PNL. In addition, a separate planarization layer for reducing the step difference may be removed or omitted, thereby minimizing or reducing the thickness of the display panel PNL to improve light efficiency.

Hereinafter, other exemplary embodiments will be described. In the following exemplary embodiments, the same components as those described above will be denoted by the same reference numerals, and repetitive descriptions thereof will not be repeated or will be simplified herein.

Fig. 10 is a cross-sectional view illustrating a display device according to another exemplary embodiment.

Referring to fig. 10, the display device according to the present exemplary embodiment is different from the exemplary embodiments of fig. 1 to 9 in that a low refractive layer LRL is in a region partitioned by a second bank BNK 2.

In some embodiments, the low refractive layer LRL may be inside the second bank BNK2, and may be partially in each of the first to third pixel regions (PXA1, PXA2 and PXA 3).

In this case, since the color conversion layer CCL is formed to have a height lower than the height of the second bank BNK2, even when a set or predetermined step difference is formed between the color conversion layer CCL and the second bank BNK2, the low refractive layer LRL may be in a region partitioned by the second bank BNK2, thereby minimizing or reducing the step difference generated due to the color conversion layer CCL. Accordingly, color difference generated due to the thickness distribution of the color conversion layer CCL and/or the color filter layer CFL may be improved, thereby improving display quality of the display panel PNL. In addition, a separate planarization layer for reducing the step difference may be removed or omitted, thereby minimizing or reducing the thickness of the display panel PNL to improve light efficiency, as described above.

In addition, since the low refractive layer LRL, the color conversion layer CCL, and the color filter layer CFL have already been described with reference to fig. 7, repetitive descriptions thereof will not be repeated here.

Fig. 11 is a cross-sectional view illustrating a display device according to still another exemplary embodiment.

Referring to fig. 11, the display device according to the present exemplary embodiment is different from the exemplary embodiment of fig. 1 to 9 in that an upper substrate UPL is on a substrate SUB on which pixel cells PXU are positioned.

In some embodiments, an upper substrate UPL (also referred to as "encapsulation substrate" or "color filter substrate") configured to encapsulate the first to third pixels (PXL1, PXL2, and PXL3) may be on one surface of the substrate SUB.

The upper substrate UPL may be on the color filter layer CFL, the low refractive layer LRL, and the color conversion layer CCL overlapping the first to third pixels (PXL1, PXL2, and PXL 3).

In one exemplary embodiment, a space between a lower plate of the display panel PNL including the substrate SUB and the display layer DPL and an upper plate of the display panel PNL including the upper substrate UPL, the color filter layer CFL, the low refractive index layer LRL, and the color conversion layer CCL may be filled with an overcoat layer OC having a relatively low refractive index of about 1 to about 1.6 and/or an air layer. According to an exemplary embodiment, the inorganic layer may further be between the color conversion layer CCL and the overcoat layer OC. The inorganic layer may prevent or reduce the penetration of impurities such as moisture and/or air into the color conversion layer CCL. The inorganic layer may be formed from a material selected from the group consisting of silicon nitridesSubstance (SiN)_x) Aluminum nitride (AlN)_x) Titanium nitride (TiN)_x) Silicon oxide (SiO)_x) Aluminum oxide (AlO)_x) Titanium oxide (TiO)_x) And silicon oxynitride (SiO)_xN_y) But the present disclosure is not necessarily limited thereto.

The color filter layer CFL, the low refractive layer LRL, and the color conversion layer CCL may be on one surface of the upper substrate UPL. For example, the color filter layer CFL may be formed on the upper substrate UPL, the low refractive layer LRL may be formed on the color filter layer CFL, and the color conversion layer CCL may be formed on the color filter layer CFL and the low refractive layer LRL. However, the present disclosure is not necessarily limited thereto, and the order of forming the color filter layer CFL, the low refractive layer LRL, and the color conversion layer CCL and/or the shape according to the order may be variously changed.

According to an exemplary embodiment, the black matrix BM may be between the first color filter CF1, the second color filter CF2, and the third color filter CF 3. The black matrix BM may be at the boundary between the pixel areas PXA so as not to cover each emission area EMA. For example, the black matrix BM may overlap the second bank BNK 2. In fig. 11, a case is illustrated in which the black matrix BM is on the upper substrate UPL and each of the first to third color filters (CF1, CF2, and CF3) is in a region divided by the black matrix BM, respectively, but the present disclosure is not necessarily limited thereto. In some embodiments, the first to third color filters (CF1, CF2, and CF3) may be formed on the upper substrate UPL, and the black matrix BM may be formed at the boundary between the pixel areas PXA. For example, the order of forming the color filter layer CFL and/or the position and/or shape according to the order may be variously changed according to the exemplary embodiment.

According to an exemplary embodiment, the black matrix BM may be further between the first color conversion layer CCL1, the second color conversion layer CCL2, and the light scattering layer LSL. In fig. 11, a case is illustrated in which the black matrix BM is on the low refractive layer LRL (or the first cover layer CP1) and each of the first color conversion layer CCL1, the second color conversion layer CCL2, and the light scattering layer LSL is in a region partitioned by the black matrix BM, but the present disclosure is not necessarily limited thereto. For example, when it is not necessary to first form the black matrix BM according to the processing method and/or the performance of the printing apparatus, the first color conversion layer CCL1, the second color conversion layer CCL2, and the light scattering layer LSL may be first formed, and then the black matrix BM may be formed. In some embodiments, the order of forming the color conversion layer CCL and/or the position and/or shape according to the order may be variously changed.

In addition, since the color filter layer CFL, the low refractive layer LRL, and the color conversion layer CCL have been described with reference to fig. 7, repetitive descriptions thereof will not be repeated here.

According to exemplary embodiments of the present disclosure, the spreadability of the low refractive layer may be ensured to minimize or reduce a step difference due to a member thereunder. For example, color difference due to the thickness distribution of the color conversion layer and/or the color filter layer may be improved, thereby improving display quality of the display panel. In addition, a separate planarization layer for reducing the step difference may be removed or omitted, thereby minimizing or reducing the thickness of the display panel to improve light efficiency.

Effects of the embodiments of the present disclosure are not limited to the exemplary embodiments set forth herein, and more additional effects and embodiments are included in the present specification.

It will be apparent to those skilled in the art that various modifications to the exemplary embodiments of the disclosure are possible without departing from the essential characteristics of the disclosure. Accordingly, the above-described embodiments should be construed as illustrative, and not restrictive. It is intended that the scope of the disclosure be defined by the following claims, and all equivalents thereof fall within the scope of the disclosure.

Claims (10)

1. A display device, comprising:

a plurality of light emitting elements;

a color conversion layer on the light emitting element; and

a low refractive layer on the color conversion layer,

wherein the low refractive layer comprises a monomer represented by formula 1 below:

formula 1

Wherein, in formula 1, R₁And R₃Each independently being a substituted or unsubstituted alkyl group or hydrogen, R₂Is a substituted or unsubstituted alkylene radical having two or more carbon atoms, X_a、X_bAnd X_cEach independently is a curable functional group, and n and m are each independently a natural number from 1 to 5.

2. The display device according to claim 1, wherein the monomer is contained in an amount of 3 wt% to 10 wt% with respect to 100 wt% of a solid content of the low refractive layer.

3. The display device of claim 1, wherein the low refractive layer further comprises hollow particles.

4. The display device according to claim 3, wherein the hollow particles are contained in an amount of 10 wt% to 80 wt% with respect to 100 wt% of a solid content of the low refractive layer.

5. The display device of claim 1, wherein the curable functional group comprises at least one selected from a methacrylate group, an acrylate group, a vinyl group, and an epoxy group.

6. The display device of claim 1, further comprising an inorganic layer between the color conversion layer and the low refractive layer.

7. The display device of claim 1, further comprising a color filter layer overlapping the color conversion layer,

wherein the low refractive layer is between the color conversion layer and the color filter layer.

8. The display device of claim 7, further comprising an inorganic layer between the color filter layer and the low refractive layer.

9. The display device according to claim 8, wherein the inorganic layer comprises at least one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and titanium oxide.

10. The display device according to claim 1, wherein the color conversion layer comprises a matrix resin and quantum dots dispersed in the matrix resin.

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