CN114068521A - Luminous test control circuit and display panel - Google Patents
Luminous test control circuit and display panel Download PDFInfo
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- CN114068521A CN114068521A CN202111328720.7A CN202111328720A CN114068521A CN 114068521 A CN114068521 A CN 114068521A CN 202111328720 A CN202111328720 A CN 202111328720A CN 114068521 A CN114068521 A CN 114068521A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 133
- 238000005468 ion implantation Methods 0.000 claims abstract description 83
- 230000004888 barrier function Effects 0.000 claims abstract description 32
- 150000002500 ions Chemical class 0.000 claims abstract description 22
- 238000004020 luminiscence type Methods 0.000 claims abstract description 4
- 230000000903 blocking effect Effects 0.000 claims description 37
- 125000006850 spacer group Chemical group 0.000 claims description 12
- 238000003475 lamination Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 13
- 230000008569 process Effects 0.000 description 13
- 230000003068 static effect Effects 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 12
- 230000000694 effects Effects 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
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Abstract
The invention discloses a light-emitting test control circuit and a display panel, wherein the light-emitting test control circuit comprises: the transistor comprises a first pole, a second pole and a third pole; the electrostatic discharge unit comprises a lamination of a semiconductor resistance layer and an ion implantation barrier layer, wherein the ion implantation barrier layer is used for preventing ions from being implanted into the semiconductor resistance layer, and the semiconductor resistance layer is used for electrically connecting the third pole and the first pole. The technical scheme provided by the embodiment of the invention improves the temperature stability of the luminescence test control circuit.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a light emitting test control circuit and a display panel.
Background
The transistors of the existing luminescence test control circuit may be damaged due to static charges in the transistor preparation working process and the subsequent process, so that the temperature stability of the control circuit for luminescence test is not good.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a lighting test control circuit and a display panel, so as to improve the temperature stability of the control circuit for lighting test.
The embodiment of the invention provides a light-emitting test control circuit, which comprises: the transistor comprises a first pole, a second pole and a third pole; the electrostatic discharge unit comprises a semiconductor resistance layer and an ion implantation barrier layer, wherein the ion implantation barrier layer is used for preventing ions from being implanted into the semiconductor resistance layer, and the semiconductor resistance layer is used for connecting the third pole and the first pole.
According to the technical scheme, the semiconductor resistor layer is equivalent to a resistor and used for connecting the third pole and the first pole, and the semiconductor resistor layer can achieve the effect of reducing static charges in the transistor, so that the transistor can be prevented from being damaged by the static charges. The electrostatic discharge unit comprises a lamination of a semiconductor resistance layer and an ion implantation barrier layer, the ion implantation barrier layer is used for preventing ions from being implanted into the semiconductor resistance layer, the problem that the resistance value of the semiconductor resistance layer is reduced due to the fact that the ion implantation barrier layer is not arranged and ions are implanted is avoided, the resistance value of the semiconductor resistance layer is increased through the ion implantation barrier layer arranged in the lamination, particularly after the temperature is increased, the resistance value of the semiconductor resistance layer prevents the third electrode from being conducted with the first electrode after the resistance value is reduced after ions are implanted, a condition that causes a test control signal received by the third pole to be transmitted from the third pole to the first pole, such that the transistor is under control of the test control signal, the light emitting test signal can be provided to the data line from the second electrode through the source electrode, and the temperature stability of the control circuit for the light emitting test is further improved. In addition, the technical scheme increases the resistance value of the semiconductor resistance layer, and can also increase the capacity of the static discharge unit for transmitting large current, thereby improving the discharge capacity of static charges.
Optionally, the transistor further includes a semiconductor active layer, the semiconductor resistance layer and the semiconductor active layer are located in the same layer, and the ion implantation blocking layer is configured to block ions doped in the semiconductor active layer from being implanted into the semiconductor resistance layer, so that an ion doping concentration of the semiconductor resistance layer is smaller than an ion doping concentration of the semiconductor active layer.
According to the technical scheme, the semiconductor active layer of the semiconductor resistance layer and the semiconductor active layer of the transistor are located on the same layer, when the semiconductor active layer is subjected to ion doping through an ion implantation process, the ion implantation barrier layer can prevent ions from being implanted into the semiconductor resistance layer, so that the resistance value of the semiconductor resistance layer is increased, particularly, the resistance value of the semiconductor resistance layer after temperature rise is increased, the condition that a test control signal received by a third pole is transmitted to a first pole from the third pole after the third pole and the first pole are conducted is avoided, the transistor can be controlled by the test control signal, the light-emitting test signal can be provided for a data line through the first pole and the second pole, and the temperature stability of a control circuit for light-emitting test is further improved. In addition, the technical scheme increases the resistance value of the semiconductor resistance layer, and can also increase the capacity of the static discharge unit for transmitting large current, thereby improving the discharge capacity of static charges.
Optionally, the ion implantation blocking layer and the third electrode are located in the same layer.
According to the technical scheme, the ion implantation barrier layer and the third electrode are located on the same layer, the ion implantation barrier layer can be manufactured while the third electrode is manufactured, the process conditions are simplified, and the manufacturing cost is reduced.
Optionally, the ion implantation barrier layer partially covers the semiconductor resistance layer.
Optionally, the ion implantation blocking layer entirely covers the semiconductor resistance layer.
According to the technical scheme, the ion implantation barrier layer can be limited to partially cover the semiconductor resistor layer, and the ion implantation barrier layer can be limited to completely cover the semiconductor resistor layer, so that the effect that the ion implantation barrier layer prevents ions from being implanted into the semiconductor resistor layer when the ion implantation process is used for carrying out ion doping on the semiconductor active layer is controlled, and the resistance value of the semiconductor resistor layer is further controlled.
Optionally, the electrostatic discharge unit further includes an insulating spacer layer, and the insulating spacer layer is located between the semiconductor resistive layer and the ion implantation blocking layer.
The technical scheme is used for realizing the electric insulation between the semiconductor resistance layer and the ion implantation barrier layer.
Optionally, the ion implantation blocking layer comprises a conductive layer;
the ion implantation barrier layer is used for inputting potential control signals through the conductive connecting end.
This technical scheme, the ion implantation barrier layer is used for passing through the current connection end input electric potential control signal, can be through the voltage size and the polarity of adjusting electric potential control signal, adjust the semiconductor resistor layer, the equivalent capacitance value that insulating spacer layer and ion implantation barrier layer constitute, and then adjust the electric potential of semiconductor resistor layer, increase the equivalent resistance between third pole and the first utmost point, after having avoided third pole and first utmost point to switch on, the test control signal that leads to the third pole to receive transmits the condition to the first utmost point from the third pole, make the transistor under test control signal's control, can realize providing the data line with luminous test signal by the second utmost point through the source, and then further improved the temperature stability who is used for the control circuit of luminous test.
Optionally, a third pole connection layer is further included, and the third pole connection layer is used for connecting the third pole and the semiconductor resistance layer;
the resistivity of the third pole connection layer is smaller than that of the third pole;
preferably, the third pole connecting layer and the first pole are located at the same layer.
According to the technical scheme, the resistivity of the third pole connecting layer is smaller than that of the third pole, and the third pole connecting layer can be in better ohmic contact with the semiconductor resistor layer, so that rapid discharge of static charges is facilitated.
Preferably, the third pole connecting layer and the first pole are located on the same layer, and the third pole connecting layer is manufactured while the first pole is manufactured, so that the preparation process is simplified, and the manufacturing cost is reduced.
Optionally, the resistor further comprises a first electrode connecting layer for connecting the first electrode and the semiconductor resistor layer;
preferably, the first pole connection layer and the first pole are located at the same layer.
According to the technical scheme, the first pole connecting layer is used for connecting the first pole and the semiconductor resistor layer, so that the phenomenon that the manufacturing area of the first pole is too large is avoided, and the size standardization of a transistor in the display panel is not facilitated.
Preferably, the first pole connecting layer and the first pole are positioned on the same layer, and the first pole connecting layer is manufactured while the first pole is manufactured, so that the preparation process is simplified, and the manufacturing cost is reduced.
Optionally, the first electrode is a source electrode, the second electrode is a drain electrode, and the third electrode is a gate electrode.
In the technical scheme, a test control signal of the light-emitting test control circuit acts on the grid electrode G, and a light-emitting test signal of the control circuit is supplied to the data line from the drain electrode D through the source electrode S.
The embodiment of the invention also provides a display panel which comprises the light-emitting test control circuit in any technical scheme.
This technical scheme includes above-mentioned technical scheme's luminous test control circuit, be used for preventing ion implantation to in the semiconductor resistance layer through the ion implantation barrier layer, thereby increased the resistance value of semiconductor resistance layer, especially increased the resistance value of semiconductor resistance layer after the temperature risees, avoided third pole and first utmost point to switch on after, lead to the condition that the test control signal that the third pole received transmits the first utmost point from the third pole, make the transistor under test control signal's control, can realize providing the data line with luminous test signal by the second utmost point through the source electrode, and then improved luminous test circuit's in the display panel temperature stability.
According to the technical scheme provided by the embodiment of the invention, the semiconductor resistor layer is equivalent to a resistor for connecting the third pole and the first pole, and the semiconductor resistor layer can realize the function of discharging static charges in the transistor, so that the transistor can be prevented from being damaged by the static charges. The electrostatic discharge unit comprises a semiconductor resistance layer and an ion injection barrier layer, the ion injection barrier layer is used for preventing ions from being injected into the semiconductor resistance layer, so that the resistance value of the semiconductor resistance layer is increased, particularly the resistance value of the semiconductor resistance layer after the temperature rises is increased, the condition that a test control signal received by a third pole is transmitted to a first pole from a grid after the third pole and the first pole are conducted is avoided, the transistor can realize that a light-emitting test signal is provided for a data line through the first pole and the second pole under the control of the test control signal, and the temperature stability of a control circuit for light-emitting test is further improved. In addition, the technical scheme increases the resistance value of the semiconductor resistance layer, and can also increase the capacity of the static discharge unit for transmitting large current, thereby improving the discharge capacity of static charges.
Drawings
Fig. 1 is a schematic structural diagram of a transistor of a lighting test control circuit according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of the transistor shown in FIG. 1;
fig. 3 is a top view of a lighting test control circuit according to an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view of the light emission test control circuit shown in FIG. 3;
FIG. 5 is a top view of the lighting test control circuit of FIG. 3;
FIG. 6 is a schematic cross-sectional view of another light-emitting test control circuit shown in FIG. 3;
FIG. 7 is another top view of the lighting test control circuit of FIG. 3;
fig. 8 is a top view of the lighting test control circuit of fig. 3.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As described in the above-mentioned background art, the temperature stability of the transistor of the existing control circuit for the light emission test is not good. Referring to fig. 1 and 2, the inventor has conducted a detailed study and then provided an electrostatic discharge unit 10 in a lighting test control circuit. Wherein the control circuit for the lighting test includes a transistor T1, fig. 1 and 2 show only one transistor T1 and the electrostatic discharge cells 10 disposed in one-to-one correspondence with the transistors T1. The inventor adopts the semiconductor resistor layer 11 as the electrostatic discharge unit 10, and the semiconductor resistor layer 11 is equivalent to a resistor R which is connected in series between the gate G and the source S of the transistor T1, and can play a role in reducing the electrostatic charge generated in the transistor T1 during the manufacturing process and the subsequent process. The inventors have conducted studies to find that the semiconductor resistive layer 11 is also subjected to an ion implantation process of the same ion concentration while the semiconductor active layer 20 of the transistor T1 is subjected to ion implantation to form source and drain regions. As the temperature increases, the resistance value of the semiconductor resistance layer 11 decreases due to ion implantation, so that the gate G and the source S are turned on, causing the test control signal received by the gate G to be transmitted from the gate G to the source S, so that the transistor T1 cannot implement the supply of the light emitting test signal from the drain D to the data line through the source S, resulting in poor temperature stability of the control circuit for the light emitting test.
Aiming at the new technical problem of the technical scheme, the embodiment of the invention provides the following technical scheme: the light emission test control circuit includes: the transistor comprises a first pole, a second pole and a third pole; the electrostatic discharge unit comprises a semiconductor resistance layer and an ion implantation barrier layer, wherein the ion implantation barrier layer is used for preventing ions from being implanted into the semiconductor resistance layer, and the semiconductor resistance layer is connected with the third pole and the first pole.
Alternatively, referring to fig. 4 and 5, the first electrode is a source S, the second electrode is a drain D, the third electrode is a gate G, the test control signal of the lighting test control circuit acts on the gate G, and the lighting test signal of the lighting test control circuit is provided to the data line from the drain D through the source S. It should be noted that, in the embodiment of the present invention, the first pole is the source S, the second pole is the drain D, and the third pole is the gate G, but the first pole of the embodiment of the present invention is not limited to the source S, the second pole is not limited to the drain D, and the third pole is not limited to the gate G.
Illustratively, referring to fig. 3-5, the lighting test control circuit includes: a lighting test control circuit 001, the lighting test control circuit 001 comprising a transistor T1 and an electrostatic discharge unit 10 disposed corresponding to the transistor T1, the transistor T1 comprising a first pole, e.g., a source S, a second pole, e.g., a drain D, and a third pole, e.g., a gate G; the electrostatic discharge unit 10 includes a stack of a semiconductor resistor layer 11 and an ion implantation barrier layer 12, the ion implantation barrier layer 12 is used for preventing ions from being implanted into the semiconductor resistor layer 11, and the semiconductor resistor layer 11 is used for connecting a third pole, such as a gate G, and a first pole, such as a source S. It should be noted that fig. 4 does not show the connection relationship between the semiconductor resistor layer 11 and the third and first poles, and specific connection relationship can be seen from fig. 5, in fig. 5, the semiconductor resistor layer 11 is connected to the third pole through the third pole connection layer GL, and the semiconductor resistor layer 11 is connected to the first pole through the first pole connection layer GL.
It should be noted that only one transistor T1 and the electrostatic discharge unit 10 disposed corresponding to the transistor T1 are shown in the embodiment of the present invention. Referring to fig. 3, the array substrate includes a display area a1 and a non-display area a2, and a plurality of sub-pixels are located in the display area a 1. The light emission test control circuit 001 is located in the non-display area a 2. A light emitting test signal is supplied from the drain electrode D to the data line through the source electrode S, and a scan driving circuit (not shown) may supply a scan signal to the scan line. It can be known that before installing a driving integrated circuit (not shown) with a built-in data driving circuit, the light emission test control circuit 001 is required to provide a light emission test signal for the data line to test whether the sub-pixel can emit light normally, and if the temperature stability of the transistor T1 is not good, the result of the test whether the sub-pixel can emit light normally is not accurate.
Exemplarily, 4 scan lines and 4 data lines are shown in fig. 3, and the scan lines are the first scan line S1, the second scan line S2, the third scan line S3, and the fourth scan line S4, respectively. The data lines are a first data line D1, a second data line D2, a third data line D3, and a fourth data line D4, respectively.
It should be noted that the transistor T1 in the embodiment of the present invention may be an NMOS transistor or a PMOS transistor. Optionally, the transistor T1 is a low temperature polysilicon thin film transistor, which has the advantages of high switching speed, thinner and smaller thin film circuit, and lower power consumption. The semiconductor active layer 20 of the low temperature polysilicon thin film transistor is a polysilicon semiconductor layer.
According to the technical scheme provided by the embodiment of the invention, the semiconductor resistor layer 11 is equivalent to the resistor R for connecting the third pole, such as the gate G, and the first pole, such as the source S, and the semiconductor resistor layer 11 can reduce the electrostatic charge in the transistor T1, so that the transistor T1 can be prevented from being damaged by the electrostatic charge. The electrostatic discharge unit 10 includes a stack of a semiconductor resistor layer 11 and an ion implantation blocking layer 12, the ion implantation blocking layer 12 is used for blocking ion implantation into the semiconductor resistor layer 11, so as to increase a resistance value of the semiconductor resistor layer 11, especially increase a resistance value of the semiconductor resistor layer 11 after a temperature rise, and avoid a situation that a test control signal received by a third pole, for example, a gate G, is transmitted from the third pole, for example, the gate G, to a first pole, for example, a source S, after the third pole, for example, the gate G, and the first pole, for example, the source S, are turned on, so that the transistor T1 can realize that a light emitting test signal is provided to a data line from a second pole, for example, a drain D, through the first pole, for example, the source S, under control of the test control signal, thereby improving temperature stability of the light emitting test control circuit. In addition, the above technical solution increases the resistance value of the semiconductor resistance layer 11, and also increases the capability of the electrostatic discharge unit 10 to transmit large current, thereby improving the electrostatic discharge capability.
Alternatively, referring to fig. 4 and 5, the transistor T1 further includes a semiconductor active layer 20, the semiconductor resistive layer 11 and the semiconductor active layer 20 are located in the same layer, and the ion implantation blocking layer 12 is used to block the ion implantation of the semiconductor active layer 20 into the semiconductor resistive layer 11, so that the ion doping concentration of the semiconductor resistive layer 11 is less than the ion doping concentration of the semiconductor active layer 20.
Specifically, referring to fig. 4, the semiconductive resistor layer 11 and the semiconductive active layer 20 of the transistor T1 are located at the same layer, when the source and drain regions of the semiconductor active layer 20 are ion-doped by the ion implantation process, the ion implantation blocking layer 12 may prevent the ion implantation into the semiconductor resistance layer 11, thereby increasing the resistance of the semiconducting resistance layer 11, in particular the resistance of the semiconducting resistance layer 11 after a temperature rise, avoiding that after the third pole e.g. the gate G and the first pole e.g. the source S are switched on, resulting in the transmission of the test control signal received at the gate G from the gate G to the source S, so that the transistor T1, under the control of the test control signal, the light emitting test signal can be supplied to the data line from the drain electrode D through the source electrode S, and the temperature stability of the control circuit for the light emitting test is further improved. In addition, the above technical solution increases the resistance value of the semiconductor resistance layer 11, and also increases the capability of the electrostatic discharge unit 10 to transmit large current, thereby improving the electrostatic discharge capability.
Illustratively, the doping of the semiconductor active layer 20 may be followed by a P-type semiconductor or an N-type semiconductor.
Alternatively, referring to fig. 4, the ion implantation blocking layer 12 and the third electrode are, for example, the gate G at the same layer.
Specifically, the ion implantation blocking layer 12 and the third electrode are, for example, the gate G is located in the same layer, and the manufacturing of the ion implantation blocking layer 12 can be completed while the gate G is manufactured, so that the process conditions are simplified, and the manufacturing cost is reduced. It should be noted that after the gate G and the ion implantation blocking layer 12 are prepared, a separate mask may be used, or the gate G may be used as a mask, when the source and drain regions of the semiconductor active layer 20 are ion-doped by the ion implantation process, the ion implantation blocking layer 12 may prevent the ion implantation into the semiconductor resistance layer 11, thereby increasing the resistance value of the semiconductive resistance layer 11, particularly, the resistance value of the semiconductive resistance layer 11 after a temperature rise, and preventing the gate G and the source S from being turned on, resulting in the transmission of the test control signal received at the gate G from the gate G to the source S, so that the transistor T1, under the control of the test control signal, the light emitting test signal can be supplied to the data line from the drain electrode D through the source electrode S, and the temperature stability of the control circuit for the light emitting test is further improved.
Alternatively, referring to fig. 4 and 5, the ion implantation barrier layer 12 partially covers the semiconductor resistive layer 11.
Alternatively, referring to fig. 6 and 7, the ion implantation blocking layer 12 entirely covers the semiconductor resistive layer 11.
After the third electrode, for example, the gate electrode G and the ion implantation blocking layer 12 are prepared, when the semiconductor active layer 20 is ion-doped by the ion implantation process, the ion implantation blocking layer 12 may prevent the ion implantation into the semiconductor resistance layer 11, thereby increasing the resistance value of the semiconductor resistance layer 11. Specifically, the ion implantation blocking layer 12 is controlled to block the ion implantation into the semiconductor resistance layer 11 according to the area of the ion implantation blocking layer 12 covering the semiconductor resistance layer 11, so as to increase the specific numerical range of the resistance value of the semiconductor resistance layer 11. The larger the area of the ion implantation blocking layer 12 covering the semiconductor resistance layer 11 is, the better the ion implantation blocking layer 12 has the effect of blocking ion implantation into the semiconductor resistance layer 11 when the semiconductor active layer 20 is ion-doped by the ion implantation process is, and the larger the resistance value of the semiconductor resistance layer 11 is. In summary, in the embodiment of the present invention, the ion implantation blocking layer 12 may be defined to partially cover the semiconductor resistance layer 11, and the ion implantation blocking layer 12 may be defined to completely cover the semiconductor resistance layer 11, so as to control an effect of the ion implantation blocking layer 12 blocking ion implantation into the semiconductor resistance layer 11 when the ion implantation process is performed on the semiconductor active layer 20, and further control a resistance value of the semiconductor resistance layer 11.
Optionally, referring to fig. 4 and 6, the electrostatic discharge unit 10 further includes an insulating spacer layer 101, and the insulating spacer layer 101 is located between the semiconductor resistor layer 11 and the ion implantation blocking layer 12.
Illustratively, the insulating spacer 101 may be silicon nitride, silicon oxide, or a stack of silicon nitride and silicon oxide, and is used to electrically insulate the semiconductor resistor layer 11 from the ion implantation barrier layer 12. Wherein, when the ion implantation blocking layer 12 and the gate electrode G are located in the same layer and fabricated at the same time, the insulating spacer layer 101 is used as an insulating layer, for example, a gate insulating layer, for electrically insulating the third electrode, for example, the gate electrode G, from the semiconductor active layer 20.
Alternatively, referring to fig. 4 and 6, the array substrate further includes a substrate 100 for supporting the entire display panel. The lighting test control circuit further comprises an insulating layer 102 for electrically insulating the third pole, e.g. the gate G, from the first pole, e.g. the source S, and from the second pole, e.g. the drain D.
Alternatively, referring to fig. 8, the ion implantation blocking layer 12 includes a conductive layer; the ion implantation barrier layer 12 is used to input a potential control signal through the conductive connection 13 of the conductive layer.
Referring to fig. 8, the ion implantation blocking layer 12 is configured to input a potential control signal through the conductive connection end 13, and may adjust an equivalent capacitance value formed by the semiconductor resistance layer 11, the insulating spacer layer 101, and the ion implantation blocking layer 12 by adjusting a voltage magnitude and a polarity of the potential control signal, so as to adjust a potential of the semiconductor resistance layer 11, to increase an equivalent resistance between the third pole, for example, the gate G and the first pole, for example, the source S, and to avoid a situation that a test control signal received by the gate G is transmitted from the gate G to the source S after the gate G and the source S are turned on, so that the transistor T1 may provide a light emitting test signal to the data line through the source S and the drain D under the control of the test control signal, thereby further improving the temperature stability of the light emitting test control circuit.
Optionally, referring to fig. 5, 7 and 8, a third electrode connecting layer, for example, a gate connecting layer GL, is further included, and the gate connecting layer GL is used for connecting the third electrode, for example, a gate G, and the semiconductor resistor layer 11; the resistivity of the gate connection layer GL is smaller than that of the gate G; preferably, the third pole connection layer, e.g. the gate connection layer GL, and the first pole, e.g. the source S, are located in the same layer and are fabricated simultaneously.
Specifically, the resistivity of the third electrode connection layer, such as the gate connection layer GL, is smaller than the resistivity of the third electrode connection layer, such as the gate G, and the gate connection layer GL can make a better ohmic contact with the semiconductor resistor layer 11, which is beneficial to the rapid discharge of static charges.
Preferably, the third electrode connection layer, such as the gate connection layer GL, and the first electrode, such as the source electrode S, are simultaneously formed in the same layer, and the gate connection layer GL is formed simultaneously with the source electrode S, so that the manufacturing process is simplified and the manufacturing cost is reduced.
It should be noted that the gate connecting layer GL and the source S are located in the same layer, an insulating spacer layer 101 and an insulating layer 102 are disposed between the gate connecting layer GL and the semiconductor resistor layer 11 at intervals, and the gate connecting layer GL may be connected to the semiconductor resistor layer 11 through a through hole.
Optionally, referring to fig. 5, 7 and 8, a first pole connection layer, for example, a source connection layer SL, is further included, and the first pole connection layer, for example, the source connection layer SL, connects the first pole, for example, the source S, and the semiconductor resistance layer 11; preferably, the first pole connection layer, e.g. the source connection layer SL, and the first pole, e.g. the source S, are located in the same layer and are fabricated simultaneously.
Specifically, the source connecting layer SL is used to connect the source S and the semiconductor resistor layer 11, so that the source S is prevented from being manufactured in an excessively large area, which is not favorable for realizing the size standardization of the transistor T1 in the display panel.
Preferably, the source electrode connecting layer SL and the source electrode S are positioned on the same layer and are manufactured at the same time, and the source electrode connecting layer SL is manufactured at the same time of manufacturing the source electrode S, so that the manufacturing process is simplified, and the manufacturing cost is reduced.
It should be noted that the source connecting layer SL and the source S are formed at the same time and on the same layer, the insulating spacer layer 101 and the insulating layer 102 are provided at an interval between the source connecting layer SL and the semiconductor resistance layer 11, and the source connecting layer SL may be connected to the semiconductor resistance layer 11 through a through hole.
The embodiment of the invention also provides a display panel which comprises the light-emitting test control circuit in any of the technical schemes. The display panel provided by the embodiment of the invention can be applied to display equipment with a display function, such as mobile phones, computers, intelligent wearable equipment and the like, and the embodiment of the invention is not limited to the display equipment.
The display panel provided by the embodiment of the invention comprises the light emitting test control circuit provided by the embodiment of the invention, has the same functions and effects, and is not repeated herein.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A lighting test control circuit, comprising:
the electrostatic discharge device comprises a transistor and an electrostatic discharge unit correspondingly connected with the transistor, wherein the transistor comprises a first pole, a second pole and a third pole;
the electrostatic discharge unit comprises a semiconductor resistance layer and an ion implantation barrier layer, wherein the ion implantation barrier layer is used for preventing ions from being implanted into the semiconductor resistance layer, and the semiconductor resistance layer is used for connecting the third pole and the first pole.
2. The lighting test control circuit of claim 1, wherein the transistor further comprises a semiconductor active layer, the semiconductor resistive layer and the semiconductor active layer are located in the same layer, and the ion implantation blocking layer is configured to block ions doped in the semiconductor active layer from being implanted into the semiconductor resistive layer.
3. The lighting test control circuit of claim 1, wherein the ion implantation blocking layer and the third pole are in the same layer.
4. The lighting test control circuit of claim 1, wherein the ion implantation blocking layer partially covers or completely covers the semiconducting resistive layer.
5. The lighting test control circuit of claim 1, wherein the electrostatic discharge unit further comprises an insulating spacer layer, the insulating spacer layer being located between the semiconductor resistive layer and the ion implantation blocking layer.
6. The luminescence test control circuit of claim 5, wherein the ion implantation blocking layer comprises a conductive layer;
the ion implantation barrier layer is used for inputting potential control signals through the conductive connecting end.
7. The lighting test control circuit of claim 1, further comprising a third pole connection layer connecting the third pole and the semiconductor resistive layer;
the resistivity of the third pole connection layer is smaller than that of the third pole;
preferably, the third pole connecting layer and the first pole are located at the same layer.
8. The lighting test control circuit of claim 1, further comprising a first pole connection layer for connecting the first pole and the semiconducting resistive layer;
preferably, the first pole connection layer and the first pole are located at the same layer.
9. The lighting test control circuit of any one of claims 1-8, wherein the first pole is a source, the second pole is a drain, and the third pole is a gate.
10. A display panel comprising the light emission test control circuit according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111328720.7A CN114068521A (en) | 2021-11-10 | 2021-11-10 | Luminous test control circuit and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111328720.7A CN114068521A (en) | 2021-11-10 | 2021-11-10 | Luminous test control circuit and display panel |
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| Publication Number | Publication Date |
|---|---|
| CN114068521A true CN114068521A (en) | 2022-02-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111328720.7A Pending CN114068521A (en) | 2021-11-10 | 2021-11-10 | Luminous test control circuit and display panel |
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| Country | Link |
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| CN (1) | CN114068521A (en) |
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