CN114068451A - Interconnect structure and method of forming the same - Google Patents

Interconnect structure and method of forming the same Download PDF

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Publication number
CN114068451A
CN114068451A CN202010748137.0A CN202010748137A CN114068451A CN 114068451 A CN114068451 A CN 114068451A CN 202010748137 A CN202010748137 A CN 202010748137A CN 114068451 A CN114068451 A CN 114068451A
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layer
dielectric layer
conductive
forming
substrate
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金吉松
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The application provides an interconnection structure and a forming method thereof, wherein the forming method comprises the following steps: providing a substrate, wherein a first through hole is formed in the substrate; forming a first conductive material layer, wherein the first conductive material layer fills the first through hole and covers the surface of the substrate; forming a dielectric material layer on the surface of the first conductive material layer; patterning the dielectric material layer and the first conductive material layer, exposing part of the surface of the substrate, and forming a dielectric layer and a first conductive layer; forming an interlayer dielectric layer on the surface of the exposed substrate, wherein the top surface of the interlayer dielectric layer is coplanar with the top surface of the dielectric layer; and selectively removing part of the dielectric layer to form a second through hole, wherein the second through hole is aligned in the width direction of the first conductive layer and exposes part of the surface of the first conductive layer. The technical scheme of the application can effectively solve the problem of misalignment of the through holes and greatly improve the yield of products.

Description

Interconnect structure and method of forming the same
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to an interconnect structure and a method for forming the same.
Background
With the development of semiconductor technology, the requirement for the integration level of an integrated circuit chip is higher and higher, and the manufacturing difficulty of an interconnection structure is higher and higher.
In the conventional technology, vias are generally used to connect upper metal lines and lower metal lines, but the formed vias are often misaligned, which increases the via resistance and may even cause short circuit problems with the wrong metal line, so how to completely align the vias and connect the upper metal lines and the lower metal lines is a core problem in forming the interconnection structure.
Disclosure of Invention
The technical problem solved by the present application is to provide an interconnect structure and a method for forming the same, in which a via of the interconnect structure can be completely aligned and connected to an upper layer metal line and a lower layer metal line.
In order to solve the above technical problem, the present application provides a method for forming an interconnect structure, including: providing a substrate, wherein a first through hole is formed in the substrate; forming a first conductive material layer, wherein the first conductive material layer fills the first through hole and covers the surface of the substrate; forming a dielectric material layer on the surface of the first conductive material layer; patterning the dielectric material layer and the first conductive material layer, exposing part of the surface of the substrate, and forming a dielectric layer and a first conductive layer; forming an interlayer dielectric layer on the surface of the exposed substrate, wherein the top surface of the interlayer dielectric layer is coplanar with the top surface of the dielectric layer; and selectively removing part of the dielectric layer to form a second through hole, wherein the second through hole is aligned in the width direction of the first conductive layer and exposes part of the surface of the first conductive layer.
In an embodiment of the present application, a process of forming a dielectric layer and a first conductive layer includes: forming a patterned mask layer on the surface of the dielectric material layer; and sequentially etching part of the dielectric material layer and the first conductive material layer by taking the patterned mask layer as a mask, exposing part of the surface of the substrate, and forming the dielectric layer and the first conductive layer.
In the embodiment of the present application, the process for forming the interlayer dielectric layer includes: forming an interlayer dielectric material layer on the surface of the patterned mask layer and the exposed surface of the substrate; and removing part of the interlayer dielectric material layer and the patterned mask layer to enable the interlayer dielectric material layer and the top surface of the dielectric layer to be coplanar to form an interlayer dielectric layer.
In an embodiment of the present invention, the process of selectively removing a portion of the dielectric layer to form the second via includes: forming photoresist layers on the surfaces of the interlayer dielectric layer and the dielectric layer; patterning the photoresist layer to expose a portion of the dielectric layer; and etching the exposed dielectric layer by taking the photoresist layer as a mask to form a second through hole.
In the embodiment of the application, the dielectric layer and the interlayer dielectric layer are made of different materials, and when the exposed dielectric layer is etched, the dielectric layer can only be corroded by the adopted etching solvent.
In an embodiment of the present application, the material of the dielectric layer comprises SiO2、SiN、Al2O3AlN, SiCN or SiOC, the material of the interlayer dielectric layer comprises SiO2、SiN、Al2O3At least one of AlN, SiCN, SiOC and low-K material.
In an embodiment of the present application, the method for forming an interconnect structure further includes: and forming a second conductive layer, wherein the second conductive layer fills the second through hole and covers the surfaces of the interlayer dielectric layer and the conductive dielectric layer.
In an embodiment of the present application, a material of the first conductive layer and the second conductive layer includes at least one of Cu, Ta, TaN, Co, Ru, RuN, Ti, and TiN.
In order to solve the above technical problem, the present application further provides an interconnect structure, including: a substrate having a first via formed therein; the first conducting layer is filled in the first through hole and covers part of the surface of the substrate; a dielectric layer on a surface of the first conductive layer, wherein a second through hole is formed in the dielectric layer, and the second through hole is aligned in a width direction of the first conductive layer and exposes a part of the surface of the first conductive layer; and the interlayer dielectric layer is positioned on the surface of the substrate, and the top surface of the interlayer dielectric layer is coplanar with the top surface of the dielectric layer.
In the embodiment of the application, the interlayer dielectric layer has a gap.
In the embodiment of the application, the dielectric layer and the interlayer dielectric layer are made of different materials.
In an embodiment of the present application, the material of the dielectric layer comprises SiO2、SiN、Al2O3AlN, SiCN or SiOC, the material of the interlayer dielectric layer comprises SiO2、SiN、Al2O3At least one of AlN, SiCN, SiOC and low-K material.
In an embodiment of the present application, the interconnect structure further includes: and the second through hole is filled with the second conducting layer, and the surfaces of the interlayer dielectric layer and the dielectric layer are covered with the second conducting layer.
In the embodiment of the application, a front conductive layer is also formed in the substrate, and the first through hole is aligned in the width direction of the front conductive layer and exposes a part of the surface of the front conductive layer.
Compared with the prior art, the technical scheme of the application has the following beneficial effects:
according to the forming method of the interconnection structure, the first conductive material layer is formed in the first through hole and on the surface of the substrate, the dielectric material layer is formed on the surface of the first conductive material layer, then the dielectric material layer and the first conductive material layer are patterned to expose parts of the surface of the substrate, the dielectric layer and the first conductive layer are formed, the interlayer dielectric layer is formed on the surface of the exposed substrate, and finally, part of the dielectric layer is selectively removed without affecting the structure of the interlayer dielectric layer, so that the formed second through hole is aligned in the width direction of the first conductive layer and exposes parts of the surface of the first conductive layer, the problem of misalignment of the through hole is effectively solved, and the product yield is greatly improved.
Furthermore, by making the materials of the dielectric layer and the interlayer dielectric layer different, when the dielectric layer is selectively etched in the subsequent process, the etching solvent can only corrode the dielectric layer without affecting the structure of the interlayer dielectric layer, so that the formed second through hole is aligned to the surface of the first conductive layer in the width direction of the first conductive layer.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:
FIG. 1 is a schematic diagram of an interconnect structure;
fig. 2 is a schematic flow chart illustrating a method for forming an interconnect structure according to an embodiment of the present disclosure;
fig. 3a to 3c, fig. 4a to 4c, fig. 5a to 5c, fig. 6a to 6c, fig. 7a to 7c, fig. 8a to 8c, and fig. 9a to 9b are schematic structural diagrams corresponding to respective steps of a method for forming an interconnect structure in an embodiment of the present invention.
Detailed Description
The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
Referring to fig. 1, an interconnect structure includes a substrate 10, and an upper layer and a lower layer of metal lines 11 and 12 are formed on the substrate 10 and perpendicular to each other. In order to connect the formed metal line 11 and the metal line 12, a via hole is formed on the lower metal line 11, a metal material is deposited on the surface of the substrate 10 and in the via hole, a metal material layer is formed after the via hole is filled with the metal material and deposited to a certain height on the surface of the substrate 10, and then the metal material layer is etched to form the metal line 12. Ideally, the via holes should align both the metal lines 11 and 12 in the width direction of the metal lines 11 and 12, such as via holes 13c in fig. 1. However, when etching the via hole, the position of the formed via hole may be shifted due to the error of the etching process, for example, the via hole 13a and the via hole 13b in fig. 1 are not aligned with the metal line 11 in the width direction of the metal line 11, and if the distance between adjacent metal lines 11 is short, the short circuit problem of the metal lines in the same layer may also be caused.
Based on this, the present disclosure provides a method for forming an interconnect structure, in which a via hole is formed to be aligned in a width direction of a lower metal line and to expose a portion of a surface of the lower metal line.
Referring to fig. 2, a method for forming an interconnect structure according to an embodiment of the present invention includes:
step S1: providing a substrate, wherein a first through hole is formed in the substrate;
step S2: forming a first conductive material layer, wherein the first conductive material layer fills the first through hole and covers the surface of the substrate;
step S3: forming a dielectric material layer on the surface of the first conductive material layer;
step S4: patterning the dielectric material layer and the first conductive material layer, exposing part of the surface of the substrate, and forming a dielectric layer and a first conductive layer;
step S5: forming an interlayer dielectric layer on the surface of the exposed substrate, wherein the top surface of the interlayer dielectric layer is coplanar with the top surface of the dielectric layer;
step S6: and selectively removing part of the dielectric layer to form a second through hole, wherein the second through hole is aligned in the width direction of the first conductive layer and exposes part of the surface of the first conductive layer.
The following describes a method for forming an interconnect structure according to the present invention in detail with reference to the following embodiments and drawings.
Fig. 3a is a top view of the interconnect structure in step S1, fig. 3B is a cross-sectional view taken along the direction a-a in fig. 3a, and fig. 3c is a cross-sectional view taken along the direction B-B in fig. 3 a. In conjunction with fig. 2, 3a to 3c, a substrate is provided having a first via 140 formed therein. The substrate may include a semiconductor base 110, and a semiconductor device, a shallow trench isolation structure (not shown in the figure), and the like may be formed in the semiconductor base 110. The substrate further includes a front metal layer 120 and a front dielectric layer 130 formed on the semiconductor substrate 110, the front metal layer 120 and the first via 140 are located in the front dielectric layer 130, and the first via 140 is aligned with the front metal layer 120.
In some embodiments, the material of the front metal layer 120 may include at least one of W, Al, Cu, Ti, Ta, TaN, NiSi, CoSi, TiN, TiAl, and TaSiN. The material of the front dielectric layer 130 may include at least one of silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbonitride.
Referring to fig. 4a to 4c, fig. 4a is a top view of the interconnect structure in step S3, fig. 4B is a sectional view taken along a-a direction in fig. 4a, and fig. 4c is a sectional view taken along a B-B direction in fig. 4 a. A first conductive material layer 151 is formed, and the first conductive material layer 151 fills the first via hole 140 and covers the surface of the substrate. The material of the first conductive material layer 151 may include at least one of Cu, Ta, TaN, Co, Ru, RuN, Ti, and TiN. The method of forming the first conductive material layer 151 may be a commonly used deposition method such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or the like.
A dielectric material layer 161 is formed on the surface of the first conductive material layer 151. The material of the dielectric material layer 161 may include SiO2、SiN、Al2O3At least one of AlN, SiCN, SiOC, etc. The method of forming the dielectric material layer 161 may be a commonly used deposition method such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or the like.
Then, the dielectric material layer 161 and the first conductive material layer 151 are patterned to expose a portion of the surface of the substrate, and a dielectric layer 162 and a first conductive layer 152 are formed.
Referring to fig. 5a to 5c, fig. 5a is a patterned mask layer 170 formed on the basis of fig. 4a, fig. 5b is a cross-sectional view taken along a direction a-a in fig. 5a, and fig. 5c is a cross-sectional view of fig. 5ca section in the direction of B-B in a. A patterned masking layer 170 is formed on the surface of the dielectric material layer 161. First, a mask material layer is formed on the surface of the dielectric material layer 161, and the material of the mask material layer may include SiO2SiN, SiOC, SiON, TiN, AlN, and Al2O3May be deposited by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), spin coating, or other suitable methods. The mask material layer is etched again, and the pattern is transferred to the mask material layer to form a patterned mask layer 170.
Referring to fig. 6a to 6c, fig. 6a is a top view of the interconnect structure formed in step S4, fig. 6B is a cross-sectional view taken along the direction a-a in fig. 6a, and fig. 6c is a cross-sectional view taken along the direction B-B in fig. 6 a. With the patterned mask layer 170 as a mask, a portion of the dielectric material layer 161 and the first conductive material layer 151 are sequentially etched to expose a portion of the surface of the substrate, in this embodiment, a portion of the surface of the front dielectric layer 130, so as to form a dielectric layer 162 and a first conductive layer 152.
Referring to fig. 7a to 7c, fig. 7a is a top view of the interconnect structure formed in step S5, fig. 7B is a sectional view taken along the direction a-a in fig. 7a, and fig. 7c is a sectional view taken along the direction B-B in fig. 7 a. Forming an interlayer dielectric material layer on the surface of the patterned mask layer 170 and the exposed surface of the substrate, and then removing part of the interlayer dielectric material layer and the patterned mask layer 170 to make the interlayer dielectric material layer and the top surface of the dielectric layer 162 coplanar to form an interlayer dielectric layer 180. A common planarization process, such as Chemical Mechanical Polishing (CMP), may be used to remove portions of the interlayer dielectric material layer and the patterned masking layer 170.
In the embodiment of the present application, the material of the interlayer dielectric layer 180 must be different from the material of the dielectric layer 162, and it is ensured that when the dielectric layer 162 is etched in a subsequent process, the used etching solvent or etching gas can only etch the dielectric layer 162, and the structure of the interlayer dielectric layer 180 is hardly affected. That is, selective etching of the solvent or etching gas between the layersDielectric layer 180 and dielectric layer 162 have a very high etch selectivity. Therefore, the selection of appropriate materials for the dielectric layer 162 and the interlayer dielectric layer 180, as well as the etching gas or etching solvent, is critical to the alignment process of the embodiments of the present application. In some embodiments, the material of the interlayer dielectric layer 180 may include SiO2、SiN、Al2O3At least one of AlN, SiCN, SiOC and low-K material. The low-K in the examples of the present application means less than SiO2A dielectric constant of (e.g., less than 3.9). The interlayer dielectric layer 180 may also have voids therein.
Referring to fig. 8a to 8C, fig. 8a is a top view of the interconnect structure formed in step S6, fig. 8B is a cross-sectional view taken along the direction B-B in fig. 8a, and fig. 8C is a cross-sectional view taken along the direction C-C in fig. 8 a. A portion of the dielectric layer 162 is selectively removed to form a second via 190, and the second via 190 is aligned in the width direction of the first conductive layer 152 and exposes a portion of the surface of the first conductive layer 152. The method specifically comprises the following processes:
a photoresist layer (not shown) is formed on the surfaces of the interlayer dielectric layer 180 and the dielectric layer 162. The photoresist layer is then patterned to expose portions of the dielectric layer 162. The exposed dielectric layer 162 is etched using the photoresist layer as a mask to form a second via 190. In etching the exposed dielectric layer 162, an etching solvent or an etching gas that can only etch the dielectric layer 162, or an etching solvent or an etching gas having a high selectivity to the dielectric layer 162 may be selected. And finally, removing the photoresist layer by adopting an ashing process.
Because the etching solvent or etching gas has a high etching selection ratio to the interlayer dielectric layer 180 and the dielectric layer 162, when the dielectric layer 162 is etched, the interlayer dielectric layer 180 is hardly affected, and the formed second through hole 190 is aligned to the first conductive layer 152 in the width direction of the first conductive layer 152, so that the problem that the through hole cannot be accurately aligned to the conductive layer in the prior art is solved, and the problem of contact resistance increase or short circuit caused by through hole misalignment in the prior art is effectively avoided.
In a subsequent process, the second conductive layer 200 may also be formed. Referring to fig. 9a and 9b, fig. 9a is a diagram in which a second conductive layer 200 is added to fig. 8b, and fig. 9b is a diagram in which a second conductive layer 200 is added to fig. 8 c. The second conductive layer 200 fills the second via 190 and covers the surfaces of the interlayer dielectric layer 180 and the conductive dielectric layer 162. In some embodiments, the material of the second conductive layer 200 may include at least one of Cu, Ta, TaN, Co, Ru, RuN, Ti, and TiN.
With continuing reference to fig. 9a and 9b, embodiments of the present application further provide an interconnect structure, including: a substrate having a first via hole 140 formed therein; a first conductive layer 152 filling the first via 140 and covering a portion of the surface of the substrate; a dielectric layer 162 on the surface of the first conductive layer 152, wherein a second via 190 is formed in the dielectric layer 162, and the second via 190 is aligned in the width direction of the first conductive layer 152 and exposes a portion of the surface of the first conductive layer 152; and the interlayer dielectric layer 180 is positioned on the surface of the substrate, and the top surface of the interlayer dielectric layer 180 is coplanar with the top surface of the dielectric layer 162.
In the embodiment of the present application, the substrate may include a semiconductor base 110, and a semiconductor device, a shallow trench isolation structure (not shown in the figure), and the like may be formed in the semiconductor base 110. The substrate further includes a front metal layer 120 and a front dielectric layer 130 formed on the semiconductor substrate 110, the front metal layer 120 and the first via 140 are located in the front dielectric layer 130, and the first via 140 is aligned in a width direction of the front conductive layer 120 and exposes a portion of the front metal layer 120.
In some embodiments, the interlayer dielectric layer 170 may further have voids therein.
In some embodiments, the materials of the dielectric layer 162 and the interlevel dielectric layer 180 are different. The material of the dielectric layer 162 may include SiO2、SiN、Al2O3AlN, SiCN or SiOC, the material of the interlayer dielectric layer 180 may include SiO2、SiN、Al2O3At least one of AlN, SiCN, SiOC and low-K material. The low-K in the examples of the present application means less than SiO2A dielectric constant of (e.g., less than 3.9).
In some embodiments, the interconnect structure further comprises: and a second conductive layer 200, wherein the second conductive layer 200 fills the second via 190 and covers the surfaces of the interlayer dielectric layer 180 and the dielectric layer 162. The material of the first conductive layer 152 and the second conductive layer 200 may include at least one of Cu, Ta, TaN, Co, Ru, RuN, Ti, and TiN.
In view of the above, it will be apparent to those skilled in the art upon reading the present application that the foregoing application content may be presented by way of example only, and may not be limiting. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, modifications, and variations are intended to be within the spirit and scope of the exemplary embodiments of this application.
It is to be understood that the term "and/or" as used herein in this embodiment includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference characters denote the same elements throughout the specification.
Further, the present specification describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

Claims (14)

1. A method for forming an interconnect structure, comprising:
providing a substrate, wherein a first through hole is formed in the substrate;
forming a first conductive material layer, wherein the first conductive material layer fills the first through hole and covers the surface of the substrate;
forming a dielectric material layer on the surface of the first conductive material layer;
patterning the dielectric material layer and the first conductive material layer, exposing part of the surface of the substrate, and forming a dielectric layer and a first conductive layer;
forming an interlayer dielectric layer on the surface of the exposed substrate, wherein the top surface of the interlayer dielectric layer is coplanar with the top surface of the dielectric layer;
and selectively removing part of the dielectric layer to form a second through hole, wherein the second through hole is aligned in the width direction of the first conductive layer and exposes part of the surface of the first conductive layer.
2. The method of claim 1, wherein the process of forming the dielectric layer and the first conductive layer comprises:
forming a patterned mask layer on the surface of the dielectric material layer;
and sequentially etching part of the dielectric material layer and the first conductive material layer by taking the patterned mask layer as a mask, exposing part of the surface of the substrate, and forming the dielectric layer and the first conductive layer.
3. The method of claim 2, wherein the step of forming the interlevel dielectric layer comprises:
forming an interlayer dielectric material layer on the surface of the patterned mask layer and the exposed surface of the substrate;
and removing part of the interlayer dielectric material layer and the patterned mask layer to enable the interlayer dielectric material layer and the top surface of the dielectric layer to be coplanar to form an interlayer dielectric layer.
4. The method of claim 1, wherein the step of selectively removing a portion of the dielectric layer to form a second via comprises:
forming photoresist layers on the surfaces of the interlayer dielectric layer and the dielectric layer;
patterning the photoresist layer to expose a portion of the dielectric layer;
and etching the exposed dielectric layer by taking the photoresist layer as a mask to form a second through hole.
5. The method as claimed in claim 4, wherein the dielectric layer and the interlevel dielectric layer are made of different materials, and an etching solvent or an etching gas is used to etch only the dielectric layer when the exposed dielectric layer is etched.
6. The method of claim 5, wherein the material of the dielectric layer comprises SiO2、SiN、Al2O3AlN, SiCN or SiOC, the material of the interlayer dielectric layer comprises SiO2、SiN、Al2O3At least one of AlN, SiCN, SiOC and low-K material.
7. The method of claim 1, further comprising: and forming a second conductive layer, wherein the second conductive layer fills the second through hole and covers the surfaces of the interlayer dielectric layer and the conductive dielectric layer.
8. The method according to claim 7, wherein a material of the first conductive layer and the second conductive layer includes at least one of Cu, Ta, TaN, Co, Ru, RuN, Ti, and TiN.
9. An interconnect structure, comprising:
a substrate having a first via formed therein;
the first conducting layer is filled in the first through hole and covers part of the surface of the substrate;
a dielectric layer on a surface of the first conductive layer, wherein a second through hole is formed in the dielectric layer, and the second through hole is aligned in a width direction of the first conductive layer and exposes a part of the surface of the first conductive layer;
and the interlayer dielectric layer is positioned on the surface of the substrate, and the top surface of the interlayer dielectric layer is coplanar with the top surface of the dielectric layer.
10. The interconnect structure of claim 9, wherein said interlevel dielectric layer has voids therein.
11. The interconnect structure of claim 9, wherein said dielectric layer and said interlevel dielectric layer are of different materials.
12. The interconnect structure of claim 11, wherein the material of the dielectric layer comprises SiO2、SiN、Al2O3AlN, SiCN or SiOC, the material of the interlayer dielectric layer comprises SiO2、SiN、Al2O3At least one of AlN, SiCN, SiOC and low-K material.
13. The interconnect structure of claim 9, further comprising: and the second through hole is filled with the second conducting layer, and the surfaces of the interlayer dielectric layer and the dielectric layer are covered with the second conducting layer.
14. The interconnect structure of claim 9, wherein the substrate further has a front conductive layer formed therein, and the first via is aligned in a width direction of the front conductive layer and exposes a portion of a surface of the front conductive layer.
CN202010748137.0A 2020-07-30 2020-07-30 Interconnect structure and method of forming the same Pending CN114068451A (en)

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