CN114065682A - Circuit yield analysis method based on multilayer perceptron neural network - Google Patents

Circuit yield analysis method based on multilayer perceptron neural network Download PDF

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CN114065682A
CN114065682A CN202111066024.3A CN202111066024A CN114065682A CN 114065682 A CN114065682 A CN 114065682A CN 202111066024 A CN202111066024 A CN 202111066024A CN 114065682 A CN114065682 A CN 114065682A
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张立军
严雨灵
张重达
马利军
娄圆
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Abstract

The invention discloses a circuit yield analysis method based on a multilayer perceptron neural network, which comprises the following steps: firstly, uniformly distributing and sampling: aiming at various process change parameters of a circuit device, a total amount sample is obtained by adopting a uniformly distributed sampling method; secondly, Monte Carlo simulation: performing circuit simulation on the total amount sample by adopting a Monte Carlo simulation method to obtain a circuit failure sample; thirdly, importance sampling: counting the mean value of each parameter of the circuit failure sample, taking the mean value as the central point of the circuit failure area, and performing Gaussian distribution sampling in the circuit failure area by taking the point as an origin to obtain an important sample; and fourthly, screening the neural network of the multilayer perceptron: inputting the important samples into a multi-layer perceptron neural network trained in advance for screening to obtain sampling points of circuit failure; fifthly, calculating the circuit yield: and calculating the circuit yield by adopting an importance sampling formula. The invention can provide fast and accurate yield verification analysis, shorten project period and improve product reliability.

Description

Circuit yield analysis method based on multilayer perceptron neural network
Technical Field
The invention belongs to the technical field of circuit yield analysis, and particularly relates to a circuit yield analysis method based on a multilayer perceptron neural network.
Background
On one hand, under the influence of continuous upgrading and iteration of a chip processing technology, the chip process is continuously miniaturized, for a CMOS (complementary metal oxide semiconductor) process below 100nm, the random variation of process parameters causes the fluctuation of the threshold voltage of an MOS (metal oxide semiconductor) transistor to be more serious, the stability of an SRAM (Static random access memory) is threatened, and the yield of the SRAM is reduced.
On the other hand, in the field of integrated circuit production and manufacturing, the yield improves the competitiveness of a company to a certain extent, and the higher the yield is, the higher the yield is at the same cost, and the higher the profit is.
In the prior art, methods for analyzing the circuit yield include a monte carlo simulation method, importance sampling simulation and the like.
The monte carlo simulation method can evaluate the fluctuation of the overall characteristics by executing multiple times of simulation and reflecting the fluctuation of various circuit elements in the simulation. However, as the integration density of the SRAM is increased, the requirement for the failure rate simulation accuracy of a single SRAM memory cell is increased, and the conventional monte carlo analysis method becomes more and more impractical because the simulation times are too large and the simulation time is too long. For example, the conventional Monte Carlo simulation is performed on a SRAM critical pathTo obtain a 6-sigma accuracy within a 95% confidence interval, 10 is required12And (5) sub-sampling. And the simulation is carried out by spice to complete 2 multiplied by 1014Sub-sampling takes approximately 7 days, so 1012A second conventional monte carlo simulation is impractical today where the design cycle is emphasized.
The importance sampling algorithm forms a corresponding weight function by constructing an importance density function (also called a bias function), and adjusts sampling points through the weight function, so that estimation of failure rate is unbiased estimation. The importance sampling method realizes the reduction of simulation times and simulation time by selecting a reasonable importance density function. However, once the importance density function is selected unreasonably, the simulation efficiency and accuracy of the importance sampling method can be made even lower than the conventional monte carlo simulation method.
How to establish a perfect statistical model, and meanwhile, the statistical model can be correctly applied in the IC design stage, and fast and accurate yield analysis can be performed, so as to effectively avoid the circuit performance and yield from being affected, which is a current important subject. As process advances and complexity increases, the biggest challenge in performing statistical analysis of circuits is the contradiction between speed and accuracy. The high accuracy is sought, which means that the variability analysis must be thoroughly completed, and this requires extremely high number of analog verification times, i.e. in combination with extremely large-scale sampling, which will compromise the chip design efficiency. If the performance is studied, the circuit analysis precision can only be reduced, Monte Carlo can complete the required sampling, but the running time is too long, circuits such as SRAM and the like with large-scale repeated structures often need to be matched with more precise 6sigma verification, millions, tens of millions or even hundreds of millions of times of simulation are performed, and the capability range of Monte Carlo is obviously exceeded. In this case, circuit designers are forced to forego Monte Carlo, and some choices maximize the margin, striving to cover all process variation factors, but may incur significant chip cost from Over Design.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a circuit yield analysis method based on a multi-layer perceptron neural network, which can provide fast and accurate yield verification analysis, shorten project cycle and improve product reliability.
In order to solve the technical problems, the invention adopts the technical scheme that: a circuit yield analysis method based on a multilayer perceptron neural network comprises the following steps:
step one, uniformly distributing and sampling: aiming at various process change parameters of a circuit device, a uniformly distributed sampling method is adopted to obtain a total amount sample;
step two, Monte Carlo simulation: performing circuit simulation on the total amount samples obtained in the step one by adopting a Monte Carlo simulation method, and obtaining circuit failure samples by counting circuit simulation results;
step three, importance sampling: counting the mean value of each parameter of the circuit failure sample, taking the mean value as the central point of the circuit failure area, and carrying out Gaussian distribution sampling in the circuit failure area by taking the central point as an origin point to obtain an important sample;
step four, screening the neural network of the multilayer perceptron: inputting the important samples into a multi-layer perceptron neural network trained in advance for screening to obtain sampling points of circuit failure;
step five, calculating the circuit yield: and calculating the circuit yield by adopting an importance sampling formula according to the result of the step four.
In the method for analyzing the circuit yield based on the multilayer perceptron neural network, the training process of the multilayer perceptron neural network in the fourth step is as follows:
step A, acquiring a training data set, wherein the specific process is as follows:
a1, aiming at each process variation parameter of the circuit device, adopting a uniformly distributed sampling method to obtain a total amount sample;
step A2, performing SPICE simulation and Monte Carlo simulation on the total amount sample, and synthesizing the result data of the SPICE simulation and the result data of the Monte Carlo simulation as a training data set;
b, establishing a multilayer perceptron neural network model aiming at the characteristics of circuit yield analysis, wherein the multilayer perceptron neural network model comprises an input layer, an output layer and one or more hidden layers connected between the input layer and the output layer;
and step C, training the multilayer perceptron neural network model established in the step B by adopting the training data set obtained in the step A, and minimizing a loss function or a cost function to obtain the trained multilayer perceptron neural network.
The above circuit yield analysis method based on the multilayer perceptron neural network includes that the multilayer perceptron neural network model includes an input layer, an output layer, and a hidden layer connected between the input layer and the output layer, the input layer and the hidden layer both include a plurality of neurons, the output layer includes a neuron, the neurons of the input layer are all connected to the neurons of the hidden layer, the neurons of the hidden layer are all connected to a neuron of the output layer, the neurons of the input layer adopt different weights, and an activation function of the hidden layer is a Sigmoid function, a tanh function or a step function.
In the circuit yield analysis method based on the multilayer perceptron neural network, the number of the neurons contained in the input layer is the same as the number of the random process variables provided in the process library file, and the number of the neurons is respectively the random process variables; the number of the neurons of the hidden layer is equal to the number of actual physical parameters of the circuit; the neuron included in the output layer is a circuit yield analysis result; the activation function of the hidden layer is a Sigmoid function.
In the circuit yield analysis method based on the multilayer perceptron neural network, in the fifth step, when the circuit yield is calculated by adopting the importance sampling formula according to the result of the fourth step, the adopted importance sampling formula is
Figure RE-GDA0003475145100000041
Yield＝1-Pfail(ii) a Wherein, PfailF (x) is the original distribution provided in the process library file for failure probability, g (x) is the sample of circuit failures determined in step fourPoint; i (x) is an indication function, when the circuit fails, I (x) is 1, otherwise, the value is 0; yield of the circuit.
Compared with the prior art, the invention has the following advantages:
1. the invention adopts the multilayer neural perceptron technology and combines the rapid Monte Carlo yield analysis of importance sampling, and compared with the conventional Monte Carlo technology, the simulation efficiency can be improved by more than 1000 times, thereby realizing the high-precision simulation of a large-scale circuit in a limited time. For example: when the overall functional yield of one memory chip is analyzed, if the required analysis precision reaches 6sigma, the time may need several months, and by adopting the method and the device, the accurate analysis result can be obtained within one day.
2. The invention can be applied to the circuit reliability analysis of high-end technology (14nm and below), can carry out fast and accurate yield analysis, effectively avoids the influence on the circuit performance and yield, and does not cause high chip cost.
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
Drawings
FIG. 1 is a block diagram of the process flow of the present invention.
FIG. 2 is a network topology structure diagram of the multi-layer perceptron neural network of the present invention.
Detailed Description
As shown in fig. 1 and fig. 2, the method for analyzing the circuit yield based on the multi-layer perceptron neural network of the present invention includes the following steps:
step one, uniformly distributing and sampling: aiming at various process change parameters of a circuit device, a uniformly distributed sampling method is adopted to obtain a total amount sample;
in specific implementation, the number of samples of the total amount samples can be set by a user according to the actual acceptable simulation time condition;
step two, Monte Carlo simulation: performing circuit simulation on the total amount samples obtained in the step one by adopting a Monte Carlo simulation method, and obtaining circuit failure samples by counting circuit simulation results;
step three, importance sampling: counting the mean value (namely the average deviation from the origin) of each parameter of the circuit failure sample, taking the mean value as the central point of the circuit failure area, and carrying out Gaussian distribution sampling in the circuit failure area by taking the central point as the origin to obtain an important sample;
in specific implementation, the sampling number for Gaussian distribution sampling can be set by a user according to the actual acceptable simulation time condition;
step four, screening the neural network of the multilayer perceptron: inputting the important samples into a multi-layer perceptron neural network trained in advance for screening to obtain sampling points of circuit failure;
in this embodiment, the training process of the multilayer perceptron neural network in step four is as follows:
step A, acquiring a training data set, wherein the specific process is as follows:
a1, aiming at each process variation parameter of the circuit device, adopting a uniformly distributed sampling method to obtain a total amount sample;
step A2, performing SPICE simulation and Monte Carlo simulation on the total amount sample, and synthesizing the result data of the SPICE simulation and the result data of the Monte Carlo simulation as a training data set;
b, establishing a multilayer perceptron neural network model aiming at the characteristics of circuit yield analysis, wherein the multilayer perceptron neural network model comprises an input layer, an output layer and one or more hidden layers connected between the input layer and the output layer;
and step C, training the multilayer perceptron neural network model established in the step B by adopting the training data set obtained in the step A, and minimizing a loss function or a cost function to obtain the trained multilayer perceptron neural network.
The Multi-Layer Perceptron neural network (MLP) is derived from a biomimetic neural network, and the screening of the target is realized by connecting a plurality of existing characteristic values and combining the existing characteristic values linearly or non-linearly.
In this embodiment, the multilayer perceptron neural network model includes an input layer, an output layer, and a hidden layer connected between the input layer and the output layer, where the input layer and the hidden layer both include a plurality of neurons, the output layer includes a neuron, the neurons of the input layer are all connected to the neurons of the hidden layer, the neurons of the hidden layer are all connected to the neurons of the output layer, the neurons of the input layer adopt different weights, and an activation function of the hidden layer is a Sigmoid function, a tanh function, or a step function.
In this embodiment, the number of neurons included in the input layer is the same as the number of random process variables provided in the process library file, and the number of neurons is respectively each random process variable; the number of the neurons of the hidden layer is equal to the number of actual physical parameters of the circuit; the neuron included in the output layer is a circuit yield analysis result; the activation function of the hidden layer is a Sigmoid function.
For example, if the number of random process variables provided in the process library file is 20, then the input layer has 20 neurons; assuming that the actual physical parameters of the circuit affected by the 20 random process variables in the process are 20000, the number of the hidden layer neurons is 20000; finally, the output layer is a node, namely whether the node is a sampling point of circuit failure or not.
In this embodiment, when the circuit yield is calculated by using the importance sampling formula for the result of the step four in the step five, the importance sampling formula is
Figure RE-GDA0003475145100000061
Yield＝1-Pfail(ii) a Wherein, Pfail(x) is the original distribution provided in the process library file, and g (x) is the sampling point of the circuit failure determined in the fourth step; i (x) is an indication function, when the circuit fails, I (x) is 1, otherwise, the value is 0; yield of the circuit.
When the input layer is connected with the hidden layer, the neurons of each input layer cannot adopt the same weight, if the same weight is adopted, an optimized classifier model cannot be well constructed according to the importance degree of each type of data, the input characteristic values are supplemented with different weights to perform weighting operation, and then the neurons are activated by changing linear rules such as an activation function.
Step five, calculating the circuit yield: and D, calculating the circuit yield of the result of the step four by adopting an importance sampling formula, thereby verifying the reliability of the circuit and outputting the reliability result of the circuit.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims (5)

1. A circuit yield analysis method based on a multilayer perceptron neural network is characterized by comprising the following steps:
step one, uniformly distributing and sampling: aiming at various process change parameters of a circuit device, a uniformly distributed sampling method is adopted to obtain a total amount sample;
step two, Monte Carlo simulation: performing circuit simulation on the total amount samples obtained in the step one by adopting a Monte Carlo simulation method, and obtaining circuit failure samples by counting circuit simulation results;
step three, importance sampling: counting the mean value of each parameter of the circuit failure sample, taking the mean value as the central point of the circuit failure area, and carrying out Gaussian distribution sampling in the circuit failure area by taking the central point as an origin point to obtain an important sample;
step four, screening the neural network of the multilayer perceptron: inputting the important samples into a multi-layer perceptron neural network trained in advance for screening to obtain sampling points of circuit failure;
step five, calculating the circuit yield: and calculating the circuit yield by adopting an importance sampling formula according to the result of the step four.
2. The method of claim 1, wherein the method comprises the following steps: the training process of the multilayer perceptron neural network in the fourth step is as follows:
step A, acquiring a training data set, wherein the specific process is as follows:
a1, aiming at each process variation parameter of the circuit device, adopting a uniformly distributed sampling method to obtain a total amount sample;
step A2, performing SPICE simulation and Monte Carlo simulation on the total amount sample, and synthesizing the result data of the SPICE simulation and the result data of the Monte Carlo simulation as a training data set;
b, establishing a multilayer perceptron neural network model aiming at the characteristics of circuit yield analysis, wherein the multilayer perceptron neural network model comprises an input layer, an output layer and one or more hidden layers connected between the input layer and the output layer;
and step C, training the multilayer perceptron neural network model established in the step B by adopting the training data set obtained in the step A, and minimizing a loss function or a cost function to obtain the trained multilayer perceptron neural network.
3. The method of claim 2, wherein the method comprises the following steps: the multilayer perceptron neural network model comprises an input layer, an output layer and a hidden layer connected between the input layer and the output layer, wherein the input layer and the hidden layer both comprise a plurality of neurons, the output layer comprises a neuron, the neurons of the input layer are all connected to the neurons of the hidden layer, the neurons of the hidden layer are all connected to the neurons of the output layer, the neurons of the input layer adopt different weights, and the activation function of the hidden layer is a Sigmoid function, a tanh function or a step function.
4. The method of claim 3, wherein the method comprises the following steps: the number of the neurons contained in the input layer is the same as the number of the random process variables provided in the process library file, and the number of the neurons is respectively the random process variables; the number of the neurons of the hidden layer is equal to the number of actual physical parameters of the circuit; the neuron included in the output layer is a circuit yield analysis result; the activation function of the hidden layer is a Sigmoid function.
5. The method of claim 1, wherein the method comprises the following steps: in the fifth step, when the circuit yield is calculated by adopting the importance sampling formula to the result of the fourth step, the adopted importance sampling formula is
Figure 412658DEST_PATH_IMAGE001
Figure 238401DEST_PATH_IMAGE002
(ii) a Wherein the content of the first and second substances,
Figure 164768DEST_PATH_IMAGE003
in order to be a probability of failure,
Figure 120086DEST_PATH_IMAGE004
for the original distribution provided in the process library file,
Figure 4866DEST_PATH_IMAGE005
the sampling point of the circuit failure determined in the fourth step;
Figure 6320DEST_PATH_IMAGE006
for indicating function, when circuit fails
Figure 595433DEST_PATH_IMAGE007
Is 1, otherwise is
Figure 61049DEST_PATH_IMAGE008
The yield of the circuit is obtained.
CN202111066024.3A 2021-09-13 2021-09-13 Circuit yield analysis method based on multilayer perceptron neural network Pending CN114065682A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115358178A (en) * 2022-08-11 2022-11-18 山东大学 Circuit yield analysis method based on fusion neural network

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115358178A (en) * 2022-08-11 2022-11-18 山东大学 Circuit yield analysis method based on fusion neural network
CN115358178B (en) * 2022-08-11 2023-04-07 山东大学 Circuit yield analysis method based on fusion neural network

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