CN114064537A

CN114064537A - Data processing method, device, equipment and medium of I2C bus

Info

Publication number: CN114064537A
Application number: CN202010747136.4A
Authority: CN
Inventors: 梁红伟
Original assignee: Zhejiang Uniview Technologies Co Ltd
Current assignee: Zhejiang Uniview Technologies Co Ltd
Priority date: 2020-07-29
Filing date: 2020-07-29
Publication date: 2022-02-18

Abstract

The embodiment of the invention discloses a data processing method, a device, equipment and a medium of an I2C bus. The method comprises the following steps: according to the acquired I2C bus sampling signal of the tested device, determining effective transmission content on an I2C bus; packing the values of the effective transmission contents on the I2C bus into a data packet with a preset format; and acquiring the data packet, analyzing the data packet, and debugging or positioning the abnormality of the I2C bus according to the message data acquired by analyzing the data packet. By adopting the scheme, only the I2C bus sampling signal needs to be analyzed, the start bit, the data bit, the response bit and the end bit of the effective transmission of the I2C bus can be accurately captured, and an engineer can debug codes or position the I2C bus problem conveniently.

Description

Data processing method, device, equipment and medium of I2C bus

Technical Field

The embodiment of the invention relates to the technical field of data communication, in particular to a data processing method, a data processing device, data processing equipment and a data processing medium of an I2C bus.

Background

The I2C bus is a simple, bidirectional two-wire synchronous serial bus that requires only two wires to transfer information between devices connected to the bus. The I2C bus is simple and easy to use, requiring only two wires to transfer information between devices connected to the bus, and is therefore widely used in the field of computer servers and various embedded systems. However, the I2C bus is a serial bidirectional multi-device bus, and improper use is prone to various problems, such as slave address collision, signal under-drive, and timing problems. However, for the positioning of the above problems, the signals can be measured only by an oscilloscope or a logic analyzer, and the combined positioning can be performed only by a driver engineer and a hardware engineer, which wastes a lot of time and human resources. Therefore, how to quickly and accurately locate the problem of the I2C bus is urgent.

Disclosure of Invention

In view of the foregoing problems, embodiments of the present invention provide a data processing method, apparatus, device, and medium for an I2C bus, so as to quickly and accurately locate a problem occurring in an I2C bus.

In a first aspect, an embodiment of the present invention provides a data processing method for an I2C bus, including:

according to the acquired I2C bus sampling signal of the tested device, determining effective transmission content on an I2C bus;

packing the values of the effective transmission contents on the I2C bus into a data packet with a preset format;

and acquiring the data packet, analyzing the data packet, and debugging or positioning the abnormality of the I2C bus according to the message data acquired by analyzing the data packet.

In a second aspect, an embodiment of the present invention further provides a data processing apparatus with an I2C bus, including:

the transmission content determining module is used for determining effective transmission content on an I2C bus according to the acquired I2C bus sampling signal of the tested device;

a data packet determining module, configured to package the value of the effective transmission content on the I2C bus into a data packet in a preset format;

and the data packet analysis module is used for acquiring the data packet, analyzing the data packet, and debugging or positioning the abnormity of the I2C bus according to the message data acquired by analyzing the data packet.

In a third aspect, an embodiment of the present invention further provides a packet capturing device, including:

one or more processors;

storage means for storing one or more programs;

the one or more programs are executed by the one or more processors, so that the one or more processors implement the data processing method of the I2C bus as described in any of the embodiments of the present invention.

In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, which, when executed by a processor, implements the data processing method of the I2C bus as described in any of the embodiments of the present invention.

The embodiment of the invention provides a data processing method of an I2C bus, which includes the steps of obtaining an I2C bus sampling signal according to signal sampling of an I2C bus of a tested device, automatically determining effective transmission content on the I2C bus, sequentially packaging the effective transmission content such as a start bit, a data bit, a response bit and an end bit to obtain a data packet with a preset format, analyzing the data packet with the preset format to obtain message data, and debugging or positioning abnormity of the I2C bus according to the obtained message data. By adopting the technical scheme, signals on the I2C bus do not need to be analyzed one by using an oscilloscope or a logic analyzer to measure signals, and only by analyzing I2C bus sampling signals, the start bit, the data bit, the response bit and the end bit of the I2C bus for effective transmission can be accurately captured, and captured effective transmission contents are automatically packaged, so that an engineer can conveniently debug codes or position the problem of the I2C bus.

The above summary of the present invention is merely an overview of the technical solutions of the present invention, and the present invention can be implemented in accordance with the content of the description in order to make the technical means of the present invention more clearly understood, and the above and other objects, features, and advantages of the present invention will be more clearly understood.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

fig. 1 is a flowchart of a data processing method of an I2C bus provided in an embodiment of the present invention;

FIG. 2 is a schematic diagram of data capture on an I2C bus according to an embodiment of the present invention;

fig. 3 is a schematic diagram of accessing an I2C bus for data packet capture according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating a packet format for read and write operations on an I2C bus according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a data packet with a predetermined format according to an embodiment of the present invention;

fig. 6 is a block diagram of a data processing apparatus of an I2C bus provided in the embodiment of the present invention;

fig. 7 is a schematic structural diagram of a bale plucking device provided in an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the operations (or steps) as a sequential process, many of the operations (or steps) can be performed in parallel, concurrently or simultaneously. In addition, the order of the operations may be re-arranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.

To facilitate understanding of the present solution, a brief description will now be made of a "master-slave" mode of the I2C bus, in which a master device is used to initiate the I2C bus to transfer data and generate a clock to a slave device, when any addressed device is considered a slave device. The master and slave, send and receive relationships are not constant across the I2C bus, but depend on the direction of data transfer at the time. If the master device is to send data to the slave device, the master device first addresses the slave device, then actively sends the data to the slave device, and finally the master device terminates the data transfer; if the master device is to receive the data of the slave device, the slave device is addressed by the master device first, then the master device receives the data sent by the slave device, and finally the master device terminates the receiving process. In this case, the master is responsible for generating the timing clock and terminating the data transfer.

The following describes in detail a data processing method, an apparatus, a device, and a medium of the I2C bus provided in the embodiments of the present invention through various embodiments and alternative solutions of various embodiments.

Fig. 1 is a flowchart of a data processing method of an I2C bus provided in an embodiment of the present invention. The embodiment of the invention can be suitable for the condition of data capture of the I2C bus. The method can be executed by a data processing device of an I2C bus, which can be implemented in a software and/or hardware manner and can be integrated on any packet capturing device with a network communication function. As shown in fig. 1, the data processing method of the I2C bus provided in the embodiment of the present invention may include the following steps S110 to S130:

and S110, determining effective transmission content on the I2C bus according to the acquired I2C bus sampling signal of the tested device.

In this embodiment, fig. 2 is a schematic diagram of data capture on an I2C bus according to an embodiment of the present invention. Referring to fig. 2, the I2C bus is composed of serial data line SDA, serial clock line SCL and pull-up resistor, respectively, and generates signals required by I2C bus protocol for data transmission by controlling the high and low level timing of SCL line and SDA line.

In this embodiment, fig. 3 is a schematic diagram of accessing an I2C bus to perform data packet capture according to an embodiment of the present invention. Referring to fig. 3, when packet grabbing is performed, a signal on the I2C bus of the device under test may be accessed to the packet grabbing apparatus of the present embodiment, and the packet grabbing apparatus samples the signal on the I2C bus of the accessed device under test to obtain an I2C bus sampling signal including an SCL clock sampling signal and an SDA data sampling signal.

In an alternative of this embodiment, sampling the signal of the I2C bus of the device under test to obtain an I2C bus sampling signal may include the following operations:

signals on a serial clock line SCL and a serial data line SDA of an I2C bus of the tested device are sampled by adopting a high-speed clock, and an I2C bus sampling signal is obtained.

IN this embodiment, referring to fig. 2 and fig. 3, the packet capture device includes a high-speed programmable logic chip, and by using the high-speed programmable logic chip, signals on the serial clock line SCL and the serial data line SDA IN the I2C bus of the device under test can be subjected to high-speed clock sampling, so as to obtain an SCL clock sampling signal and an SDA data sampling signal, which are denoted as SCL _ IN and SDA _ IN, respectively.

In this embodiment, referring to fig. 2 and fig. 3, since the packet capturing device of the present application belongs to an external device with respect to the device under test, after the packet capturing device of the present application is connected to the I2C bus of the device under test, it is necessary to isolate the I2C signal on the I2C bus of the device under test, and perform level matching on the I2C signal on the I2C bus, so as to ensure that the level of the I2C signal entering the packet capturing device from the I2C bus is consistent with the level of the I2C signal on the I2C bus of the device under test. Furthermore, the level-matched I2C signal on the I2C bus can be sampled to obtain an I2C bus sample signal. For example, 5V, 3.3V, 2.5V, 1.8V level inputs may be provided on the bale plucking device to match the level of the I2C signal entering the bale plucking device to the level of the I2C signal on the device under test I2C bus.

In the embodiment, the I2C bus of the device under test does not always transmit data, and when the pull-up resistors connected to the SCL line and the SDA line are pulled high and the SCL line and the SDA line are kept at a high level, the I2C bus of the device under test is in an idle state. The I2C protocol, however, specifies that the transfer of data over the I2C bus must be conditioned to begin with a start signal and to stop with an end signal, so that only data from the start signal to the end signal is effectively transferred. The effective transmission content on the I2C bus comprises the following contents: the data content corresponding to the start bit, the data bit, the response bit and the end bit.

In an alternative of this embodiment, determining the effective transmission content of the I2C bus of the device under test according to the acquired I2C bus sampling signal may include the following steps a 1-A3:

step A1, if the SCL clock sampling signal is at high level and the SDA data sampling signal jumps from high to low, it is determined that the I2C bus is currently in the start state and the currently corresponding start bit is determined.

In this embodiment, referring to fig. 2 and 3, when the I2C bus is in the idle state, both the SCL line and the SDA line are held high. After the I2C bus sampling signals are obtained from the SCL line and the SDA line, the obtained SCL clock sampling signal SCL _ IN and the SDA data sampling signal SDA _ IN can be detected IN real time. If SCL _ IN is detected to be at a high level at the falling edge of SDA _ IN, it is determined that the I2C bus of the device under test is currently IN the start state, i.e., a start condition is triggered, and a corresponding start bit may be determined for the currently IN start state, where "01" may be used to indicate the start bit.

Step A2, after the I2C bus is determined to be in the initial state, byte sampling is carried out on the SDA data sampling signal, and data bits transmitted on the I2C bus are determined; and determining that the response bit corresponding to one byte is transmitted on the I2C bus.

In the present embodiment, referring to fig. 2 and 3, when it is determined that the I2C bus is in the start state, it indicates that the I2C bus of the device under test will start to transmit byte data. Therefore, after the I2C bus is determined to be in the initial state, the SDA data sampling signal may start to be byte-sampled, and the byte data transmitted through the I2C bus is obtained, i.e., the corresponding data bit is obtained. For example, when a byte sample is performed, the count value bit _ cnt of the counter is initialized to an initial value of 000, and when the falling edge of the SCL clock sampling signal SCL _ IN is reached, the count value reaches 111 through the counter +1, thereby completing a byte sample. When the I2C bus is detected to be in the acknowledge ACK or the initial state, the count value bit _ cnt of the counter is cleared, so as to count again the next byte sample.

In this embodiment, referring to fig. 2 and fig. 3, in the process of generating each clock pulse on the SCL line, a data bit is transmitted on the SDA line, and after a byte is transmitted in the order from the high bit to the low bit of the data bit, an ACK response signal needs to be responded to the master device through the I2C bus, so that the ACK response signal immediately follows the byte that has transmitted 8 bits, and a response bit corresponding to the ACK response signal can be obtained, which can be represented by "00".

And A3, if the SCL clock sampling signal is at high level and the SDA data sampling signal jumps from low to high, judging that the I2C bus is currently in an end state, and determining a currently corresponding end bit.

IN this embodiment, referring to fig. 2 and fig. 3, when detecting the obtained SCL clock sampling signal SCL _ IN and the SDA data sampling signal SDA _ IN real time, if detecting that SCL _ IN is at a high level at a rising edge of SDA _ IN, it is determined that the I2C bus of the device under test is currently IN an end state, that is, an end condition is triggered, at this time, a corresponding end bit may be determined for the currently-IN start state, where "10" may be used to represent the end bit, and after the start condition is generated, the I2C bus is IN a busy state.

And S120, packing the values of the effective transmission contents on the I2C bus into a data packet with a preset format.

In an alternative of this embodiment, the step of packing the values of the valid transmission content on the I2C bus into a data packet with a preset format may include the following operations:

and splicing the effective transmission contents according to the transmission sequence of the effective transmission contents on the I2C bus to obtain a data packet with a preset format for read-write operation between the master device and the slave device.

In this embodiment, fig. 4 is a schematic diagram of a packet format for read and write operations on an I2C bus according to an embodiment of the present invention. Referring to fig. 4, according to the transmission order of each effective transmission content and the read/write operation type determined on the bus of the device under test I2C, each effective transmission content is sequentially spliced and packaged by using a suitable data format, so as to obtain a data packet in a preset format.

S130, acquiring a data packet in a preset format, analyzing the data packet in the preset format, and debugging or positioning the abnormity of the I2C bus according to message data obtained by analyzing the data packet.

In this embodiment, optionally, the valid transmission content on the I2C bus is converted from serial to parallel, organized into a data packet with a preset format, and sent to the MCU module in the packet capture device through a parallel interface, such as an SPI (not limited to an SPI interface).

In an alternative of this embodiment, the obtaining of the data packet in the preset format and the parsing of the data packet in the preset format may include the following operations:

analyzing the obtained data packet to obtain message data of the data packet; the message data is used for representing data information transmitted by the I2C bus sampling signal, and the message data of the data packet comprises a device address indicated by a data bit in effective transmission content, a read/write state, a response state indicated by a response bit, and a data input/output state.

In this embodiment, referring to fig. 2 and 3, after a packet of data packets in a preset format is obtained, an MCU module in the packet capturing device may analyze the obtained data packets, and then store the data packets in a memory external to the packet capturing device to support long-time packet capturing; and then screening and displaying according to the setting of the user, supporting the display of serial port information, and downloading the monitored data packet. For example, the device address, read/write operation type, and ACK analysis may be performed on a packet in a predetermined format, for example, according to the format composition of the packet, bits 7-bit1 of DATA0 following the start bit "01" are the device address, bit0 of DATA0 is the read/write bit, 0 is the write, 1 is the read, and "01" immediately following the DATA bit is the ACK.

IN this embodiment, the packet DATA format displayed by the final parsing packet may refer to the packet DATA contents shown IN table 1, table 2 and table 3 below, and may specifically include attributes such as a packet time, a device address, a read/write status Op type, a response status ACK indicated by a response bit, and a DATA input DATA IN/output DATA OUT status, and the user may perform a filtering operation according to the attributes. Therefore, the I2C message can be automatically analyzed, the display is visual, and the display is displayed according to the message time, the equipment address, the read/write operation type, the data content, the response state indicated by the response bit, the data input/output state and other attributes, for example, when a software engineer debugs a code, whether the message is generated or not or whether the message is correct or not can be grabbed for a long time by the packet grabbing equipment of the scheme of the application after the code is executed.

TABLE 1

Time	Device address	Op type	ACK	DATA IN	DATA OUT
						2020-06-22 10:54:47	1010000	Write	Yes	0xB0
2020-06-22 10:54:47	1010000	Read	Yes		0XA1

TABLE 2

Time

Device address

Op type

ACK

DATA IN

ACK

DATAIN

ACK

2020-06-22 10:55:10

1010000

Write

Yes

0XB0

Yes

0XB1

Yes

TABLE 3

Time

Device address

Op type

ACK

DATAIN

ACK

DATAIN

ACK

DATAIN

2020-06-22 10:55:10

1010000

Write

Yes

0XB0

Yes

0XB1

Yes

0xB2

In an alternative of this embodiment, before parsing a packet, the data processing method of the I2C bus provided in this embodiment of the present invention further includes the following operations:

and adding a time stamp to the data packet with the preset format, and storing the data packet with the preset format added with the time stamp in a memory.

In this embodiment, fig. 5 is a schematic diagram of a data packet with a preset format provided in an embodiment of the present invention. Referring to fig. 5, the packet capturing device may stamp the obtained data packet in the preset format through the MCU module provided by the packet capturing device, for example, stamp the data packet in the preset format according to the time format of year/month/day/hour/minute/second/microsecond, and then store the data packet in the preset format added with the timestamp in the external memory of the MCU module, so as to achieve long-time packet capturing.

In this embodiment, referring to fig. 2 and fig. 3, after a timestamp is applied to a data packet, the data packet sent may be analyzed first, and then stored in a memory of an external device of a packet capturing device, so as to support long-time packet capturing; and then screening and displaying according to the setting of the user, supporting the display of serial port information, and downloading the monitored data packet.

The embodiment of the invention provides a data processing method of an I2C bus, and by adopting the technical scheme, signals on the I2C bus do not need to be analyzed one by using signals measured by an oscilloscope or a logic analyzer, and the bus transmission state of the I2C bus can be determined in real time only according to the I2C bus sampling signals obtained by sampling the I2C bus, so that the start bit, the data bit, the response bit and the end bit of the I2C bus for effective transmission can be accurately captured, the captured effective transmission contents are automatically packaged, and the code of an engineer or the problem of the I2C bus can be conveniently located.

Fig. 6 is a block diagram of a data processing apparatus of an I2C bus according to an embodiment of the present invention. The embodiment of the invention can be suitable for the condition of data capture of the I2C bus. The device can be realized in a software and/or hardware mode and can be integrated on any packet capturing equipment with a network communication function.

As shown in fig. 6, the data processing apparatus of I2C bus provided in the embodiment of the present invention may include the following: a transmission content determining module 610, a data packet determining module 620 and a data packet parsing module 630. Wherein:

the transmission content determining module 610 is configured to determine effective transmission content on an I2C bus according to the acquired I2C bus sampling signal of the device under test;

a packet determining module 620, configured to package the value of the effective transmission content on the I2C bus into a packet with a preset format;

and the data packet analyzing module 630 is configured to acquire the data packet, analyze the data packet, and debug or locate an abnormality of the I2C bus according to the message data acquired by analyzing the data packet.

On the basis of the foregoing embodiment, optionally, the apparatus further includes:

the signal sampling module 640 is configured to sample signals on a serial clock line SCL and a serial data line SDA in the I2C bus by using a high-speed clock to obtain the I2C bus sampling signal; wherein the I2C bus sample signal comprises an SCL clock sample signal and an SDA data sample signal.

On the basis of the foregoing embodiment, optionally, the transmission content determining module 610 includes:

if the SCL clock sampling signal is at a high level and the SDA data sampling signal jumps from high to low, judging that the I2C bus is currently in an initial state, and determining a currently corresponding initial bit;

after determining that the I2C bus is in the start state, starting byte sampling of the SDA data sampling signal, determining data bits transmitted on the I2C bus; and determining a response bit corresponding to the completion of one byte of transmission on the I2C bus;

and if the SCL clock sampling signal is at a high level and the SDA data sampling signal jumps from low to high, judging that the I2C bus is currently in an end state, and determining a currently corresponding end bit.

On the basis of the foregoing embodiment, optionally, the data packet determining module 620 includes:

On the basis of the foregoing embodiment, optionally, the packet parsing module 630 includes:

analyzing the acquired data packet to obtain message data of the data packet,

the message data is used for representing data information transmitted by the I2C bus sampling signal, wherein the message data of the data packet comprises a device address indicated by a data bit in effective transmission content, a read/write state, a response state indicated by a response bit, and a data input/output state.

and before the data packet is analyzed, adding a time stamp to the data packet with the preset format, and storing the data packet with the preset format added with the time stamp in a memory.

The I2C bus data processing apparatus provided in the embodiment of the present invention can execute the I2C bus data processing method provided in any embodiment of the present invention, and has the corresponding functions and advantages of executing the I2C bus data processing method, and reference may be made to the I2C bus data processing method provided in any embodiment of the present invention without detailed technical details in the above embodiments.

Fig. 7 is a schematic structural diagram of a bale plucking device provided in an embodiment of the present invention. As shown in fig. 7, the bale plucking apparatus provided in the embodiment of the present invention includes: one or more processors 710 and storage 720; the processor 710 in the packet capturing device may be one or more, and one processor 710 is taken as an example in fig. 7; storage 720 for storing one or more programs; the one or more programs are executed by the one or more processors 710, so that the one or more processors 710 implement the data processing method of the I2C bus according to any of the embodiments of the present invention.

The packet capturing device may further include: an input device 730 and an output device 740.

The processor 710, the storage device 720, the input device 730, and the output device 740 in the packet capturing apparatus may be connected by a bus or other means, and fig. 7 illustrates an example of a connection by a bus.

The storage device 720 in the bale plucking apparatus is used as a computer readable storage medium for storing one or more programs, which may be software programs, computer executable programs, and modules, such as program instructions/modules corresponding to the data processing method of the I2C bus provided in the embodiment of the present invention. The processor 710 executes various functional applications and data processing of the bale plucking device by running software programs, instructions and modules stored in the storage device 720, namely, the data processing method of the I2C bus in the above method embodiment is realized.

The storage 720 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to use of the packet capture apparatus, and the like. Additionally, the storage 720 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, the storage 720 may further include memory located remotely from the processor 710, which may be connected to the device over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The input device 730 may be used to receive entered numeric or character information and generate key signal inputs relating to user settings and function controls of the bale plucking apparatus. The output device 740 may include a display device such as a display screen.

And, when the one or more programs included in the above-mentioned bale plucking apparatus are executed by the one or more processors 510, the programs perform the following operations:

Of course, it will be understood by those skilled in the art that when one or more programs included in the above-described packet capturing apparatus are executed by the one or more processors 710, the programs may also perform operations associated with the data processing method of the I2C bus provided in any embodiment of the present invention.

An embodiment of the present invention provides a computer-readable storage medium on which a computer program is stored, the program being executed by a processor to perform a data processing method of an I2C bus, the method including:

Alternatively, the program may be used to execute a data processing method of the I2C bus provided in any embodiment of the present invention when the program is executed by the processor.

Computer storage media for embodiments of the invention may employ any combination of one or more computer-readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a Read Only Memory (ROM), an Erasable Programmable Read Only Memory (EPROM), a flash Memory, an optical fiber, a portable CD-ROM, an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. A computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take a variety of forms, including, but not limited to: an electromagnetic signal, an optical signal, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, Radio Frequency (RF), etc., or any suitable combination of the foregoing.

Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A data processing method of an I2C bus is characterized by comprising the following steps:

2. The method of claim 1, further comprising:

sampling signals on a serial clock line SCL and a serial data line SDA in the I2C bus by adopting a high-speed clock to obtain a sampling signal of the I2C bus; wherein the I2C bus sample signal comprises an SCL clock sample signal and an SDA data sample signal.

3. The method of claim 1, wherein determining valid transmission content on the I2C bus according to the acquired I2C bus sampling signal of the device under test comprises:

4. The method of claim 1, wherein packaging the values of the valid transmission content on the I2C bus into a packet with a preset format comprises:

5. The method of claim 1, wherein obtaining the data packet and parsing the data packet comprises:

analyzing the acquired data packet to obtain message data of the data packet,

6. The method of claim 1, wherein prior to parsing the packet, the method further comprises:

7. A data processing apparatus for an I2C bus, comprising:

8. The apparatus of claim 7, wherein the transmission content determining module comprises:

9. A bale plucking apparatus, comprising:

one or more processors;

storage means for storing one or more programs;

when executed by the one or more processors, cause the one or more processors to implement the data processing method of the I2C bus of any one of claims 1-6.

10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the data processing method of the I2C bus of any one of claims 1-6.