CN114064505A

CN114064505A - Test method, system, device and storage medium for decoding unit

Info

Publication number: CN114064505A
Application number: CN202111419719.5A
Authority: CN
Inventors: 林思博
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2021-11-26
Filing date: 2021-11-26
Publication date: 2022-02-18

Abstract

The present disclosure provides a test method, system, device and storage medium for a decoding unit, the method comprising: acquiring a target instruction; acquiring a set of approximate instruction codes according to a target instruction, wherein the set of approximate instruction codes comprises a plurality of approximate instruction codes corresponding to the target instruction; acquiring a plurality of approximate instructions to be tested corresponding to the target instruction according to at least one legal format of the target instruction and a set of the approximate instruction codes; a plurality of approximate instructions to be tested are tested using a decode unit. The testing method can comprehensively complete the verification of the target instruction and the approximate instruction of the target instruction, and verifies whether the decoding unit can support the newly added instruction and normally work under the condition of newly added target instruction.

Description

Test method, system, device and storage medium for decoding unit

Technical Field

Embodiments of the present disclosure relate to a test method, system, apparatus, and storage medium for a decode unit.

Background

The processor is used as a specialized unit for operation and logic control, common calculation or logic control can be abstracted and packaged into a single instruction, and when a user develops a program based on a specific processor platform, the instructions can be directly used to achieve a specific target without paying attention to hardware implementation, and a combination formed by the instructions is called an instruction set. Due to the consideration of hardware simplification, the instructions in the instruction set are relatively simple, and a user needs to perform secondary packaging at a software level to complete a final algorithm during development.

With the development of the technology, the operation requirement of software on a processor is higher and higher, the realization of some common algorithms on a software level cannot meet the requirement on speed, and the speed can be increased only by converting the common algorithms into hardware realization. Thus, the refinement and addition of these algorithms to instructions integrates one direction of processor evolution.

Disclosure of Invention

At least one embodiment of the present disclosure provides a test method for a decoding unit, including: acquiring a target instruction; acquiring a set of approximate instruction codes according to the target instruction, wherein the set of approximate instruction codes comprises a plurality of approximate instruction codes corresponding to the target instruction; acquiring a plurality of approximate instructions to be tested corresponding to the target instruction according to at least one legal format of the target instruction and the set of the approximate instruction codes; testing the plurality of approximate instructions under test using the decode unit.

For example, in a testing method provided in at least one embodiment of the present disclosure, acquiring a set of approximate instruction codes according to the target instruction includes: acquiring at least one legal instruction code of the target instruction; acquiring an instruction constraint table corresponding to the at least one legal instruction code; and acquiring the approximate instruction codes according to the instruction constraint table.

For example, in a testing method provided by at least one embodiment of the present disclosure, obtaining the plurality of approximate instruction codes according to the instruction constraint table includes: and randomly changing at least one of the at least one block of constituent area of each of the at least one legal instruction code to form a plurality of approximate instruction code sequences according to the instruction constraint table, and marking each of the plurality of approximate instruction code sequences for legality and marking at least one randomly changed constituent area of each of the plurality of approximate instruction code sequences to form the plurality of approximate instruction codes.

For example, in a testing method provided by at least one embodiment of the present disclosure, the at least one component area is a multi-block component area, the multi-block component area includes an operation code area, and one or more of the following areas are included: an instruction prefix region, an instruction map region, and an instruction operand region.

For example, in a testing method provided by at least one embodiment of the present disclosure, randomly altering at least one of the at least one block constituting regions of each of the at least one legal instruction codes to form a plurality of approximate instruction code sequences includes one or more of the following operations: carrying out constraint random operation of selecting a random value in a preset range on the instruction prefix region; carrying out constrained random operation of selecting a random value within a preset range on the instruction map area; performing cross randomization on the operation code region to select a random value; the constraint to validly distinguish the instruction operand regions is random to select a random value.

For example, in a testing method provided in at least one embodiment of the present disclosure, obtaining the plurality of approximate instruction codes according to the instruction constraint table further includes: checking uniqueness of each of the plurality of approximate instruction code sequences by judging consistency of at least one block constituting region of each of the plurality of approximate instruction codes.

For example, in a testing method provided in at least one embodiment of the present disclosure, acquiring a plurality of approximate instructions to be tested corresponding to the target instruction according to at least one legal format of the target instruction and the set of approximate instruction codes includes: randomly mixing each of the plurality of approximate instruction codes of the set of approximate instruction codes with each of the at least one legal format of the target instruction to obtain the plurality of approximate instructions to be tested.

For example, in a testing method provided in at least one embodiment of the present disclosure, the testing the plurality of approximate instructions to be tested using the decode unit includes: obtaining a plurality of tested instruction groups according to the plurality of similar instructions to be tested; obtaining a plurality of test cases, wherein each tested instruction group has a corresponding test case selected from the plurality of test cases; and testing each instruction group to be tested in the plurality of instruction groups in parallel by utilizing the plurality of test cases.

For example, in a testing method provided in at least one embodiment of the present disclosure, obtaining a plurality of instruction groups to be tested according to the plurality of approximate instructions to be tested includes: dividing the plurality of approximate instructions to be tested into a plurality of instruction groups to be tested; or, at least one legal instruction of the target instruction is obtained, the multiple to-be-tested approximate instructions and the at least one legal instruction are mixed to obtain an instruction mixing set, and all tested instructions included in the instruction mixing set are divided into the multiple tested instruction groups.

For example, in a testing method provided by at least one embodiment of the present disclosure, testing each of the multiple groups of instructions under test in parallel by using the multiple test cases includes: and for the decoding test of the current tested instruction corresponding to each tested instruction group, responding to the current tested instruction as an illegal instruction, and executing a jump operation so as to jump to the test of the next tested instruction after the current tested instruction is decoded.

For example, in a testing method provided by at least one embodiment of the present disclosure, executing a jump operation to jump to a test of the next instruction under test after the current instruction under test is decoded includes: a heavy-load exception response function; decoding the current instruction to be tested; in response to triggering an exception, executing the exception response function, directing a return address to an initial address of a next instruction under test to jump to testing of the next instruction under test, and in response to not triggering an exception, testing for an error.

For example, in a testing method provided by at least one embodiment of the present disclosure, testing each of the multiple groups of instructions under test in parallel by using the multiple test cases includes: for the decoding test of the corresponding current instruction to be tested in each instruction group to be tested, responding to the current instruction to be tested as a legal instruction: responding to the condition that an exception is not triggered and the decoding execution result of the current instruction to be tested is inconsistent with an expected result, and testing for an error; directly jumping to the decoding test of the next instruction to be tested in response to the condition that the exception is not triggered and the decoding execution result of the current instruction to be tested is consistent with the expected result; in response to a trigger exception, the test is error-free.

At least one embodiment of the present disclosure provides a test system for a decoding unit, including: an instruction acquisition module configured to acquire a target instruction; an approximate instruction code acquisition module configured to acquire a set of approximate instruction codes according to the target instruction, the set of approximate instruction codes including a plurality of approximate instruction codes corresponding to the target instruction; and the to-be-tested instruction acquisition module is configured to acquire a plurality of to-be-tested approximate instructions corresponding to the target instruction according to the legal format of the target instruction and the approximate instruction code set, wherein the plurality of to-be-tested approximate instructions are configured to be tested through the decoding unit.

At least one embodiment of the present disclosure provides an electronic device, including: a processor and a memory, wherein the memory has stored thereon a computer program which, when executed by the processor, implements a testing method as claimed in any one of the above.

At least one embodiment of the present disclosure provides a computer-readable storage medium, wherein the storage medium stores a computer program, and the computer program, when executed by a processor, implements the testing method as described in any of the above examples.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a schematic diagram of an instruction code;

FIG. 2 is a schematic diagram of decoding;

FIG. 3 is a schematic diagram of alignment of instructions;

FIG. 4 is a partial schematic view of an instruction map;

FIG. 5 is a flow chart of a test method for a decode unit according to some embodiments of the present disclosure;

fig. 6 is a flowchart of step S2 in fig. 5 according to some embodiments of the present disclosure;

fig. 7 is a flowchart of step S4 in fig. 5 according to some embodiments of the present disclosure;

FIG. 8 is a flowchart of a decode test of a corresponding current instruction under test in each instruction group under test according to some embodiments of the present disclosure;

FIG. 9 is a block diagram of a test system provided by some embodiments of the present disclosure; and

fig. 10 is a block diagram of an electronic device provided in some embodiments of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The use of "first," "second," and similar terms in the embodiments of the disclosure is not intended to indicate any order, quantity, or importance, but rather to distinguish one element from another. The use of the terms "a" and "an" or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. Likewise, the word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Flow charts are used in the disclosed embodiments to illustrate the steps of a method according to an embodiment of the disclosure. It should be understood that the preceding and following steps are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations may be added to the processes, or a certain step or steps may be removed from the processes.

Currently, the instruction code of some complex instruction sets generally consists of four regions, namely, an instruction Prefix (Prefix), an instruction Map (Map), an operation code (Opcode) and an instruction Operand (Operand), and for example, the decoding order is performed in the order of Prefix- > Map- > Opcode- > Operand, as shown in fig. 1. When the instruction does not meet the above instruction format, the instruction is considered to belong to an illegal instruction code.

As shown in fig. 1, the instruction prefix is used to distinguish certain specific instruction sets (e.g., to mark an added instruction set) or to override the behavior of an original instruction set. The instruction map is used to mark the instruction map (e.g., to refer to a particular instruction table). The operation code is used for marking a unique position in a specific instruction map, so that the decoding entry and core behavior of the instruction are agreed, namely the operation code represents the unique coding position in the specified instruction map and represents the basic behavior of the instruction. The instruction operands represent the original operands required by the instruction and may be carried or expanded using a convention format.

As shown in fig. 2, the inventors of the present disclosure found that the decoding process includes: firstly, judging whether the instruction needs to be reloaded or not and whether the instruction belongs to a certain specific instruction set or not according to the instruction prefix, finding a corresponding instruction map inlet according to the instruction map, finding a unique coding position in the specified instruction map according to the operation code, finally analyzing the instruction operand, and ending decoding.

As shown in fig. 3, the operation code codes of the instruction a and the instruction b are the same, but the instruction a and the instruction b belong to different instruction maps, and therefore the instruction a and the instruction b are not the same instruction. For example, instruction b and instruction c have the same instruction map and opcode encoding, but when instruction prefix a is an instruction set tag, instruction b and instruction c are not the same instruction. For example, instruction d and instruction e belong to different forms of the same instruction when instruction prefix B and instruction prefix C are both simple instruction reloads.

In this regard, the inventors of the present disclosure have discovered that a single instruction, in addition to being characterized by a unique opcode, has some format constraints, such as not allowing certain specific instruction prefixes to be carried. For example, if the convention instruction c does not support the instruction prefix B, but the instruction prefix B is added to the encoding of the instruction c when the decoding unit is input, the instruction code of the current instruction is considered to belong to an illegal instruction code. Thus, the instruction code that does not satisfy the instruction constraint belongs to an illegal instruction code.

As shown in fig. 4, the horizontal direction is the low 4-bit hexadecimal coding of the opcode and the vertical direction is the high 4-bit hexadecimal coding of the opcode. For example, there are only four defined commands A/B/C/D in the command map, and the opcode encoding is 0x22/0x21/0x42/0x44 in order. Then for instruction a, the encoding of instruction B and instruction C differs by only 4 bits from instruction a, which may be referred to as the approximate instruction of instruction a. Instruction D encodes an approximate instruction that is completely different from instruction A and does not belong to instruction A. The undefined code is called an instruction hole (hole), i.e. a blank position in the instruction map where no valid instruction code is marked. Such as 0x33 or 0x23, which do not agree in the instruction map that the code represents, belong to the instruction hole. The instruction set will not generally fill the entire instruction map, and when the opcode portion of the instruction code falls on an instruction hole, the instruction code is considered to be an illegal instruction code.

Thus, the inventors of the present disclosure have found that, in general, when the instruction structure and instruction constraints are satisfied and a defined opcode exists in a unique instruction map, the opcode can be identified as a valid instruction code, and, conversely, as an invalid instruction code. That is, the defined instruction codes existing in the decoding table of the decoding unit are considered as legal instruction codes, otherwise, the defined instruction codes are all illegal instruction codes, i.e. all the defined legal instruction codes are removed, and the rest are illegal instruction codes.

The inventors of the present disclosure further found that the current application puts higher demands on the computation precision, for example, the basic function of the original instruction may need to be extended, or the operand precision may need to be extended, but it is not necessary to replace the instruction code, and at this time, some instruction prefixes may be added to reload the instruction, which needs to be supported by the decode unit.

The inventor of the present disclosure has also found that the expansion of the instruction set and the instruction reload impose new requirements on the verification of the decoding unit, for example, it is necessary to ensure that the newly added instruction is decoded normally, and at the same time, it is necessary to ensure that the approximate input is not translated into the existing or newly added correct instruction incorrectly, and the test traversal amount is relatively large.

To this end, at least one embodiment of the present disclosure provides a testing method for a decoding unit, including: acquiring a target instruction; acquiring a set of approximate instruction codes according to a target instruction, wherein the set of approximate instruction codes comprises a plurality of approximate instruction codes corresponding to the target instruction; acquiring a plurality of approximate instructions to be tested corresponding to the target instruction according to at least one legal format of the target instruction and a set of the approximate instruction codes; a plurality of approximate instructions to be tested are tested using a decode unit.

The testing method of the embodiment of the disclosure can comprehensively complete the verification of the target instruction (for example, the newly added instruction) and the approximate instruction of the target instruction, and verify whether the decoding unit can support the newly added instruction and normally work under the condition of the newly added target instruction.

Fig. 5 is a flowchart of a testing method for a decoding unit according to some embodiments of the present disclosure.

For example, as shown in fig. 5, a testing method for decoding units according to at least one embodiment of the present disclosure includes steps S1 to S4.

And step S1, acquiring a target instruction.

Step S2, acquiring a set of approximate instruction codes according to the target instruction, where the set of approximate instruction codes includes a plurality of approximate instruction codes corresponding to the target instruction.

Step S3, according to at least one legal format of the target instruction and the set of approximate instruction codes, obtaining a plurality of approximate instructions to be tested corresponding to the target instruction.

Step S4, a plurality of approximate instructions to be tested are tested by using the decode unit.

Therefore, the test method of the embodiment of the disclosure can complete verification of the target instruction (for example, the new instruction) and the approximate instruction of the target instruction more comprehensively, and verify whether the decoding unit can support the new instruction and whether the decoding unit can work normally under the condition of the new target instruction.

For example, in step S1, the target instruction is an instruction that needs to be newly added in the original instruction set. It should be noted that, the following description mainly takes the target instruction as the new instruction as an example, but the embodiments of the present disclosure are not limited to this.

In some examples, the number of the target instructions obtained may be one or more, and each target instruction may be tested according to steps S1 to S4. For example, the embodiment of the present disclosure may simultaneously perform the test according to the above steps S1 to S4 for a plurality of different target instructions.

In some examples, the instruction code is hexadecimal encoding of the corresponding instruction. This is merely an example and is not a limitation of the present disclosure, and for example, other binary codes may be used, which are not described herein.

Fig. 6 is a flowchart of step S2 in fig. 5 according to some embodiments of the present disclosure.

For example, as shown in fig. 6, for step S2, acquiring the set of approximate instruction codes according to the target instruction includes steps S21 to S23.

And step S21, acquiring at least one legal instruction code of the target instruction.

And step S22, acquiring an instruction constraint table corresponding to at least one legal instruction code.

And step S23, acquiring a plurality of approximate instruction codes according to the instruction constraint table.

Therefore, the embodiment of the disclosure generates a plurality of approximate instruction codes corresponding to the target instruction based on the legal instruction codes in the instruction constraint table, so that the workload can be reduced, for example, only the instruction constraint table needs to be maintained each time the target instruction is newly added, and other parts can be basically multiplexed, thereby having high efficiency and convenient operation.

In some examples, the instruction code includes at least one composition area. For example, the at least one block constituting region includes an opcode region. For another example, the at least one constituent region is a multi-block constituent region, and the multi-block constituent region may include not only the opcode region but also one or more of an instruction prefix region, an instruction map region, and an instruction operand region, which is advantageous in that the test method can cover a sufficient number of test scenarios. This is merely exemplary and not limiting, for example, the instruction codes of the present disclosure may also be other configurations, which are not described herein again. It should be noted that, in the embodiment of the present disclosure, the bit width of each block constituting area of the instruction code is not limited, for example, the bit width of the operation code area may be 1bit or 2bit, which is not limited and described herein.

In some examples, at least one of the instruction prefix, the instruction map, and the instruction operand may not be carried when the instruction definition is performed. For example, an instruction may carry multiple instruction prefixes, and may not be carried when the underlying instruction set is used and no reloading is required. For example, the instruction map may not be carried when using the underlying instruction set. For example, instruction operands may not be carried when the original operands are not needed by the instruction.

For example, the test method of the embodiment of the present disclosure is applicable to any instruction that is decoded by looking up a table, that is, the specific form of the table is not limited, and is not described herein again.

The inventor of the present disclosure finds that, for verification in the case of adding a new target instruction, it is necessary to ensure not only the decoding correctness of the agreed legal instruction code format, but also the decoding correctness of the approximate instruction position that does not affect different instruction maps or different instruction maps, and to correctly identify an illegal instruction under the condition that the operation code is unique but the instruction prefix, the instruction map, and the instruction operand do not satisfy the constraints.

In some examples, a target instruction has multiple legal instruction codes, for example, A, B, C three legal instruction codes, for which, the instruction code scenario that the approximate instruction code of the target instruction can cover includes at least one of the following cases:

in the first case: only changing the operation code area of the legal instruction code, namely the corresponding acquired instruction code is an approximate instruction code which is positioned on the same instruction map as the target instruction, if the corresponding acquired instruction code is the defined or agreed legal instruction code, normally decoding the corresponding instruction instead of newly adding the instruction; if the command falls into the command hole, the illegal message is reported.

In the second case: only the instruction map area of the legal instruction code is changed, namely the correspondingly acquired instruction code is the same code which is positioned on a different instruction map with the target instruction, if the correspondingly acquired instruction code is the defined or agreed legal instruction code, the corresponding instruction is normally decoded instead of a newly added instruction, and if the correspondingly acquired instruction code falls in an instruction hole, the illegal instruction is reported.

In the third case: only changing the instruction prefix area of the legal instruction code, if the decoding table supports, normally decoding, and if the constraint is violated, reporting the illegal.

In a fourth case: only changing the instruction operand region of the legal instruction code, if the decoding table supports, decoding normally, if the constraint is violated, reporting illegally.

In the fifth case: and any two or more of the instruction prefix area, the instruction map area, the operation code area and the instruction operand area are changed, if the corresponding obtained instruction code has a legal instruction code, the corresponding instruction is decoded normally, and if the corresponding instruction code does not have the legal instruction code, the corresponding instruction is reported illegally.

In some examples, the alteration of the above embodiments may include an act of replacing a value, and may also include an act of deleting a value. It should be noted that, the scenarios that can be covered by the approximate instruction code of the target instruction in the foregoing embodiments are merely exemplary, and are not limiting of the embodiments of the present disclosure.

Thus, embodiments of the present disclosure are able to generate approximate instruction codes that cover a sufficient number of scenarios.

For example, for step S21, in some examples, the at least one legal instruction code corresponding to the target instruction may be a plurality of legal instruction codes, and the plurality of legal instruction codes corresponding to the target instruction are generally defined or agreed by the specification of the specific project.

For example, with respect to step S22, in some examples, the instruction constraint table corresponding to the at least one legal instruction code is obtained by adding the value of each block constituting region (e.g., Prefix, Map, Opcode, Operand) of all legal instruction codes of the target instruction to the instruction constraint table, that is, adding all legal instruction codes corresponding to the target instruction to the instruction constraint table, and can be used to generate the approximate instruction code and identify whether or not the generated approximate instruction code is legal. For example, all legal instruction codes corresponding to the target instruction can be manually added to the instruction constraint table, and all constraints in the instruction constraint table are correct legal instruction codes.

In some examples, based on the instruction constraint table corresponding to the previous item, if a new item is updated based on the instruction constraint table, and under the condition that a plurality of original legal instruction codes of the original instruction constraint table do not need to pay attention to or influence the new item, and the like, only the legal instruction codes need to be continuously added in the original instruction constraint table. This is merely an example and is not a limitation of embodiments of the present disclosure.

For example, for step S23, in some examples, obtaining a plurality of approximate instruction codes from the instruction constraint table includes the following steps or processes: according to the instruction constraint table, at least one of at least one block of composition area of each legal instruction code in at least one legal instruction code is randomly changed to form a plurality of approximate instruction code sequences, legality marking is carried out on each approximate instruction code sequence in the plurality of approximate instruction code sequences, and at least one composition area which is randomly changed in each approximate instruction code sequence in the plurality of approximate instruction code sequences is marked to form a plurality of approximate instruction codes. Thus, the testing method of the embodiment of the disclosure is not only efficient, but also can generate sufficiently comprehensive approximate instruction codes, and can cover most of the testing scenes needing verification, for example, the instruction code scenes related to the above embodiments.

In some examples, randomly altering at least one of the at least one block constituent regions of each of the at least one legal instruction code to form a plurality of approximate instruction code sequences includes one or more of: (a) carrying out constraint random operation of selecting a random value in a preset range on the instruction prefix region; (b) carrying out constrained random operation of selecting a random value within a preset range on the instruction map area; (c) performing cross randomization on the operation code region to select a random value; (d) the constraint of validity differentiation on instruction operand regions is random to select a random value. Therefore, the number of approximate instruction codes can be effectively reduced by carrying out the random operation under the constraint, a relatively reasonable set of approximate instruction codes for testing can be obtained, unnecessary invalid testing can be avoided, and the problem that the test convergence speed is seriously influenced due to the overlarge number magnitude of the obtained approximate instruction codes can also be avoided.

In some examples, for operations (a) and (b), with respect to the instruction prefix and the instruction map, there are fewer valid values and a random value may be chosen from a legal range, so that the problem of too many invalid tests due to the adoption of full randomness may be avoided.

In some examples, for operation (c), generally considering scalability, the bit width of the operation code is at least 1 byte, that is, at least 256 operation codes can be accommodated in one instruction table, so that by using a cross random method, that is, fixing the upper half part and the lower half part of the operation code respectively, and performing randomization on the remaining part, the problem that the magnitude of the obtained approximate instruction code is large due to using full random, which seriously affects the speed of test convergence can be avoided.

In some examples, for operation (d), due to the precision requirement of the instruction operand, there are typically too many valid values, and the randomness to the instruction operand region may only distinguish between valid and invalid, i.e., the constraint of distinguishing the validity of the instruction operand region is random to select a random value.

In some examples, the validity and invalidity of instruction operands may be determined according to the original definition of the instruction, i.e., defined valid and undefined invalid. For example, if the instruction convention supports 16 logical registers, then all 16 registers are valid operands, and if the instruction convention supports 32bit wide memory, then the addresses of 0x 0-0 xFFFFFFFF are valid operands.

In some examples, for operation (c), comprising: and selecting random values of the operation code areas of the legal instruction codes in the instruction constraint table, and keeping the values of other areas of the legal instruction codes unchanged, thereby obtaining corresponding approximate instruction codes. Similarly, for operations (a), (b), and (d), at least one component area of the legal instruction code in the instruction constraint table may be randomly selected, and the values of other component areas may be kept unchanged to obtain the corresponding approximate instruction code, which is not described herein again.

For marking the randomly changed composition area of each approximate instruction code sequence, in some examples, the marking may be performed by annotating, for example, a specific character sequence may be added after the approximate instruction code sequence and the character sequence may be customized as long as the character sequence is not mistaken for the instruction code, and the embodiment of the present disclosure is not limited thereto.

Similarly, the method for legality marking of each approximate instruction code sequence is similar to the method for marking the randomly changed component area of each approximate instruction code sequence, and reference may be made to the foregoing description, and details are not repeated here. Before the legality marking, the legality of the approximate instruction code sequence needs to be judged according to the instruction constraint table, which is not the key point of the description of the present disclosure and is not described herein again.

For example, for step S23, in some examples, obtaining the plurality of approximate instruction codes according to the instruction constraint table further comprises the steps or processes of: the uniqueness of each of the plurality of approximate instruction code sequences is checked by judging the consistency of at least one block constituting region of each of the plurality of approximate instruction codes. Therefore, unnecessary repeated tests caused by non-uniqueness of the approximate instruction codes are avoided, and the fact that the simulation time is prolonged due to the repeated tests is avoided. For example, when the four constituent regions (e.g., Prefix, Map, Opcode, Operand) of the randomly generated approximate instruction code and the previously generated approximate instruction code completely coincide, it is indicated that the currently generated approximate instruction code is not unique.

For example, for step S3, in some examples, obtaining a plurality of approximate instructions to be tested corresponding to the target instruction according to at least one legal format of the target instruction and the set of approximate instruction codes includes the following processes or steps: and randomly mixing each approximate instruction code in a plurality of approximate instruction codes of the set of approximate instruction codes with each approximate instruction code in at least one legal format of the target instruction to obtain a plurality of approximate instructions to be tested. Therefore, the embodiment of the disclosure can obtain a plurality of approximate instructions to be tested which are relatively reasonable and can cover enough test scenes.

The inventor of the present disclosure has found that, in general, for a processor of a complex instruction set, a plurality of instruction maps and a plurality of instruction prefixes are supported, a random range is relatively large, and thus, the number of instructions to be tested included in a finally generated set of instructions to be tested is generally ten thousand or hundred thousand, and if a single simulation task is used to serially complete the test on all instructions to be tested, although hardware resources may not be excessively occupied, a single simulation convergence time is very long, for example, the time may last for several days or ten days, and the long duration is basically unacceptable.

Fig. 7 is a flowchart of step S4 in fig. 5 according to some embodiments of the present disclosure.

For example, as shown in FIG. 7, for step S4, testing a plurality of approximate instructions to be tested using the decode unit includes steps S41 to S43.

And step S41, acquiring a plurality of tested instruction groups according to the plurality of to-be-tested approximate instructions.

And step S42, acquiring a plurality of test cases, wherein each tested instruction group has a corresponding test case selected from the plurality of test cases.

And step S43, testing each instruction group to be tested in the plurality of instruction groups in parallel by using the plurality of test cases.

Therefore, the embodiment of the disclosure realizes the traversal test of a plurality of tested instruction groups in parallel by adopting a plurality of test cases, can reduce the simulation time for completing the test of all tested instructions, can complete the verification work as soon as possible by utilizing limited hardware resources, and reduces the total simulation time.

In some examples, the parallel testing described above is implemented by way of LSF clustering. Therefore, parallel testing is easier to realize and manage, and expansibility is good. This is merely exemplary and not a limitation of the present disclosure, as long as the parallel testing of all the to-be-tested approximate instructions can be achieved, and the detailed description is omitted here.

For example, with respect to step S41, in some examples, obtaining a plurality of sets of instructions under test from a plurality of approximate instructions under test includes the following process or steps: and dividing the approximate instructions to be tested into a plurality of instruction groups to be tested. Therefore, the embodiment of the disclosure can realize the mixed test of the legal instruction and the illegal instruction, and the test method covers more test scenes.

For another example, with respect to step S41, in other examples, obtaining a plurality of sets of instructions under test from a plurality of approximate instructions under test includes the following processes or steps: the method comprises the steps of obtaining at least one legal instruction of a target instruction, mixing a plurality of approximate instructions to be tested and the at least one legal instruction to obtain an instruction mixing set, and dividing all tested instructions included in the instruction mixing set into a plurality of tested instruction groups. Thus, the test method disclosed by the embodiment of the disclosure has more covered scenes and longer simulation time.

It should be noted that, in the embodiment of the present disclosure, a legal instruction in the generated multiple approximate instructions to be tested can be rejected, and only an illegal instruction in the multiple approximate instructions to be tested is tested individually, so that the test condition is simpler and the simulation time is shorter. Since it is not a focus of the description of the present disclosure, it is not described in detail.

For example, with respect to step S43, in some examples, testing each of a plurality of groups of instructions under test with a plurality of test cases in parallel includes the following processes or steps: and for the decoding test of the current tested instruction corresponding to each tested instruction group, responding to the current tested instruction as an illegal instruction, executing a jump operation, so that after the current tested instruction is decoded, jumping to the test of the next tested instruction. Therefore, according to the embodiment of the disclosure, the overload operation can be selectively inserted according to the expected validity of the tested instruction, so that the test of the next tested instruction can be continued as soon as possible after the exception is triggered, and it is avoided that the simulation cannot be performed in sequence due to the jump fault caused by the illegal instruction decoding failure, that is, the embodiment of the disclosure can smoothly complete the traversal test of all the tested instructions.

In some examples, a plurality of generated approximate instructions to be tested are read by an automatic tool, the execution time of a single instruction to be tested and available hardware resources of a project are comprehensively considered, a plurality of test cases are adopted, and a plurality of simulation tasks are used for parallel simulation, so that the simulation time for completing the test of all the instructions to be tested can be reduced, and the number of parallel simulation tasks which can be simultaneously performed is limited by the hardware resources of a specific project.

In some examples, performing a jump operation to cause a jump to the test of the next instruction under test after the current instruction under test is decoded by execution includes the following processes or steps: (1) a heavy load Exception (Exception) response function; (2) decoding the current instruction to be tested; (3) in response to triggering the exception, an exception response function is executed that directs the return address to the initial address of the next instruction under test to jump to testing of the next instruction under test, and in response to not triggering the exception, the test reports an error. Therefore, the jump position is pointed to the beginning of the next instruction to be tested by directly reloading the response function, some instruction executions which are not concerned about can be reduced, and the simulation time is reduced.

For example, with respect to step S43, in some examples, testing each of a plurality of groups of instructions under test with a plurality of test cases in parallel includes the following processes or steps:

for the decoding test of the corresponding current instruction to be tested in each instruction group to be tested, responding to the fact that the current instruction to be tested is a legal instruction: if the exception is not triggered and the decoding execution result of the current instruction to be tested is inconsistent with the expected result, the test reports an error; if the exception is not triggered and the decoding execution result of the current instruction to be tested is consistent with the expected result, directly jumping to the decoding test of the next instruction to be tested; if the trigger exception is responded, the test is in error. Therefore, the embodiment of the disclosure can test the decoding condition of the decoding unit on the legal tested instruction.

FIG. 8 is a flowchart illustrating a decode test of a corresponding current instruction under test in each instruction group under test according to some embodiments of the present disclosure.

For example, as shown in FIG. 8, the decode test of the corresponding current instruction under test in each instruction group under test includes steps T41 through T49.

And step T41, starting the decoding test of the current instruction to be tested.

Step T42, judging whether the current detected instruction is illegal: if yes, go on to step T43; if not, go to step T47.

Step T43, reload the exception response function, and point the return address to the initial address of the next instruction under test.

And step T44, decoding the current instruction to be detected.

Step T45, judging whether the current detected instruction triggers abnormity: if yes, go on to step T46; if not, go to step T49.

And step T46, executing the abnormal response function, jumping to the test of the next tested instruction, regarding the next tested instruction as the current tested instruction of the next test, and then turning to step T41 to execute circularly until the test of all tested instructions in the tested instruction group is completed.

Step T47, judging whether the current detected instruction triggers abnormity: if yes, go to step T49; if not, go to step T48.

Step T48, determining whether the decoding execution result of the current instruction to be tested is inconsistent with the expected result: if yes, go to step T49; if not, go to step T46.

And step T49, testing and reporting errors.

In some examples, the determination in step T45 that the current instruction under test does not trigger an exception is transferred to the test of step T49 to report an error, which indicates that the decoding unit failed to decode the illegal instruction under test.

In some examples, the determination in step T47 that the current instruction under test does not trigger an exception is transferred to the test of step T49 to report an error, which indicates that the decoding unit failed to decode the valid instruction under test.

In some examples, in step T48, it is determined that the decoding execution result of the current instruction under test is inconsistent with the expected result, which indicates that the decoding unit has failed to decode the valid instruction under test, for example, there is a possibility that an error occurs in the operation code generated after decoding.

In some examples, in step T48, it is determined that the decoding execution result of the current instruction under test is consistent with the expected result, that is, the exception is not triggered and the execution result is correct, which indicates that the decoding is successful and the decoding unit is working normally.

Therefore, each single test case in the multiple test cases adopted by the embodiment of the disclosure can complete the test of multiple tested instructions, so that the traversal test of all tested instructions can be completed quickly by using relatively reasonable resources, and the verification convergence is accelerated.

Fig. 9 is a block diagram of a test system for a decode unit according to some embodiments of the present disclosure.

For example, as shown in fig. 9, a test system 100 for a decode unit according to at least one embodiment of the present disclosure includes an instruction obtaining module 101, an approximate instruction code obtaining module 102, and an instruction to be tested obtaining module 103. The instruction fetch module 101 is configured to fetch a target instruction. The approximate instruction code obtaining module 102 is configured to obtain a set of approximate instruction codes according to the target instruction, where the set of approximate instruction codes includes a plurality of approximate instruction codes corresponding to the target instruction. The to-be-tested instruction obtaining module 103 is configured to obtain a plurality of to-be-tested approximate instructions corresponding to the target instruction according to the legal format and the approximate instruction code set of the target instruction, where the plurality of to-be-tested approximate instructions are configured to be tested by the decoding unit 301.

It should be noted that, in the embodiment of the present disclosure, the test system 100 for decoding units may include more or less modules, and the connection relationship between the modules is not limited and may be determined according to actual requirements. The specific configuration of each module is not limited. For technical effects of the test system 100 for decoding units, reference may be made to technical effects of the test method for decoding units provided in the above embodiments of the present disclosure, which are not described herein again.

The various modules in the above embodiments may each be configured as software, hardware, firmware, or any combination thereof that performs a particular function. For example, the modules may correspond to an application specific integrated circuit, to pure software code, or to a combination of software and hardware.

It should be noted that, although the test system for the decoding unit is described above as being divided into modules for respectively performing corresponding processes, it is clear to those skilled in the art that the processes performed by the modules may be performed without any specific module division by the test system or without explicit delimitation between the modules.

Fig. 10 is a schematic structural diagram of an electronic device according to at least one embodiment of the present disclosure. The terminal device in the embodiments of the present disclosure may include, but is not limited to, a mobile terminal such as a mobile phone, a notebook computer, a digital broadcast receiver, a PDA (personal digital assistant), a PAD (tablet computer), a PMP (portable multimedia player), a vehicle terminal (e.g., a car navigation terminal), and the like, and a stationary terminal such as a digital TV, a desktop computer, and the like. The electronic device shown in fig. 10 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.

For example, as shown in fig. 10, in some examples, an electronic device 200 includes a processing apparatus (e.g., a central processing unit, a graphics processor, etc.) 201 that may perform the testing methods described above according to a program stored in a Read Only Memory (ROM)202 or a program loaded from a storage apparatus 208 into a Random Access Memory (RAM) 203. In the RAM203, various programs and data necessary for the operation of the computer system are also stored. The processing device 201, the ROM202 and the RAM203 are connected thereto via a bus 204. An input/output (I/O) interface 205 is also connected to bus 204.

For example, input devices 206 including, for example, a touch screen, touch pad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 207 including devices such as Liquid Crystal Displays (LCDs), speakers, vibrators, and the like; storage 208 including, for example, magnetic tape, hard disk, etc.; and a communication device 209 including a network interface card such as a LAN card, modem, or the like. The communication means 209 may allow the electronic apparatus 200 to perform wireless or wired communication with other apparatuses to exchange data, performing communication processing via a network such as the internet. A drive 310 is also connected to the I/O interface 205 as needed. A removable medium 311 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 310 as necessary, so that a computer program read out therefrom is mounted into the storage device 209 as necessary. While fig. 10 illustrates an electronic device 200 that includes various means, it is to be understood that not all illustrated means are required to be implemented or included. More or fewer devices may be alternatively implemented or included.

For example, the electronic device 200 may further include a peripheral interface (not shown in the figure) and the like. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning (lighting) interface, and the like. The communication device 209 may communicate with networks such as the internet, intranets, and/or wireless networks such as cellular telephone networks, wireless Local Area Networks (LANs), and/or Metropolitan Area Networks (MANs) and other devices via wireless communication. The wireless communication may use any of a number of communication standards, protocols, and technologies, including, but not limited to, global system for mobile communications (GSM), Enhanced Data GSM Environment (EDGE), wideband code division multiple access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and/or IEEE 802.11n standards), voice over internet protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and/or Short Message Service (SMS), or any other suitable communication protocol.

For example, the electronic device may be any device such as a mobile phone, a tablet computer, a notebook computer, an electronic book, a game machine, a television, a digital photo frame, and a navigator, and may also be any combination of electronic devices and hardware, which is not limited in this respect in the embodiments of the disclosure.

For example, the processes described above with reference to the flowcharts may be implemented as computer software programs, according to embodiments of the present disclosure. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a non-transitory computer readable medium, the computer program containing program code for performing the method illustrated by the flow chart. In such an embodiment, the computer program may be downloaded and installed from a network via the communication means 209, or installed from the storage means 208, or installed from the ROM 202. The computer program, when executed by the processing device 201, performs the above-described test functions for the decoding unit as defined in the method of the embodiments of the present disclosure.

It should be noted that the computer readable medium in the present disclosure can be a computer readable signal medium or a computer readable storage medium or any combination of the two. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In embodiments of the disclosure, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In embodiments of the present disclosure, however, a computer readable signal medium may comprise a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, optical cables, RF (radio frequency), etc., or any suitable combination of the foregoing.

In some embodiments, the clients, servers may communicate using any currently known or future developed network protocol, such as HTTP (HyperText transfer protocol), and may be interconnected with any form or medium of digital data communication (e.g., a communications network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), the Internet (e.g., the Internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future developed network.

The computer readable medium may be embodied in the electronic device; or may exist separately without being assembled into the electronic device.

It should be noted that, in the embodiment of the present disclosure, reference may be made to the above description on the test method for the decoding unit for specific functions and technical effects of the electronic device 200, and details are not described here.

The following points need to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims

1. A test method for a coding unit, comprising:

acquiring a target instruction;

acquiring a set of approximate instruction codes according to the target instruction, wherein the set of approximate instruction codes comprises a plurality of approximate instruction codes corresponding to the target instruction;

acquiring a plurality of approximate instructions to be tested corresponding to the target instruction according to at least one legal format of the target instruction and the set of the approximate instruction codes;

testing the plurality of approximate instructions under test using the decode unit.

2. The test method of claim 1, wherein fetching a set of approximate instruction codes according to the target instruction comprises:

acquiring at least one legal instruction code of the target instruction;

acquiring an instruction constraint table corresponding to the at least one legal instruction code;

and acquiring the approximate instruction codes according to the instruction constraint table.

3. The testing method of claim 2, wherein obtaining the plurality of approximate instruction codes according to the instruction constraint table comprises:

and randomly changing at least one of the at least one block of constituent area of each of the at least one legal instruction code to form a plurality of approximate instruction code sequences according to the instruction constraint table, and marking each of the plurality of approximate instruction code sequences for legality and marking at least one randomly changed constituent area of each of the plurality of approximate instruction code sequences to form the plurality of approximate instruction codes.

4. The test method of claim 3,

the at least one block of component area is a multi-block component area, the multi-block component area includes an operation code area and includes one or more of the following areas: an instruction prefix region, an instruction map region, and an instruction operand region.

5. The test method of claim 4, wherein randomly altering at least one of the at least one block constituent regions of each of the at least one legal instruction codes to form a plurality of approximate instruction code sequences comprises one or more of:

carrying out constraint random operation of selecting a random value in a preset range on the instruction prefix region;

carrying out constrained random operation of selecting a random value within a preset range on the instruction map area;

performing cross randomization on the operation code region to select a random value;

the constraint to validly distinguish the instruction operand regions is random to select a random value.

6. The test method of claim 4, wherein obtaining the plurality of approximate instruction codes according to the instruction constraint table further comprises:

checking uniqueness of each of the plurality of approximate instruction code sequences by judging consistency of at least one block constituting region of each of the plurality of approximate instruction codes.

7. The test method according to any one of claims 1 to 6, wherein obtaining a plurality of approximate instructions to be tested corresponding to the target instruction according to at least one legal format of the target instruction and the set of approximate instruction codes comprises:

randomly mixing each of the plurality of approximate instruction codes of the set of approximate instruction codes with each of the at least one legal format of the target instruction to obtain the plurality of approximate instructions to be tested.

8. The method of any of claims 1-6, wherein testing the plurality of approximate instructions to be tested using the decode unit comprises:

obtaining a plurality of tested instruction groups according to the plurality of similar instructions to be tested;

obtaining a plurality of test cases, wherein each tested instruction group has a corresponding test case selected from the plurality of test cases;

and testing each instruction group to be tested in the plurality of instruction groups in parallel by utilizing the plurality of test cases.

9. The test method of claim 8, wherein fetching a plurality of instruction groups under test from the plurality of approximate instructions under test comprises:

dividing the plurality of approximate instructions to be tested into a plurality of instruction groups to be tested; alternatively, the first and second electrodes may be,

and acquiring at least one legal instruction of the target instruction, mixing the plurality of approximate instructions to be tested and the at least one legal instruction to obtain an instruction mixing set, and dividing all tested instructions included in the instruction mixing set into the plurality of tested instruction groups.

10. The testing method of claim 9, wherein testing each of the plurality of groups of instructions under test with the plurality of test cases in parallel comprises:

and for the decoding test of the current tested instruction corresponding to each tested instruction group, responding to the current tested instruction as an illegal instruction, and executing a jump operation so as to jump to the test of the next tested instruction after the current tested instruction is decoded.

11. The method for testing as defined in claim 10, wherein performing a jump operation to cause a jump to the test of the next instruction under test after the current instruction under test is decoded comprises:

a heavy-load exception response function;

decoding the current instruction to be tested;

in response to triggering an exception, executing the exception response function, directing a return address to an initial address of a next instruction under test to jump to testing of the next instruction under test, and in response to not triggering an exception, testing for an error.

12. The testing method of claim 9, wherein testing each of the plurality of groups of instructions under test with the plurality of test cases in parallel comprises:

for the decoding test of the corresponding current instruction to be tested in each instruction group to be tested, responding to the current instruction to be tested as a legal instruction,

responding to the condition that an exception is not triggered and the decoding execution result of the current instruction to be tested is inconsistent with an expected result, and testing for an error;

directly jumping to the decoding test of the next instruction to be tested in response to the condition that the exception is not triggered and the decoding execution result of the current instruction to be tested is consistent with the expected result;

in response to a trigger exception, the test is error-free.

13. A test system for a decode unit, comprising:

an instruction acquisition module configured to acquire a target instruction;

an approximate instruction code acquisition module configured to acquire a set of approximate instruction codes according to the target instruction, the set of approximate instruction codes including a plurality of approximate instruction codes corresponding to the target instruction;

and the to-be-tested instruction acquisition module is configured to acquire a plurality of to-be-tested approximate instructions corresponding to the target instruction according to the legal format of the target instruction and the approximate instruction code set, wherein the plurality of to-be-tested approximate instructions are configured to be tested through the decoding unit.

14. An electronic device, comprising:

a processor and a memory, wherein the processor is capable of processing a plurality of data,

wherein the memory has stored thereon a computer program which, when executed by the processor, implements the testing method of any one of claims 1 to 12.

15. A computer-readable storage medium, wherein a computer program is stored in the storage medium, which computer program, when being executed by a processor, carries out the testing method of any one of claims 1 to 12.