CN114063538A

CN114063538A - Intelligent control circuit of circuit breaker

Info

Publication number: CN114063538A
Application number: CN202111538695.5A
Authority: CN
Inventors: 姚卫东; 宋玉锋; 申海群; 李成成; 夏文; 高修荣; 朱江燕; 王剑; 李海峰; 陈超
Original assignee: Jiangsu Modern Electric Technology Co ltd
Current assignee: Jiangsu Modern Electric Technology Co ltd
Priority date: 2021-12-16
Filing date: 2021-12-16
Publication date: 2022-02-18
Anticipated expiration: 2041-12-16
Also published as: CN114063538B

Abstract

The invention discloses an intelligent control circuit of a circuit breaker, which comprises a core module, a first conditioning circuit, a second conditioning circuit, a frequency sampling circuit, a clock circuit, a signal input circuit, a control output circuit, a communication circuit module and a power module, wherein the core module comprises a control chip, a metering chip, an AD chip, a storage chip and an encryption chip. The invention adopts a single chip for control, simplifies the structure of the whole control circuit, reduces the number of main chips and reduces the whole power consumption.

Description

Intelligent control circuit of circuit breaker

Technical Field

The invention relates to a control circuit, in particular to an intelligent control circuit of a circuit breaker, and belongs to the field of intelligent circuit breakers.

Background

The outdoor vacuum circuit breaker is named because arc extinguishing media and insulating media of a contact gap after arc extinguishing are high vacuum; the arc extinguishing device has the advantages of small volume, light weight, suitability for frequent operation and no need of maintenance for arc extinguishing, and is relatively popularized in power distribution networks. The primary and secondary fusion outdoor vacuum circuit breaker deeply fuses an alternating current sensor, a capacitor and a vacuum arc extinguish chamber to replace an electromagnetic PT, and eliminates hidden troubles of ferromagnetic resonance and damage caused by lightning stroke. The capacitor power-taking technology is adopted to provide higher requirements for the power consumption of the circuit breaker controller.

Chinese patent publication No. CN109936219A discloses a circuit breaker intelligent control circuit, contain first control chip, the second control chip, the line loss module, three sets of conditioning circuits, frequency sampling circuit, clock circuit, first storage circuit, the second storage circuit, first signal input circuit, the second signal input circuit, control output circuit, alternating current-direct current converting circuit, battery charging control circuit, the battery, battery voltage measurement and loading circuit, voltage stabilizing circuit, motor drive circuit, encryption module, the GPS module, the WIFI module, temperature and humidity module and instruction output circuit. The intelligent control circuit in the prior art adopts double-chip control, the control logic and the structure are more complicated, the power consumption is higher, and the external power supply is not controlled.

Disclosure of Invention

The invention aims to solve the technical problem of providing an intelligent control circuit of a circuit breaker, and reducing power consumption.

In order to solve the technical problems, the technical scheme adopted by the invention is as follows:

the utility model provides a circuit breaker intelligent control circuit which characterized in that: the device comprises a core module, a first conditioning circuit, a second conditioning circuit, a frequency sampling circuit, a clock circuit, a signal input circuit, a control output circuit, a communication circuit module and a power supply module, wherein the core module comprises a control chip, a metering chip, an AD chip, a storage chip and an encryption chip; the three-phase current IA, IB, IC and zero sequence current ILX are connected with an AD chip of the core module through a first conditioning circuit, the three-phase voltage UA, UB, UC and zero sequence voltage ULX are connected with the AD chip of the core module through a second conditioning circuit, and the three-phase voltage UA is connected with an I/O port line of a control chip of the core module through a frequency sampling circuit; the signal input circuit is connected with an I/O port line of a control chip of the core module; the control output circuit is connected with an I/O port line of a control chip of the core module; the AD chip is connected with the parallel data port of the control chip; the storage chip is connected with the SPI port of the control chip through a line; the input direct-current voltage generates stable voltage through the power supply module to supply power to each module; the three-phase currents IA, IB and IC are connected with a metering chip of the core module through a first conditioning circuit; the three-phase voltages UA, UB and UC are connected with a metering chip of the core module through a second conditioning circuit; the metering chip is connected with the SPI port of the control chip through a line, the encryption chip is connected with the SPI port of the control chip through a line, and the clock circuit is connected with 3I/O ports of the core module through lines.

Further, the communication circuit module contains GPS module, WIFI module, industry special wireless module, man-machine contact module and network communication module, industry special wireless module and core module's serial port connection, network communication module and core module's serial port connection, man-machine contact module and core module's IO mouth line connection, WIFI module and core module's serial port connection, GPS module and core module's serial port connection.

Furthermore, the power module comprises a battery charging control circuit, a battery measuring and loading circuit and a voltage stabilizing circuit, wherein an input direct current voltage is respectively connected with the voltage stabilizing circuit, the battery measuring and loading circuit and the battery charging control circuit, the battery charging control circuit is connected with the battery, the battery is connected with the battery measuring and loading circuit, the battery measuring and loading circuit is connected with the core module, and the voltage stabilizing circuit generates a stable voltage to supply power to each module.

Further, the control chip adopts an ARM microprocessor STM32F series chip U, the metering chip adopts an ATT7022 metering chip U, 1 pin of the U is connected with one end of a resistor R and one end of a capacitor C, the other end of the resistor R is connected with 3.3V, the other end of the capacitor C is connected with VSS, 2 pins of the U are connected with one end of the resistor R, the other end of the resistor R is connected with 3V, 3 pins of the U are connected with one end of the resistor R and one end of a resistor R, the other end of the resistor R is connected with one end of the resistor R, the other end of the resistor R and the other end of the resistor R are connected with one end of the resistor R and VSS, 4 pins of the U are connected with the other end of the resistor R, 6 pins of the U are connected with one end of the resistor R and one end of the resistor R, the other end of the resistor R is connected with one end of the resistor R, the other end of the resistor R and the other end of the resistor R are connected with one end of the resistor R and VSS, the other end of the resistor R is connected with 7 pins of the U, a pin 9 of the U2 is connected with one end of a resistor R9 and one end of a resistor R10, the other end of the resistor R9 is connected with one end of a resistor R11, the other end of a resistor R11 is connected with one end of a resistor R12, the other end of the resistor R10 and the other end of a resistor R12 are connected with one end of a resistor R30 and VSS, the other end of the resistor R30 is connected with a pin 10 of the U2, a pin 11 of the U2 is connected with a pin 15 of the U2, a pin 13 of the U2 is connected with one end of a resistor R14 and one end of a resistor R15, the other end of the resistor R14 is connected with one end of a resistor R16, the other end of the resistor R16 is connected with one end of a resistor R17, the other end of the resistor R15 and the other end of the resistor R17 are connected with one end of the resistor R31 and VSS, the other end of the resistor R31 is connected with a pin 14 of the U31, a pin 16 of the resistor R31 and one end of the resistor R31, the other end of the resistor R31 is connected with one end of the resistor R3617, and the other end of the resistor R31 are connected with one end of the resistor R3617, the other end of the U is connected with one end of a resistor R and one end of the resistor R, the other end of the resistor R is connected with one end of the resistor R, the other end of the resistor R and the other end of the resistor R are connected with one end of the resistor R and VSS, the other end of the resistor R is connected with 20 pins of the U, 21 pins of the U are connected with one end of the resistor R, one end of the resistor R and one end of a capacitor C, the other end of the resistor R is connected with one end of the capacitor C and VSS, 22 pins of the U are connected with one end of the resistor R and one end of the resistor C, the other end of the resistor R is connected with the other end of the capacitor C and VSS, 23, 24, 32, 33 and 44 pins of the U are connected with VSS, one end of the capacitor C and one end of the capacitor C are connected with VSS, the other end of the capacitor C is connected with one end of the crystal oscillator tube X and the other end of the U42 pins; an AD chip adopts an 8-channel 16-bit AD7066 chip U3,

pins

1, 48, 38 and 37 of U3 are connected with the anode of a capacitor C68, one end of a capacitor C59 and +5V,

pins

2, 47, 41 and 40 of U3 are connected with the cathode of a capacitor C68, the other end of the capacitor C59 and VSS,

pins

44 and 45 of U3 are connected with one end of a capacitor C63, the other end of the capacitor C63 is connected with one end of a capacitor C63,

pins

46 and 43 of U63 and VSS, the other end of the capacitor C63 is connected with pin 42 of U63, pin 36 of U63 is connected with one end of a capacitor C63, pin 39 of U63 is connected with one end of a capacitor C63, the other end of U63 and the other end of the capacitor C63 are connected with VSS, pin 23 of U63 is connected with 3.3V, pin 26 of U63 is connected with pin 26,

pins

8, 7, 6 and 34 of U63 are respectively connected with

pins

1, 2, VSS of a resistor module R63, pin 3 and pin 3R 72 are connected with a capacitor module R72, pin 3 is connected with a resistor module R72, pin 3 and a resistor module R72,

pins

3, 4 and 5 of U3 are connected with VSS; the encryption chip adopts a Beijing intelligent chip micro U4, wherein a pin 1 of U4 is connected with VSS, a pin 8 of U4 is connected with a D pole of a field effect tube V1 and one end of a capacitor C58, the other end of the capacitor C58 is connected with VSS, a G pole of the field effect tube V1 is connected with one end of a resistor R41, and the other end of the resistor R41 is connected with an S pole of a field effect tube V1 and 3.3V; the memory chip adopts a W25Q16 chip U5, the

pins

3, 7 and 8 of U5 are connected with 3.3V, and the pin 4 of U5 is connected with VSS.

Furthermore, the first conditioning circuit and the second conditioning circuit respectively comprise 4 conditioning circuits, each conditioning circuit comprises an operational amplifier U9A, a pin 3 of U9A is connected with one end of a resistor R59, a pin 2 of U9A is connected with one end of a resistor R44, and the other end of the resistor R44 is connected with a pin 1 of U9A.

Furthermore, the frequency sampling circuit comprises an operational amplifier U10A, wherein a pin 2 of U10A is connected with one end of a resistor R58, a pin 4 of U10A is connected with-12 VCL, a pin 3 of U10A is connected with one end of a resistor R97 and one end of a resistor R95, the other end of the resistor R97 is connected with VSS, a pin 8 of U10A is connected with 12VCL, and the other end of the resistor R95 is connected with a pin 1 of U10A and one end of a resistor R96.

Furthermore, the clock circuit adopts a DS1302 chip U6, a pin 2 of U6 is connected with one end of a crystal oscillator tube Y1, a pin 3 of U6 is connected with the other end of a crystal oscillator tube Y1, a pin 4 of U6 is connected with VSS, a pin 8 of U6 is connected with the positive electrode of a battery BT1, and the negative electrode of the battery BT1 is connected with VSS.

Furthermore, the signal input circuit comprises a photoelectric coupler ISO7, a K pin of a photoelectric coupler ISO7 is connected with an I/O port of a control chip U1, a pin A of the photoelectric coupler ISO7 is connected with one end of a resistor R133, the other end of the resistor R133 is connected with 3.3V, a pin E of the photoelectric coupler ISO7 is connected with 24VGND, a pin C of the photoelectric coupler ISO7 is connected with one end of a resistor R122, the other end of the resistor R122 is connected with one end of a resistor R155 and a pin G of a field-effect tube V10, a pin S of the field-effect tube V10 and the other end of the resistor R155 are connected with ZB24V, a pin D of the field-effect tube V10 is connected with one end of a resistor R57, the other end of the resistor R57 is connected with a pin A of the photoelectric coupler ISO6, a pin E of the photoelectric coupler ISO6 is connected with VSS, a pin C of the photoelectric coupler ISO6 is connected with one end of a resistor R51, and the other end of the resistor R51 is connected with 3.3V; the control output circuit comprises a photoelectric coupler Q14, wherein a pin A of a photoelectric coupler Q14 is connected with one end of a resistor R111, the other end of the resistor R111 is connected with 3.3V, a pin C of the photoelectric coupler Q14 is connected with KZ24V, a pin E of the photoelectric coupler Q14 is connected with one end of a resistor R103, the other end of the resistor R103 is connected with one end of a resistor R36 and a pole G of a field effect transistor V7, and the pole S of the field effect transistor and the other end of the resistor R36 are connected with 24 VGND.

Further, the battery measuring and loading circuit comprises a resistor R48, one end of the resistor R48 is connected with KEY +, the other end of the resistor R48 is connected with the positive electrode of the battery BT2, one end of the resistor R55 and the S pole of a field effect transistor V4, the negative electrode of the battery BT2 is connected with one end of a resistor R39, the E pin and 24VGND of a transistor Q20, the other end of the resistor R39 is connected with KZBAST and the B pin of a transistor Q20, the C pin of a transistor Q20 is connected with one end of a resistor R54 and the C pin of a transistor Q54, the other end of the resistor R54 is connected with the other end of a resistor R54 and the G pole of a field effect transistor V54, the E pin of the transistor Q54 is connected with one end of a resistor R54 and 24VGND, the B pin of the transistor Q54 is connected with the other end of the resistor R54 and one end of a resistor R54, the other end of the resistor R54 is connected with KEY-, the D pole of the field effect transistor V54 is connected with the anode of a diode D54 and one end of a variable resistor W36123, the other end of the resistor R123 is connected with a pin A of a photoelectric coupler TF1 and a pin C of a photoelectric coupler TF2, a pin K of the photoelectric coupler TF1 is connected with the anode of a diode D32, the cathode of the diode D32 is connected with one end of a resistor R124, the other end of the resistor R124 is connected with a pin E and a pin 24VGND of a photoelectric coupler TF2, a pin C of a photoelectric coupler TF1 is connected with 3.3V, a pin E of the photoelectric coupler TF1 is connected with one end of a resistor R126 and one end of a resistor R98, the other end of the resistor R98 is connected with a pin A of the photoelectric coupler TF2 and one end of a resistor R100, and a pin K of the photoelectric coupler TF2 is connected with the other end of the resistor R100 and the VSS; the battery charging control circuit comprises a photocoupler Q25, a pin A of a photocoupler Q25 is connected with one end of a resistor R52, the other end of a resistor R52 is connected with 3.3V, a pin C of the photocoupler Q25 is connected with one end of a resistor R53, the other end of a resistor R53 is connected with one end of a resistor R38 and a pole G of a field-effect tube V5, the other end of a resistor R38 is connected with the pole S of the field-effect tube, the cathode of a diode D20 and the anode of a diode D45, the pole D of the field-effect tube V5 is connected with one end of a resistor R50, the other end of the resistor R50 is connected with the anode of a diode D46, the cathode of a diode D46 is connected with the anode of a battery BT2, and a pin E of the photocoupler Q25 is connected with the cathode of a battery BT2 and 24 VGND.

Further, the wireless module for the special industry work comprises a field effect transistor V3, the D pole of the field effect transistor V3 is connected with G24V, the S pole of the field effect transistor V3 is connected with one end of a resistor R93 and ZB24V, the G pole of the field effect transistor V3 is connected with the other end of a resistor R93 and one end of a resistor R46, the other end of the resistor R46 is connected with the C pin of a photoelectric coupler Q21, the E pin of the photoelectric coupler Q21 is connected with 24VGND, the A pin of the photoelectric coupler Q21 is connected with one end of a resistor R92, the other end of the resistor R92 is connected with 3.3V, the K pin of the photoelectric coupler Q21 is connected with the anode of a diode D30, the cathode of the diode D30 is connected with KZ31, the 24VGND is connected with

pins

1 and 4 of an interface GX1, and the 2 pin of an interface GX1 is connected with G24V; an ESP-07S module U7 is adopted as a WIFI module, a pin 1 of U7 is connected with one end of a resistor R37, a pin 3 of U7 is connected with one end of a resistor R40, a pin 8 of U7 is connected with the other end of a resistor R37, the other end of a resistor R40, the anode of a capacitor C2 and the D pole of a field-effect tube V2, the S pole of the field-effect tube V2 is connected with +3.3V and one end of a resistor R35, the other end of the resistor R35 is connected with the G pole of a field-effect tube V2, and the cathode of the capacitor C2 is connected with a pin 15 of U7 and VSS; the GPS module adopts an ST-26_ U7L chip U8, a pin 9 of U8 is connected with one end of a reactor L3,

pins

10 and 12 of U8 are connected with VSS, a pin 11 of U8 is connected with the other end of a reactor L3 and a pin 1 of an interface XS1,

pins

2, 3 and 4 of the interface XS1 are connected with VSS, a pin 23 of U8 is connected with one end of a capacitor C51, the anode of a capacitor C52 and the cathode of a field effect tube V11, a pin 24 of U8 is connected with VSS, the other end of the capacitor C51 and the cathode of a capacitor C52, the S pole of the field effect tube V11 is connected with 3.3V and one end of a resistor R157, and the G pole of the field effect tube V11 is connected with the other end of the resistor R157; the voltage stabilizing circuit adopts a DC/DC module.

Compared with the prior art, the invention has the following advantages and effects: the intelligent control circuit of the circuit breaker is controlled by adopting a single chip, so that the structure of the whole control circuit is simplified, the number of main chips is reduced, and the whole power consumption is reduced; meanwhile, through a unique circuit structure design, the invention can control the peripheral power supply, thereby further reducing the power consumption of the control circuit.

Drawings

Fig. 1 is a schematic diagram of a circuit breaker intelligent control circuit of the present invention.

FIG. 2 is a circuit diagram of a metrology chip of the present invention.

Fig. 3 is a circuit diagram of an AD chip of the present invention.

Fig. 4 is a circuit diagram of an encryption chip of the present invention.

Fig. 5 is a circuit diagram of a memory chip of the present invention.

Fig. 6 is a circuit diagram of the conditioning circuit of the present invention.

Fig. 7 is a circuit diagram of a frequency sampling circuit of the present invention.

Fig. 8 is a circuit diagram of a clock circuit of the present invention.

Fig. 9 is a circuit diagram of a signal input circuit of the present invention.

Fig. 10 is a circuit diagram of the control output circuit of the present invention.

Fig. 11 is a circuit diagram of the battery measurement and documentation circuit of the present invention.

Fig. 12 is a circuit diagram of a battery charge control circuit of the present invention.

Fig. 13 is a circuit diagram of the proprietary wireless module of the present invention.

Fig. 14 is a circuit diagram of a WIFI module of the present invention.

Fig. 15 is a circuit diagram of a GPS module of the present invention.

Detailed Description

To elaborate on technical solutions adopted by the present invention to achieve predetermined technical objects, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, it is obvious that the described embodiments are only partial embodiments of the present invention, not all embodiments, and technical means or technical features in the embodiments of the present invention may be replaced without creative efforts, and the present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

Fig. 1 shows an intelligent control circuit for a circuit breaker according to the present invention, which includes a core module 1, a first conditioning circuit 7, a second conditioning circuit 8, a frequency sampling circuit 9, a clock circuit 10, a signal input circuit 11, a control output circuit 12, a communication circuit module, and a power module, where the core module 1 includes a control chip 2, a metering chip 3, an AD chip 4, a storage chip 5, and an encryption chip 6. Three-phase currents IA, IB, IC and zero sequence current ILX are connected with an AD chip 4 of the core module 1 through a first conditioning circuit 7, three-phase voltages UA, UB, UC and zero sequence voltage ULX are connected with the AD chip 4 of the core module 1 through a second conditioning circuit 8, and the three-phase voltage UA is connected with an I/O port line of a control chip 2 of the core module 1 through a frequency sampling circuit 9; the signal input circuit 11 is connected with an I/O port line of the control chip 2 of the core module 1; the control output circuit 12 is connected with an I/O port line of the control chip 2 of the core module 1; the AD chip 4 is connected with the parallel data port of the control chip 2; the memory chip 5 is connected with the SPI port of the control chip 2 through a line; the input direct-current voltage generates stable voltage through the power supply module to supply power to each module; the three-phase currents IA, IB and IC are connected with the metering chip 3 of the core module 1 through a first conditioning circuit 7; the three-phase voltages UA, UB and UC are connected with the metering chip 3 of the core module 1 through a second conditioning circuit 8; the metering chip 3 is connected with the SPI port of the control chip 2, the encryption chip 6 is connected with the SPI port of the control chip 2, and the clock circuit 10 is connected with 3I/O ports of the core module 1.

The communication circuit module contains GPS module 13, WIFI module 14, special work wireless module 15, man-machine contact module 16 and network communication module 17, special work wireless module 15 and core module 1's serial port connection, network communication module 17 and core module 1's serial port connection, man-machine contact module 16 and core module 1's IO mouth line connection, WIFI module 14 and core module 1's serial port connection, GPS module 13 and core module 1's serial port connection.

The power supply module comprises a battery charging control circuit 18, a battery 19, a battery measuring and loading circuit 20 and a voltage stabilizing circuit 21, wherein an input direct-current voltage is respectively connected with the voltage stabilizing circuit 21, the battery measuring and loading circuit 20 and the battery charging control circuit 18, the battery charging control circuit 18 is connected with the battery 19, the battery 19 is connected with the battery measuring and loading circuit 20, the battery measuring and loading circuit 20 is connected with the core module 1, and the voltage stabilizing circuit generates a stable voltage to supply power to each module.

The control chip adopts an ARM microprocessor STM32F40 series chip U1, and the processor comprises an A/D conversion module, an SPI peripheral interface, a USART universal synchronous asynchronous receiver-transmitter, a timer and a universal I/O. And the functions of signal acquisition, data processing and storage, communication and the like are completed.

The metering chip adopts an ATT7022E metering chip U2, and the ATT7022E integrates a 7-path second-order sigma-delta ADC, a reference voltage circuit, and circuits for digital signal processing and the like for measuring all power, energy, effective values, power factors and frequencies, so that the active power, reactive power, apparent power, active energy and reactive energy of each phase and combined phases can be measured, and parameters such as each phase current, voltage effective values, power factors, phase angles, frequencies and the like can be measured. U1 pin connecting resistance R end and capacitance C end, resistance R other end connecting 3.3V, capacitance C other end connecting VSS, U2 pin connecting resistance R end, resistance R other end connecting 3.3V, U3 pin connecting resistance R end and resistance R end, resistance R other end connecting resistance R end and IACL, resistance R other end and resistance R other end connecting resistance R end and VSS, U4 pin connecting resistance R other end, U6 pin connecting resistance R end and resistance R end, resistance R other end connecting resistance R end and IBCL, resistance R other end and resistance R other end connecting resistance R end and VSS, resistance R other end connecting U7 pin, U9 pin connecting resistance R end and resistance R end, resistance R other end connecting resistance R end, the other end of the resistor R11 is connected with one end of a resistor R12 and ICCL, the other end of the resistor R10 and the other end of the resistor R12 are connected with one end of a resistor R30 and VSS, the other end of the resistor R30 is connected with a pin 10 of a U2, a pin 11 of the U2 is connected with a pin 15 of the U2, a pin 13 of the U2 is connected with one end of a resistor R14 and one end of a resistor R15, the other end of the resistor R14 is connected with one end of a resistor R16, the other end of the resistor R16 is connected with one end of a resistor R17 and UA3, the other end of the resistor R15 and the other end of a resistor R17 are connected with one end of a resistor R31 and VSS, the other end of the resistor R31 is connected with a pin 14 of the U31, a pin 16 of the U31 is connected with one end of the resistor R31 and one end of the R31, the other end of the resistor R31 is connected with one end of the U31 and the UB 31, the other end of the resistor R31 and the other end of the U31 is connected with one end of the resistor R31 and the U31, the other end of the resistor R31 and the other end of the U31 and the U31 is connected with the resistor R31, the other end of the U31 and the U31 is connected with the U31, the other end of the resistor R24 is connected with one end of a resistor R25 and UC3, the other end of the resistor R23 and the other end of the resistor R25 are connected with one end of a resistor R33 and VSS, the other end of the resistor R33 is connected with 20 pins of a U2, 21 pins of the U2 are connected with one end of a resistor R43, one end of the resistor R27 and one end of a capacitor C14, the other end of the resistor R43 is connected with one end of a resistor R26, the other end of the resistor R27 is connected with the other end of a capacitor C14 and VSS, 22 pins of the U2 are connected with one end of a resistor R34 and one end of a resistor C27, the other end of a resistor R34 is connected with the other end of a capacitor C27 and VSS, 23, 24, 32, 33 and 44 pins of the U2 are connected with VSS, one end of the capacitor C43 and one end of the capacitor C42 are connected with VSS, the other end of the capacitor C43 is connected with one end of a crystal tube X3 and a pin of the U2, and the other end of the capacitor C42 is connected with the other end of the crystal tube X3 and the pin of the U2. The AINB0 is connected with a pin 1 of the current conditioning circuit U9, and the AINB1, the AINB2 and the AINB3 are respectively connected with corresponding pins of the current conditioning circuit U9; the AINB4, the AINB5, the AINB6 and the AINB7 are respectively connected with corresponding output pins of the voltage conditioning circuit; IACL, IBCL, ICCL, I0, UA3, UB3, UC3 and VLX are respectively connected with corresponding input pins of the AD chip 3; AT _ CS, AT _ SCLK, AT _ SDO, AT _ SDI are connected to the SPI port of the control chip 2.

As shown in fig. 3, the AD chip employs an 8-channel 16-bit AD7066 chip U3 that samples the input synchronously, a 16-bit ADC, with a 200kSPS sampling rate.

Pins

1, 48, 38 and 37 of U3 are connected with the anode of a capacitor C68, one end of the capacitor C59 and +5V,

pins

2, 47, 41 and 40 of U3 are connected with the cathode of the capacitor C68, the other end of the capacitor C59 and VSS,

pins

44 and 45 of U3 are connected with one end of a capacitor C63, the other end of the capacitor C63 is connected with one end of a capacitor C64,

pins

46 and 43 of U3 and VSS, the other end of the capacitor C64 is connected with pin 42 of U3, pin 36 of U3 is connected with one end of a capacitor C65, pin 39 of U3 is connected with one end of a capacitor C66, pin 35 of U3, the other end of the capacitor C65 and the other end of the capacitor C66 are connected with VSS, a pin 23 of U3 is connected with 3.3V, a pin 26 of U3 is connected with VSS,

pins

8, 7, 6 and 34 of U3 are respectively connected with

pins

1, 2, 3 and 4 of the resistor module R42,

pins

5 and 7 of the resistor module R42 are connected with 3.3V and one end of the capacitor C69, the other end of the capacitor C69 is connected with a pin 11 of U3,

pins

6 and 8 of the resistor module R42 are connected with VSS, and

pins

3, 4 and 5 of U3 are connected with VSS; FSMC _ D0-FSMC _ D15 are connected to the data I/O port of the control chip 2.

As shown in FIG. 4, the encryption chip adopts a Beijing smart chip micro U4, wherein a pin 1 of U4 is connected with VSS, a pin 8 of U4 is connected with a D pole of a field effect transistor V1 and one end of a capacitor C58, the other end of the capacitor C58 is connected with VSS, a G pole of the field effect transistor V1 is connected with one end of a resistor R41, and the other end of the resistor R41 is connected with an S pole of a field effect transistor V1 and 3.3V. Flash2_ CS, Flash2_ MISO, Flash2_ SCK and Flash2_ MOSI are respectively connected to the SPI port line of the control chip 2.

As shown in FIG. 5, the memory chip adopts a W25Q16 chip U5, the

pins

3, 7 and 8 of U5 are connected with 3.3V, and the pin 4 of U5 is connected with VSS. Flash1_ CS, Flash1_ MISO, Flash1_ SCK and Flash1_ MOSI are respectively connected to the SPI port line of the control chip 2.

As shown in fig. 6, the first conditioning circuit and the second conditioning circuit respectively include 4 conditioning circuits, each conditioning circuit includes an operational amplifier U9A, a pin 3 of U9A is connected to one end of a resistor R59, a pin 2 of U9A is connected to one end of a resistor R44, and the other end of the resistor R44 is connected to a pin 1 of U9A. The operational amplifier U9A acts as a follower and acts as an impedance match.

As shown in fig. 7, the frequency sampling circuit includes an operational amplifier U10A, a pin 2 of U10A is connected to one end of a resistor R58, a pin 4 of U10A is connected to-12 VCL, a pin 3 of U10A is connected to one end of a resistor R97 and one end of a resistor R95, the other end of the resistor R97 is connected to VSS, a pin 8 of U10A is connected to 12VCL, and the other end of the resistor R95 is connected to a pin 1 of U10A and one end of a resistor R96. The AINB4 is connected with the output of the A-phase voltage conditioning circuit, one path of the anode of the operational amplifier U10 is grounded through a resistor R97, the other path of the anode of the operational amplifier U10 is connected with the output of the operational amplifier U10 through a resistor R95, the cathode of the operational amplifier is connected with voltage input AINB4 through a resistor R58, one path of the output of the operational amplifier is fed back to the anode of the operational amplifier through a resistor R95, and the other path of the output of the operational amplifier is connected with an I/O port of the control chip 2 through a resistor R96. The output of the operational amplifier is zero during the positive half cycle and high during the negative half cycle of the AINB4 ac voltage, converting the sine wave to a square wave. The control chip 2 calculates the frequency by measuring the time interval of the high and low square waves.

As shown in fig. 8, the clock circuit adopts a DS1302 chip U6, a pin 2 of U6 is connected to one end of a crystal oscillator tube Y1, a pin 3 of U6 is connected to the other end of a crystal oscillator tube Y1, a pin 4 of U6 is connected to VSS, a pin 8 of U6 is connected to the positive electrode of a battery BT1, and the negative electrode of the battery BT1 is connected to VSS.

Pins

1 and 4 of the CLOCK circuit are connected with a power supply,

pins

2 and 3 are connected with a crystal oscillator, pins 8 are connected with a battery, and CLOCK _ SCLK, CLOCK _ IO and CLOCK _ RST are connected with an I/O port line of the control chip 2.

As shown in fig. 9, the signal input circuit includes a photocoupler ISO7, a pin K of the photocoupler ISO7 is connected to the I/O port of the control chip 2, a pin a of the photocoupler ISO7 is connected to one end of a resistor R133, the other end of the resistor R133 is connected to 3.3V, a pin E of the photocoupler ISO7 is connected to 24VGND, a pin C of the photocoupler ISO7 is connected to one end of a resistor R122, the other end of the resistor R122 is connected to one end of a resistor R155 and a pin G of a field effect transistor V10, a pin S of the field effect transistor V10 and the other end of the resistor R155 are connected to ZB24V, a pin D of the field effect transistor V10 is connected to one end of a resistor R57, the other end of the resistor R57 is connected to a pin a of the photocoupler ISO6, a pin E of the photocoupler ISO6 is connected to VSS, a pin C of the photocoupler ISO6 is connected to one end of a resistor R51, and the other end of the resistor R51 is connected to 3.3V. RDYXKZ is connected with an I/O port of the control chip 2, the control chip 2 is normally set to be high RDYXKZ, the optical coupler ISO7 is not conducted, the V10 is cut off, and YX24V is dead. When the signal state is read, the control chip 2 pulls down RDYXKZ, the optocoupler ISO7 is conducted, ZB24V supplies power to YX24V through V10, the signal YX1 is connected with the input negative electrode of the optocoupler, the output E electrode of the optocoupler is connected with the power ground VSS, the output C electrode of the optocoupler is connected with 3.3V through a resistor and is simultaneously connected with an I/O port line of the control chip 2. When YX1 is low, the optical coupler is conducted, and the output YX1_ FW of the optical coupler is low; when YX1 is high, the optocoupler is not conducting and the output YX1_ FW of the optocoupler is high.

As shown in fig. 10, the control output circuit includes a photocoupler Q14, a pin a of a photocoupler Q14 is connected to one end of a resistor R111, the other end of the resistor R111 is connected to 3.3V, a pin C of the photocoupler Q14 is connected to KZ24V, a pin E of the photocoupler Q14 is connected to one end of a resistor R103, the other end of the resistor R103 is connected to one end of a resistor R36 and a pole G of a fet V7, and the pole S of the fet and the other end of the resistor R36 are connected to 24 VGND. 3.3V connects the input positive pole of opto-coupler through the resistor, the I/O mouth HEIN of control chip 2 connects the input negative pole of opto-coupler, work power supply KZ24V is connected with the output C utmost point of opto-coupler, the output E utmost point of opto-coupler is connected with field effect transistor V7 'S G utmost point through resistance R103, field effect transistor V7' S G utmost point is connected with 24VGND of work power supply through resistance R36, field effect transistor V7 'S S utmost point is connected with 24VGND of work power supply, field effect transistor V7' S D utmost point is to outer output control. When the HEIN is low, the optocoupler Q14 is turned on, KZ24V outputs to the G pole of the fet V7, and the fet V7 is turned on to output. When the HEIN is high, the optocoupler Q14 is not turned on, the G pole of the field effect transistor V7 is connected to 24VGND through the resistor R36, and the field effect transistor V7 is turned off, and no output is provided.

As shown in fig. 11, the battery measuring and loading circuit includes a resistor R48, one end of the resistor R48 is connected to KEY +, the other end of the resistor R48 is connected to the positive electrode of the battery BT2, one end of the resistor R55, and the S pole of the fet V4, the negative electrode of the battery BT2 is connected to one end of the resistor R39, the E pin and 24VGND of the transistor Q20, the other end of the resistor R39 is connected to kzbat and the B pole of the transistor Q20, the C pole of the transistor Q20 is connected to one end of the resistor R54 and the C pole of the transistor Q54, the other end of the resistor R54 is connected to the other end of the resistor R54 and the G pole of the fet V54, the E pin of the transistor Q54 is connected to one end of the resistor R54 and the 24VGND, the B pin of the transistor Q54 is connected to the other end of the resistor R54 and one end of the resistor R54, the other end of the resistor R54 is connected to the KEY-, the D pole of the fet V54 is connected to the anode of the variable resistor W54, the cathode of the variable resistor ZB 54, the other end of the resistor R123 is connected with a pin A of a photoelectric coupler TF1 and a pin C of a photoelectric coupler TF2, a pin K of the photoelectric coupler TF1 is connected with an anode of a diode D32, a cathode of the diode D32 is connected with one end of a resistor R124, the other end of the resistor R124 is connected with a pin E and a pin 24VGND of the photoelectric coupler TF2, a pin C of the photoelectric coupler TF1 is connected with 3.3V, a pin E of the photoelectric coupler TF1 is connected with one end of a resistor R126 and one end of a resistor R98, the other end of the resistor R98 is connected with a pin A of the photoelectric coupler TF2 and one end of a resistor R100, and a pin K of the photoelectric coupler TF2 is connected with the other end of the resistor R100 and the VSS. The KEY + KEY-is connected with the loading KEY, when the KEY and the KEY-are closed after being pressed, positive electricity BT + of the battery BT2 enables Q23 and V4 to be conducted through R48R49, battery voltage is loaded to a working power supply ZB24V through V4 and D50, the core module 1 is electrified to work, and the control chip 2 of the core module 1 controls the KZBAST port line to output high level, so that Q20 is conducted, and V4 is kept to be conducted. After the key is released, the core module 1 works according to the set time, and after the time is up, the KZBAST port line output low levels Q20 and V4 are cut off, and the battery stops loading. After the battery is loaded, BT + is connected with one end of a potentiometer W1 through V4, the other 2 ends of the potentiometer W1 are connected with a resistor R123 after being short-circuited, the other end of the resistor R123 is connected with an input A pole of an optocoupler TF1 and an output C pole of the optocoupler TF2, an input K pole of the optocoupler TF1 is connected with an anode of a diode D32, a cathode of the diode D32 is connected with a resistor R124, and the other end of the resistor R124 is connected with an output E pole of the optocoupler TF2 and 24 VGND; an output C pole of the optocoupler TF1 is connected with 3.3V, an output E pole of the optocoupler TF1 is connected with the resistors R126 and R98, the other end V-BAT of the resistor R126 is connected with an AD channel of the control chip 2, the battery voltage is measured, and the W1 adjustment precision is achieved. The resistor R98 is connected with the resistor R100 and the input A pole of the optocoupler TF2, and the input K pole of the optocoupler TF2 is connected with VSS after being short-circuited with the other end of the resistor R100.

As shown in fig. 12, the battery charge control circuit includes a photocoupler Q25, a pin a of a photocoupler Q25 is connected to one end of a resistor R52, the other end of the resistor R52 is connected to 3.3V, a pin C of the photocoupler Q25 is connected to one end of a resistor R53, the other end of the resistor R53 is connected to one end of a resistor R38 and the pole G of a fet V5, the other end of a resistor R38 is connected to the pole S of the fet, the cathode of a diode D20 and the anode of a diode D45, the pole D of the fet V5 is connected to one end of a resistor R50, the other end of the resistor R50 is connected to the anode of a diode D46, the cathode of the diode D46 is connected to the anode of a battery BT2, and the pin E of the photocoupler Q25 is connected to the cathode of a

battery

2 and 24 vgbt. ZB2 is an external input power source connected with the anode of D20, the cathode of D20 is connected with the anode of D45, the S poles of R38 and V5, the cathode of D45 is connected with ZB24V to supply power to the core module 1, DCCDKZ is connected with the IO port line of the core module 1 and connected with the input K pin of an optocoupler Q25, the input A pin of Q25 is connected with R52, the other end of R52 is connected with 3.3V, the output C pole of Q25 is connected with R53, the other end of R53 is connected with the G poles of R38 and V5, the output D pole of V5 is connected with a resistor R50, a resistor R50 plays a current limiting role, the other end of the resistor R50 is connected with the anode of a diode D46, and the cathode of the diode D46 is connected with the anode BT + of a battery 2. The control chip 2 of the core module 1 controls DCCDKZ to be pulled down, the optocoupler Q25 and the triode V5 are conducted, and an external power supply charges the battery BT2 through D20, V5, R27 and D46. When the DCCDKZ is set high, the optocoupler Q25 and the triode V5 are cut off, and charging is stopped.

As shown in fig. 13, the wireless module includes a fet V3, a D terminal of a fet V3 is connected to G24V, an S terminal of a fet V3 is connected to one end of a resistor R93 and ZB24V, a G terminal of a fet V3 is connected to the other end of a resistor R93 and one end of a resistor R46, the other end of a resistor R46 is connected to a C terminal of a photocoupler Q21, an E terminal of a photocoupler Q21 is connected to 24VGND, an a terminal of a photocoupler Q21 is connected to one end of a resistor R92, the other end of a resistor R92 is connected to 3.3V, a K terminal of a photocoupler Q21 is connected to an anode of a diode D30, a cathode of a diode D30 is connected to KZ31, a cathode of the diode VGND is connected to

pins

1 and 4 of an interface GX1, and a 2 terminal of an interface GX1 is connected to G24V. The industrial wireless module adopts a Xiamen Quxin 2816-D module which is connected with a serial port of the control chip 2. KZ31 is connected with the IO port of the control chip 2, the power supply of the module is controlled, KZ31 is pulled down, and Q21 and V3 are conducted to supply power to the module.

As shown in fig. 14, the WIFI module adopts an ESP-07S module U7, pin 1 of U7 is connected to one end of a resistor R37, pin 3 of U7 is connected to one end of a resistor R40, pin 8 of U7 is connected to the other end of a resistor R37, the other end of a resistor R40, the anode of a capacitor C2, and the D-pole of a fet V2, the S-pole of a fet V2 is connected to 3.3V, one end of a resistor R35, the other end of the resistor R35 is connected to the G-pole of a fet V2, and the cathode of a capacitor C2 is connected to pin 15 of U7. The Wifi module adopts the ESP-07S module of Anxinke scientific and technological development, directly is connected with control chip 2 'S serial ports, and KZWIFI is connected with control chip 2' S IO mouth, and when it draws down, V2 switches on, supplies power for U7.

As shown in fig. 15, the GPS module employs ST-26_ U7L chip U8, pin 9 of U8 is connected to one end of reactor L3, pins 10 and 12 of U8 are connected to VSS, pin 11 of U8 is connected to the other end of reactor L3 and pin 1 of interface XS1, pins 2, 3 and 4 of interface XS1 are connected to VSS, pin 23 of U8 is connected to one end of capacitor C51, the positive electrode of capacitor C52 and the negative electrode of fet V11, pin 24 of U8 is connected to VSS, the other end of capacitor C51 and the negative electrode of capacitor C52, the S electrode of fet V11 is connected to 3.3V and one end of resistor R157, and the G electrode of fet V11 is connected to the other end of resistor R157. An XS1 socket connects to the GPS antenna. The GPS module adopts ST-26_ U7L and is directly connected with a serial port of the control chip 2, the USART3_ TX is pulled down, the V11 is conducted to supply power to the U8, and the USART3_ RX receives timing and latitude and longitude information.

The voltage stabilizing circuit adopts a DC/DC module produced by Jinshengyang company.

The intelligent control circuit of the circuit breaker is controlled by adopting a single chip, so that the structure of the whole control circuit is simplified, the number of main chips is reduced, and the whole power consumption is reduced; meanwhile, through a unique circuit structure design, the invention can control the peripheral power supply, thereby further reducing the power consumption of the control circuit.

Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. The utility model provides a circuit breaker intelligent control circuit which characterized in that: the device comprises a core module, a first conditioning circuit, a second conditioning circuit, a frequency sampling circuit, a clock circuit, a signal input circuit, a control output circuit, a communication circuit module and a power supply module, wherein the core module comprises a control chip, a metering chip, an AD chip, a storage chip and an encryption chip; the three-phase current IA, IB, IC and zero sequence current ILX are connected with an AD chip of the core module through a first conditioning circuit, the three-phase voltage UA, UB, UC and zero sequence voltage ULX are connected with the AD chip of the core module through a second conditioning circuit, and the three-phase voltage UA is connected with an I/O port line of a control chip of the core module through a frequency sampling circuit; the signal input circuit is connected with an I/O port line of a control chip of the core module; the control output circuit is connected with an I/O port line of a control chip of the core module; the AD chip is connected with the parallel data port of the control chip; the storage chip is connected with the SPI port of the control chip through a line; the input direct-current voltage generates stable voltage through the power supply module to supply power to each module; the three-phase currents IA, IB and IC are connected with a metering chip of the core module through a first conditioning circuit; the three-phase voltages UA, UB and UC are connected with a metering chip of the core module through a second conditioning circuit; the metering chip is connected with the SPI port of the control chip through a line, the encryption chip is connected with the SPI port of the control chip through a line, and the clock circuit is connected with 3I/O ports of the core module through lines.

2. The intelligent control circuit of the circuit breaker according to claim 1, characterized in that: the communication circuit module comprises a GPS module, a WIFI module, a work-specific wireless module, a man-machine contact module and a network communication module, the work-specific wireless module is connected with a serial port of the core module, the network communication module is connected with a serial port of the core module, the man-machine contact module is connected with an I/O port of the core module through a wire, the WIFI module is connected with the serial port of the core module, and the GPS module is connected with the serial port of the core module.

3. The intelligent control circuit of the circuit breaker according to claim 1, characterized in that: the power supply module comprises a battery charging control circuit, a battery measuring and loading circuit and a voltage stabilizing circuit, wherein an input direct-current voltage is respectively connected with the voltage stabilizing circuit, the battery measuring and loading circuit and the battery charging control circuit, the battery charging control circuit is connected with the battery, the battery is connected with the battery measuring and loading circuit, the battery measuring and loading circuit is connected with the core module, and the voltage stabilizing circuit generates a stable voltage to supply power to each module.

4. The intelligent control circuit of the circuit breaker according to claim 1, characterized in that: the control chip adopts an ARM microprocessor STM32F series chip U, the metering chip adopts an ATT7022 metering chip U, 1 pin of the U is connected with one end of a resistor R and one end of a capacitor C, the other end of the resistor R is connected with 3.3V, the other end of the capacitor C is connected with VSS, 2 pins of the U are connected with one end of a resistor R, the other end of the resistor R is connected with 3.3V, the 3 pins of the U are connected with one end of the resistor R and one end of a resistor R, the other end of the resistor R is connected with one end of the resistor R, the other end of the resistor R and the other end of the resistor R are connected with one end of the resistor R and VSS, 4 pins of the U are connected with the other end of the resistor R, 6 pins of the U are connected with one end of the resistor R and one end of the resistor R, the other end of the resistor R is connected with one end of the resistor R, the other end of the resistor R and the other end of the resistor R are connected with one end of the resistor R and VSS, the other end of the resistor R is connected with 7 pins of the U, a pin 9 of the U2 is connected with one end of a resistor R9 and one end of a resistor R10, the other end of the resistor R9 is connected with one end of a resistor R11, the other end of a resistor R11 is connected with one end of a resistor R12, the other end of the resistor R10 and the other end of a resistor R12 are connected with one end of a resistor R30 and VSS, the other end of the resistor R30 is connected with a pin 10 of the U2, a pin 11 of the U2 is connected with a pin 15 of the U2, a pin 13 of the U2 is connected with one end of a resistor R14 and one end of a resistor R15, the other end of the resistor R14 is connected with one end of a resistor R16, the other end of the resistor R16 is connected with one end of a resistor R17, the other end of the resistor R15 and the other end of the resistor R17 are connected with one end of the resistor R31 and VSS, the other end of the resistor R31 is connected with a pin 14 of the U31, a pin 16 of the resistor R31 and one end of the resistor R31, the other end of the resistor R31 is connected with one end of the resistor R3617, and the other end of the resistor R31 are connected with one end of the resistor R3617, the other end of the U is connected with one end of a resistor R and one end of the resistor R, the other end of the resistor R is connected with one end of the resistor R, the other end of the resistor R and the other end of the resistor R are connected with one end of the resistor R and VSS, the other end of the resistor R is connected with 20 pins of the U, 21 pins of the U are connected with one end of the resistor R, one end of the resistor R and one end of a capacitor C, the other end of the resistor R is connected with one end of the capacitor C and VSS, 22 pins of the U are connected with one end of the resistor R and one end of the resistor C, the other end of the resistor R is connected with the other end of the capacitor C and VSS, 23, 24, 32, 33 and 44 pins of the U are connected with VSS, one end of the capacitor C and one end of the capacitor C are connected with VSS, the other end of the capacitor C is connected with one end of the crystal oscillator tube X and the other end of the U42 pins; an AD chip adopts an 8-channel 16-bit AD7066 chip U3, pins 1, 48, 38 and 37 of U3 are connected with the anode of a capacitor C68, one end of a capacitor C59 and +5V, pins 2, 47, 41 and 40 of U3 are connected with the cathode of a capacitor C68, the other end of the capacitor C59 and VSS, pins 44 and 45 of U3 are connected with one end of a capacitor C63, the other end of the capacitor C63 is connected with one end of a capacitor C63, pins 46 and 43 of U63 and VSS, the other end of the capacitor C63 is connected with pin 42 of U63, pin 36 of U63 is connected with one end of a capacitor C63, pin 39 of U63 is connected with one end of a capacitor C63, the other end of U63 and the other end of the capacitor C63 are connected with VSS, pin 23 of U63 is connected with 3.3V, pin 26 of U63 is connected with pin 26, pins 8, 7, 6 and 34 of U63 are respectively connected with pins 1, 2, VSS of a resistor module R63, pin 3 and pin 3R 72 are connected with a capacitor module R72, pin 3 is connected with a resistor module R72, pin 3 and a resistor module R72, pins 3, 4 and 5 of U3 are connected with VSS; the encryption chip adopts a Beijing intelligent chip micro U4, wherein a pin 1 of U4 is connected with VSS, a pin 8 of U4 is connected with a D pole of a field effect tube V1 and one end of a capacitor C58, the other end of the capacitor C58 is connected with VSS, a G pole of the field effect tube V1 is connected with one end of a resistor R41, and the other end of the resistor R41 is connected with an S pole of a field effect tube V1 and 3.3V; the memory chip adopts a W25Q16 chip U5, the pins 3, 7 and 8 of U5 are connected with 3.3V, and the pin 4 of U5 is connected with VSS.

5. The intelligent control circuit of the circuit breaker according to claim 4, wherein: the first conditioning circuit and the second conditioning circuit respectively comprise 4 conditioning circuits, each conditioning circuit comprises an operational amplifier U9A, a pin 3 of U9A is connected with one end of a resistor R59, a pin 2 of U9A is connected with one end of a resistor R44, and the other end of a resistor R44 is connected with a pin 1 of U9A.

6. The intelligent control circuit of the circuit breaker according to claim 4, wherein: the frequency sampling circuit comprises an operational amplifier U10A, wherein a pin 2 of a U10A is connected with one end of a resistor R58, a pin 4 of the U10A is connected with-12 VCL, a pin 3 of the U10A is connected with one end of a resistor R97 and one end of a resistor R95, the other end of the resistor R97 is connected with VSS, a pin 8 of the U10A is connected with 12VCL, and the other end of the resistor R95 is connected with a pin 1 of the U10A and one end of a resistor R96.

7. The intelligent control circuit of the circuit breaker according to claim 4, wherein: the clock circuit adopts a DS1302 chip U6, wherein a pin 2 of U6 is connected with one end of a crystal oscillation tube Y1, a pin 3 of U6 is connected with the other end of a crystal oscillation tube Y1, a pin 4 of U6 is connected with VSS, a pin 8 of U6 is connected with the positive electrode of a battery BT1, and the negative electrode of the battery BT1 is connected with VSS.

8. The intelligent control circuit of the circuit breaker according to claim 4, wherein: the signal input circuit comprises a photoelectric coupler ISO7, a K pin of a photoelectric coupler ISO7 is connected with an I/O port of a control chip U1, a pin A of the photoelectric coupler ISO7 is connected with one end of a resistor R133, the other end of the resistor R133 is connected with 3.3V, a pin E of the photoelectric coupler ISO7 is connected with 24VGND, a pin C of the photoelectric coupler ISO7 is connected with one end of a resistor R122, the other end of the resistor R122 is connected with one end of a resistor R155 and a pole G of a field-effect tube V10, a pole S of the field-effect tube V10 and the other end of the resistor R155 are connected with ZB24V, a pole D of the field-effect tube V10 is connected with one end of a resistor R57, the other end of a resistor R57 is connected with a pin A of the photoelectric coupler ISO6, a pin E of the photoelectric coupler ISO6 is connected with VSS, a pin C of the photoelectric coupler ISO6 is connected with one end of the resistor R51, and the other end of the resistor R51 is connected with 3.3V; the control output circuit comprises a photoelectric coupler Q14, wherein a pin A of a photoelectric coupler Q14 is connected with one end of a resistor R111, the other end of the resistor R111 is connected with 3.3V, a pin C of the photoelectric coupler Q14 is connected with KZ24V, a pin E of the photoelectric coupler Q14 is connected with one end of a resistor R103, the other end of the resistor R103 is connected with one end of a resistor R36 and a pole G of a field effect transistor V7, and the pole S of the field effect transistor and the other end of the resistor R36 are connected with 24 VGND.

9. The intelligent control circuit of the circuit breaker according to claim 3, wherein: the battery measuring and loading circuit comprises a resistor R48, one end of the resistor R48 is connected with KEY +, the other end of the resistor R48 is connected with the anode of a battery BT2, one end of a resistor R55 and the S pole of a field effect transistor V4, the cathode of the battery BT2 is connected with one end of a resistor R39, the E pole and 24VGND of a transistor Q20, the other end of the resistor R39 is connected with KZBAST and the B pole of a transistor Q20, the C pole of a transistor Q20 is connected with one end of a resistor R54 and the C pole of a transistor Q54, the other end of the resistor R54 is connected with the other end of the resistor R54 and the G pole of the field effect transistor V54, the E pole of the transistor Q54 is connected with one end of the resistor R54 and one end of the VGND, the B pole of the transistor Q54 is connected with the other end of the resistor R54, the other end of the resistor R54 is connected with the D pole of the field effect transistor V54, the cathode of the diode D54 is connected with one end of the variable resistor D54 and the cathode of the variable resistor ZB 36123, the other end of the resistor R123 is connected with a pin A of a photoelectric coupler TF1 and a pin C of a photoelectric coupler TF2, a pin K of the photoelectric coupler TF1 is connected with the anode of a diode D32, the cathode of the diode D32 is connected with one end of a resistor R124, the other end of the resistor R124 is connected with a pin E and a pin 24VGND of a photoelectric coupler TF2, a pin C of a photoelectric coupler TF1 is connected with 3.3V, a pin E of the photoelectric coupler TF1 is connected with one end of a resistor R126 and one end of a resistor R98, the other end of the resistor R98 is connected with a pin A of the photoelectric coupler TF2 and one end of a resistor R100, and a pin K of the photoelectric coupler TF2 is connected with the other end of the resistor R100 and the VSS; the battery charging control circuit comprises a photocoupler Q25, a pin A of a photocoupler Q25 is connected with one end of a resistor R52, the other end of a resistor R52 is connected with 3.3V, a pin C of the photocoupler Q25 is connected with one end of a resistor R53, the other end of a resistor R53 is connected with one end of a resistor R38 and a pole G of a field-effect tube V5, the other end of a resistor R38 is connected with the pole S of the field-effect tube, the cathode of a diode D20 and the anode of a diode D45, the pole D of the field-effect tube V5 is connected with one end of a resistor R50, the other end of the resistor R50 is connected with the anode of a diode D46, the cathode of a diode D46 is connected with the anode of a battery BT2, and a pin E of the photocoupler Q25 is connected with the cathode of a battery BT2 and 24 VGND.

10. The intelligent control circuit of the circuit breaker according to claim 2, characterized in that: the wireless module for the special industry work comprises a field effect transistor V3, wherein the D pole of a field effect transistor V3 is connected with G24V, the S pole of the field effect transistor V3 is connected with one end of a resistor R93 and a ZB24V, the G pole of a field effect transistor V3 is connected with the other end of a resistor R93 and one end of a resistor R46, the other end of a resistor R46 is connected with the C pin of a photoelectric coupler Q21, the E pin of the photoelectric coupler Q21 is connected with 24VGND, the A pin of the photoelectric coupler Q21 is connected with one end of a resistor R92, the other end of the resistor R92 is connected with 3.3V, the K pin of the photoelectric coupler Q21 is connected with the anode of a diode D30, the cathode of the diode D30 is connected with KZ31, the 24VGND is connected with pins 1 and 4 of an interface GX1, and the 2 pin of an interface GX1 is connected with G24V; an ESP-07S module U7 is adopted as a WIFI module, a pin 1 of U7 is connected with one end of a resistor R37, a pin 3 of U7 is connected with one end of a resistor R40, a pin 8 of U7 is connected with the other end of a resistor R37, the other end of a resistor R40, the anode of a capacitor C2 and the D pole of a field-effect tube V2, the S pole of the field-effect tube V2 is connected with +3.3V and one end of a resistor R35, the other end of the resistor R35 is connected with the G pole of a field-effect tube V2, and the cathode of the capacitor C2 is connected with a pin 15 of U7 and VSS; the GPS module adopts an ST-26_ U7L chip U8, a pin 9 of U8 is connected with one end of a reactor L3, pins 10 and 12 of U8 are connected with VSS, a pin 11 of U8 is connected with the other end of a reactor L3 and a pin 1 of an interface XS1, pins 2, 3 and 4 of the interface XS1 are connected with VSS, a pin 23 of U8 is connected with one end of a capacitor C51, the anode of a capacitor C52 and the cathode of a field effect tube V11, a pin 24 of U8 is connected with VSS, the other end of the capacitor C51 and the cathode of a capacitor C52, the S pole of the field effect tube V11 is connected with 3.3V and one end of a resistor R157, and the G pole of the field effect tube V11 is connected with the other end of the resistor R157; the voltage stabilizing circuit adopts a DC/DC module.