CN114050808A

CN114050808A - Narrow pulse weak signal conditioning circuit

Info

Publication number: CN114050808A
Application number: CN202111261661.6A
Authority: CN
Inventors: 张美燕; 蔡文郁
Original assignee: Zhejiang University of Water Resources and Electric Power
Current assignee: Zhejiang University of Water Resources and Electric Power
Priority date: 2021-10-28
Filing date: 2021-10-28
Publication date: 2022-02-15

Abstract

The invention relates to a narrow-pulse weak-voltage signal conditioning circuit. The invention mainly comprises an interface unit, an adjustable resistor array unit, a pre-amplifier unit, a first-stage autocorrelation detection circuit unit, a voltage-controlled gain amplifier unit and a second-stage autocorrelation detection circuit unit. The original narrow-pulse weak voltage signal is input to the pre-stage amplifier unit and then output, and then is input to the first-stage autocorrelation detection circuit unit and then output, and then is input to the voltage-controlled gain amplifier unit and then output, and then is input to the second-stage autocorrelation detection circuit unit, and finally the conditioned signal is obtained. The invention can realize the anti-noise amplification of weak and small voltage signals, and is particularly suitable for narrow pulse weak signals with higher frequency. The gains of the pre-amplifier unit and the voltage-controlled gain amplifier unit can be controlled by a processor program, so that the output of a signal with a large dynamic range can be stabilized at a certain amplitude, and the integrity of the signal is improved.

Description

Narrow pulse weak signal conditioning circuit

Technical Field

The invention belongs to the technical field of weak current signal conditioning, and particularly relates to a narrow-pulse weak voltage signal conditioning circuit.

Background

The signal conditioning circuit has the function of converting weak small signals measured by the sensitive element into a standard signal circuit which can be identified and processed at the later stage in the circuit processing system, and the performance of the signal conditioning circuit at the front end directly influences the precision performance of the circuit processing system on the measurement of original signals. The signal conditioning technology relates to the technologies of amplification, filtering, compensation and the like, and can be widely applied to various circuit system scenes such as sensing detection and the like.

The general requirements of the signal conditioning circuit are as follows: (1) the signal amplification adjustable range is large, and various application scenes can be compatible; (2) the signal frequency range is large, and high-frequency and low-frequency signals can be compatible; (3) the signal gain is programmable and adjustable, and the amplification factor can be flexibly changed; (4) the effective suppression of self noise and background noise signals can be realized.

For more high frequency applications, there are more narrow pulse signals. The narrow-pulse weak signal is often characterized by narrow width, small amplitude and the like, and is easily interfered by external noise in an actual environment, the original signal can be attenuated and superimposed with noise, and meanwhile, the dynamic range of the signal intensity is large in different application scenes.

The existing narrow-pulse weak signal conditioning circuit generally adopts a single-stage or double-stage amplification mode, adopts a relatively fixed amplification factor, has insufficient signal response in time, and lacks consideration for noise suppression and the like. Therefore, the traditional preposed narrow pulse weak signal conditioning and amplifying circuit has the following defects:

(1) the magnification is not adjustable. The dynamic range of the narrow pulse weak signal is large, the pulse signal is seriously saturated and distorted when the amplitude is large due to overlarge gain, and the pulse signal is insufficiently amplified due to undersize gain, so that the processing performance of a post-stage circuit is influenced.

(2) Bandpass and bandstop filters, etc., are less robust to broadband white noise and may attenuate the desired signal. Digital methods such as the accumulation method require repeated measurement, so that the speed is low while the precision is improved, and the cost is high.

(3) The circuit speed is slow, and the narrow pulse signals with the same width of nanosecond level cannot be correctly processed, so that the signal detection capability of a post-stage circuit is influenced.

Disclosure of Invention

In order to solve the problems, the invention provides a novel narrow-pulse weak-voltage signal conditioning circuit based on a pre-stage amplifier unit, a first-stage autocorrelation detection circuit unit, a voltage-controlled gain amplifier unit and a second-stage autocorrelation detection circuit unit.

The narrow-pulse weak-voltage signal conditioning circuit mainly comprises an interface unit, an adjustable resistor array unit, a pre-amplifier unit, a primary autocorrelation detection circuit unit, a voltage-controlled gain amplifier unit and a secondary autocorrelation detection circuit unit. The original narrow-pulse weak voltage signal is input to a pre-stage amplifier unit and then output, then is input to a first-stage autocorrelation detection circuit unit and then output, and then is input to a voltage-controlled gain amplifier unit and then output, and then is input to a second-stage autocorrelation detection circuit unit, and finally a conditioned signal is obtained; the interface unit comprises a power interface, a signal interface, a first MCU gain adjusting interface and a second MCU gain adjusting interface; the power interface is connected with the power module through the connecting base and supplies power to the pre-amplifier unit, the first-stage autocorrelation detection circuit unit, the voltage-controlled gain amplifier unit and the second-stage autocorrelation detection circuit unit; the signal interface transmits signals for the upper level and the rear level of the system through the connecting row seat; the first MCU gain adjusting interface and the second MCU gain adjusting interface are connected with the single chip microcomputer MCU through the connecting row seat.

The adjustable resistor array unit comprises 4 MOSFET switches and resistors R23, R24, R25, R26, R27, R30, R31 and R32. The 1 st pins of the resistors R23, R24, R25, R26 and R27 are all connected to the 2 nd pin RES _ IN of the signal interface, and the 2 nd pin is respectively connected to the 2 nd pin of R30, the 1 st pin of the MOS switch Q1, the 1 st pin of the MOS switch Q2, the 1 st pin of the MOS switch Q3 and the 1 st pin of the MOS switch Q4. The 2 nd pins of the MOS switches Q1, Q2, Q3 and Q4 are respectively connected to the 1 st, 2 nd, 3 rd and 4 th pins of the first MCU gain adjustment interface, and the 3 rd pin is respectively connected to the 2 nd pin of R30, the 2 nd pin of R31, the 2 nd pin of R32 and the ground GND. The 1 st pin of the resistor R30 is connected to the 2 nd pin of the resistor R31, the 1 st pin of the resistor R31 is connected to the 2 nd pin of the resistor R32, and the 1 st pin of the resistor R32 is connected to the ground.

The preamplifier unit adopts an operational amplifier with the model of OPA842, resistors R1, R3 and R11 and filter capacitors C1, E1, C5, E4 and C3. The operational amplifier U1A has a forward power supply terminal (pin 7) connected to the VCC5V power supply pin of the power interface, a reverse power supply terminal (pin 4) connected to the VCC-5V power supply pin of the power interface, an inverting input terminal connected to the 2 nd pin RES _ IN of the SIGNAL interface and the 2 nd pin of the resistor R1, a non-inverting input terminal connected to the 1 st pin SIGNAL _ IN of the SIGNAL interface and the 2 nd pin of the resistor R11, and an output terminal connected to the 1 st pins of R1 and R3. Pin 1 of resistor R11 is connected to ground. The 1 st pin of the filter capacitor C3 is connected to the 2 nd pin of the R3 as the output SIGNAL _ V1 of the pre-amplifier unit, and the 2 nd pin is connected to the SIGNAL input terminal of the first-stage autocorrelation detecting circuit unit. The filter capacitors C1 and E1 are respectively connected between the positive power supply end and the ground wire of the operational amplifier, and the filter capacitors C5 and E4 are respectively connected between the negative power supply end and the ground wire of the operational amplifier.

The first-stage autocorrelation detection circuit unit mainly comprises a delay line chip and an analog multiplier chip. The delay line chip of the first-stage autocorrelation detection circuit unit adopts an ELMEC model, and the analog multipliers all adopt AD835 chips. The voltage reference terminal of the delay line chip K1 is connected to the ground, the input terminal thereof is connected to the 1 st pins of the SIGNAL output terminals SIGNAL _ V1 and R4 of the preamplifier unit, and the output terminal thereof is connected to the 1 st pin of the resistor R8. The forward power supply end of the analog multiplier U2 is connected with a VCC5V power supply pin of a power interface, the reverse power supply end is connected with a VCC-5V power supply pin of the power interface, the positive phase input end of a channel 1 is connected with a pin 2 of a resistor R4 and a resistor R5, the reverse phase input end of the channel 1 is connected with a pin 1 of the resistor R5 and a ground wire, the positive phase input end of the channel 2 is connected with a pin 2 of a resistor R8 and a resistor R12, the reverse phase input end of the channel 2 is connected with a pin 1 of the resistor R12 and a ground wire, the adjusting end is connected with a pin 1 of the resistor R14 and a pin 2 of the resistor R20, and the output end is connected with a pin 2 of the resistor R14 and the resistor R7. The 1 st pin of the R7 is connected to the 2 nd pin of the capacitor C6, which is also the SIGNAL output terminal SIGNAL _ V2 of the first stage autocorrelation detecting circuit unit, and is connected to the SIGNAL input terminal of the voltage controlled gain amplifier unit. The 1 st pin of the resistor R20 and the 1 st pin of the capacitor C6 are connected to ground. The filter capacitors C2 and E2 are respectively connected between the forward power supply end of the analog multiplier U2 and the ground wire, and the filter capacitors C8 and E5 are respectively connected between the reverse power supply end of the analog multiplier U2 and the ground wire.

The voltage-controlled gain amplifier unit mainly comprises a voltage-controlled gain amplifier and a digital-to-analog converter. The model of the voltage-controlled gain amplifier is VCA821, and the model of the digital-to-analog conversion chip is TLV 5636. The inverting input terminal of the voltage-controlled gain amplifier U4 is connected to the SIGNAL output terminal SIGNAL _ V2 of the first-stage autocorrelation detecting circuit unit and the 1 st pin of the resistor R16, the non-inverting input terminal is connected to the 1 st pin of the resistor R17, the voltage input terminal is connected to the 7 th pin voltage output terminal of the digital-to-analog converter U5, the gain resistor is provided with a forward terminal (the 4 th pin of U5), an inverting terminal (the 5 th pin of U5) and two terminals of the resistor R2, the feedback resistor input terminal (the 12 th pin of U5) is connected to the 1 st pin of the resistor R6, and the output terminal (the 10 th pin of U5) is connected to the 2 nd pin of the resistor R6 and the 1 st pin of the resistor R9. The 2 nd pin of the resistor R9 is the SIGNAL output terminal SIGNAL _ V3 of the voltage-controlled gain amplifier unit, and is also the SIGNAL input terminal of the two-stage autocorrelation detection circuit unit. The forward power supply end of the digital-to-analog converter U5 is connected with a 5V power supply pin of the power interface, the ground end is connected with a ground wire of the power interface, the SPI clock, the data, chip selection and frame synchronization ends are respectively connected with

pins

1, 2, 3 and 4 of the second MCU gain adjustment interface, and the analog reference voltage input/output end is connected to the ground wire through a capacitor C10. The filter capacitor C11 is connected between the positive supply terminal of the digital-to-analog converter U5 and the ground line.

The second-stage autocorrelation detection circuit unit comprises a delay line chip and an analog multiplier chip. The delay line chip adopts the model ELMEC, and the analog multiplier adopts the model AD835 chip. The voltage reference end of the delay line chip K2 is connected with the ground wire, the input end is connected with the signal output end of the voltage-controlled gain amplifier unit and the 1 st pin of the R10, and the output end is connected with the 1 st pin of the resistor R18. The forward power supply end of the analog multiplier U3 is connected with a VCC5V power supply pin of a power interface, the reverse power supply end is connected with a VCC-5V power supply pin of the power interface, the positive phase input end of a channel 1 is connected with a pin 2 of a resistor R10 and a resistor R13, the reverse phase input end of the channel 1 is connected with a pin 1 of the resistor R13 and a ground wire, the positive phase input end of the channel 2 is connected with a pin 2 of a resistor R18 and a resistor R19, the reverse phase input end of the channel 2 is connected with a pin 1 of the resistor R19 and a ground wire, the adjusting end is connected with a pin 1 of the resistor R21 and a pin 2 of the resistor R22, and the output end is connected with a pin 2 of the resistor R21 and the resistor R15. Pin 1 of R15 is connected to pin 2 of capacitor C7, and also conditioned SIGNAL output SIGNAL _ OUT is connected to pin 3 of the SIGNAL interface. The 1 st pin of the resistor R22 and the 1 st pin of the capacitor C7 are connected to ground. The filter capacitors C4 and E3 are respectively connected between the forward power supply end of the analog multiplier U3 and the ground wire, and the filter capacitors C9 and E6 are respectively connected between the reverse power supply end of the analog multiplier U3 and the ground wire.

The 1 st pin of the socket connector row seat P1 of the power interface is connected with the VCC5V output end of the power module, the 2 nd pin is connected with the VCC-5V output end of the power module, the 3 rd pin is connected with the VCC3V3 output end of the power module, and the 4 th pin is connected with the ground wire end of the power module. The 1 st pin of the socket connector row seat P4 of the signal interface is connected with the output end of a signal, the 2 nd pin of the row seat is connected with the output end of the adjustable resistor array, the 3 rd pin of the row seat is connected with the input end of the signal, and the 4 th pin of the row seat is connected with a ground wire end.

Pins

1, 2, 3 and 4 of the socket connector row seat P2 of the first MCU gain adjustment interface are respectively connected to the MOS switch interface of the MCU control circuit. And

pins

1, 2, 3 and 4 of the socket connector row seat P3 of the second MCU gain adjustment interface are respectively connected to the SPI communication interface of the MCU control circuit.

The main chip of the invention is selected as follows:

1. the pre-operational amplifier selects a broadband, low-distortion and low-noise OPA842 chip, and the gain-bandwidth product of the chip is 200 MHz.

2. The analog multiplier selects a four-quadrant high-speed AD835 chip with the bandwidth of 250 MHz.

3. The chip of the delay line core is an ELMEC 8510 chip with high-speed 8.5ns delay, and the bandwidth is 300 MHz.

4. The model of the voltage-controlled amplifier is a VCA821 chip with linearly adjustable broadband gain, and the slew rate is 2500V/us.

5. The digital-to-analog converter adopts a TLV5636 chip which outputs high-speed D/A by 12-bit voltage and is provided with an SPI serial interface.

The invention aims to provide a narrow pulse weak signal conditioning circuit with controllable gain, noise suppression and high-speed processing, which has the advantages that:

1. the invention can realize the anti-noise amplification of weak and small voltage signals, and is particularly suitable for narrow pulse weak signals with higher frequency.

2. The gains of the pre-amplifier unit and the voltage-controlled gain amplifier unit can be controlled by a processor program, so that the output of a signal with a large dynamic range can be stabilized at a certain amplitude, and the integrity of the signal is improved.

3. The invention sets two-stage autocorrelation filtering, the first stage autocorrelation filtering mainly removes the Gaussian white noise influence in the environment, the second stage autocorrelation filtering mainly removes the random noise introduced by the processing circuit, the suppression capability for the broadband white noise and other noise irrelevant to the original signal is stronger, and the final stage can output clean useful signals.

Drawings

FIG. 1 is a block diagram of the circuitry of the present invention;

FIG. 2 is a schematic diagram of an adjustable resistor array unit according to the present invention;

FIG. 3 is a schematic diagram of a preamplifier unit according to the invention;

FIG. 4 is a schematic diagram of a stage of autocorrelation detection circuitry in accordance with the present invention;

FIG. 5 is a schematic diagram of a voltage controlled gain amplifier unit according to the present invention;

FIG. 6 is a schematic diagram of a two-stage autocorrelation detection circuit unit in the present invention;

FIG. 7 is a wiring diagram of an interface unit according to the present invention;

fig. 8 is an example signal filtering result of the present invention.

Detailed Description

The invention is further described below with reference to the accompanying drawings.

As shown in fig. 1, a block diagram of a circuit system for conditioning a weak signal with narrow pulses in this embodiment includes an interface unit, an adjustable resistor array unit, a pre-stage amplifier unit, a first-stage autocorrelation detection circuit unit, a voltage-controlled gain amplifier unit, and a second-stage autocorrelation detection circuit unit; an original narrow-pulse weak-voltage SIGNAL _ IN signal is input into a pre-stage amplifier unit and then output SIGNAL _ V1, and then input into a first-stage autocorrelation detection circuit unit and then output SIGNAL _ V2, and then input into a voltage-controlled gain amplifier unit and then output SIGNAL _ V3, and then input into a second-stage autocorrelation detection circuit unit, and finally a conditioned signal SIGNAL _ OUT is obtained. The MCU interface unit is provided with an adjustable resistor array unit through an IO interface so as to control the gain of the preamplifier unit. The signal SIGNAL _ V1 after the pre-amplification is subjected to autocorrelation filtering through a primary autocorrelation detection circuit unit to obtain a signal SIGNAL _ V2, the SIGNAL _ V2 realizes the post-amplification through a voltage-controlled gain amplifier unit, and the amplification coefficient is controlled by the DAC output voltage of the digital-to-analog converter controlled by the MCU interface unit. The signal SIGNAL _ V3 output by the voltage-controlled gain amplifier unit is subjected to autocorrelation filtering by a secondary autocorrelation detection circuit unit to obtain an output signal SIGNAL _ OUT.

As shown in fig. 2, the adjustable resistor array unit includes 4 MOSFET-N switches Q1, Q2, Q3, Q4. The gain adjustment interface P2 connected with the MCU is connected with the grid G of the 4 NMOS tubes, when the IO level output of the MCU is 0, the corresponding MOS tube is conducted, when the IO level output is 1, the corresponding MOS tube is cut off, and the RES _ IN changes with reference to the load impedance of GND. 4 MOS switches, corresponding to the array, can output 16 resistance value changes. Assuming that the resistance values of the resistors are all 100 ohms, when Q3Q2Q1Q0 is 0000, the resistance value of RES _ IN to ground is 500; when Q3Q2Q1Q0 is 0001, RES _ IN has a resistance to ground of 400; when Q3Q2Q1Q0 is 0011, RES _ IN has a resistance to ground of 300; when Q3Q2Q1Q0 is 0111, RES _ IN has a resistance to ground of 200; when Q3Q2Q1Q0 is 1111, the RES _ IN ground resistance value is 100. By setting the G-level of the MOS tube, the RES _ IN impedance can be adjusted, so that the digital control variable gain function is realized IN a simple resistor array mode.

As shown IN fig. 3, the input SIGNAL of the preamplifier unit is SIGNAL _ IN, the output SIGNAL is SIGNAL _ V1, the preamplifier unit mainly includes a wideband low-distortion operational amplifier of type OPA842, the positive input terminal is connected to the original SIGNAL input, the negative input terminal is connected to the output terminal of the adjustable resistor array unit and the feedback resistor R1, the larger input resistor can obtain a complete SIGNAL from the previous stage, the smaller output resistor is convenient for the load to obtain a SIGNAL, the U1 chip is OPA842, the common mode rejection ratio under standard measurement can reach 95, and the common mode SIGNAL introduced by the IN-phase amplifier can be better rejected. The amplification factor of the operational amplifier U1 is set by the ground resistance and the feedback resistance R1500 omega of the output end RES _ IN of the adjustable resistance array unit, and the gain is regulated and controlled by the adjustable resistance array unit. When the ground-to-ground value of the output RES _ IN of the adjustable resistor array is 100, the amplification factor of the positive-phase amplifier is 6V/V, and when the ground-to-ground value of RES _ IN is 500, the amplification factor is 2V/V. The resistors R3 and R11 are impedance matching resistors, so that the phenomenon of signal reflection such as ringing, overshoot and the like caused by the fact that high-speed signals flow through devices with large abrupt impedance changes in the transmission process is prevented. Capacitors C1, C5, E1 and E4 are power supply filter capacitors, because low and high frequency noise exists in a power supply, the capacitors are connected between the power supply and the ground in series to smooth output voltage, a front stage selects a 4.7uF tantalum capacitor to reduce pulse and low frequency interference, and a rear stage selects a 0.1uF ceramic capacitor to reduce high frequency interference caused by instantaneous change of load current. The capacitor C3 is a DC blocking capacitor and removes the common mode voltage introduced by the non-inverting amplifier.

As shown in fig. 4, the input SIGNAL of the first stage autocorrelation detecting circuit unit is SIGNAL _ V1, the output SIGNAL is SIGNAL _ V2, and the first stage autocorrelation detecting circuit unit includes a delay line chip K1 and an analog multiplier chip U2. Delay line chips K1 and K2 of the first-stage and second-stage autocorrelation detection circuit units adopt ELMEC 8510 chips, and analog multiplier chips adopt AD835 chips. An analog multiplier in a first-stage analog autocorrelation circuit multiplies an input signal of a channel 1 by an input signal of a channel 2 which passes through an 8.5ns delay line core chip ELMEC, and then an integrator formed by an input resistor R7 and a capacitor C6 performs integration operation, so that autocorrelation processing on hardware is realized, and noise signals irrelevant to useful signals, such as broadband white noise and the like, are filtered. The resistor R7 and the capacitor C6 form an integration circuit, generally, the time constant of the integration circuit needs to be larger than or equal to 10 times of pulse width, for a 1 nanosecond pulse signal, the value of the resistor R7 is 50 ohms, and the value of the capacitor C6 is 27 picofarads, so that the time parameter requirement is met. Let x (t) be an actual signal, where x (t) is s (t) + n (t), s (t) and n (t) are respectively a useful signal and a random noise signal, x (t) is delayed by τ ns to obtain x (t- τ), the analog multiplier multiplies x (t) by x (t- τ) and performs an integration operation, and x (t) is subjected to autocorrelation processing to obtain x (t)

Wherein R is_s(τ) and R_n(τ) is the autocorrelation of s (t) and n (t), respectively, R_sn(τ) and R_ns(τ) is the cross-correlation between s (t) and n (t). Due to the fact thatIf the signal and the broadband random white noise are not correlated, R_sn(τ)＝R_ns(τ) ═ 0, and since n (t) is broadband white noise, when τ is far from the vicinity of τ ═ 0, R_n(τ) → 0, final R_x(τ)＝R_s(τ), noise is suppressed. The resistor R14 and the resistor R20 are divided and input into the adjusting end of the analog multiplier U2, and the scaling factor of the analog multiplier is set to be 1. The resistors R5 and R12 are impedance matching resistors, so that signal reflection phenomena such as ringing, overshoot and the like are avoided. The capacitors C2, C8, E2 and E5 are power supply filter capacitors for filtering power supply ripples.

As shown in fig. 5, the input SIGNAL of the voltage controlled gain amplifier unit is SIGNAL _ V2, the output SIGNAL is SIGNAL _ V3, and the voltage controlled gain amplifier unit includes a voltage controlled gain amplifier U4 and a digital-to-analog converter U5. The voltage controlled gain amplifier is model VCA821 and the digital to analog converter is model TLV 5636. The inverting input end (the 6 th pin) of the voltage-controlled gain amplifier U4 is connected with the output SIGNAL _ V2 of the first-stage autocorrelation detection circuit unit, the non-inverting input end (the 3 rd pin) is connected to the ground wire through a resistor R17, the voltage input end is connected with the DAC voltage output end of the digital-to-analog converter U5, and the positive end and the negative end of the gain resistor are respectively connected with the two ends of the resistor R2. The maximum gain of the voltage-controlled gain amplifier U4 is set by a resistor R2 and a feedback resistor R6, and the gain is regulated by the DAC output voltage. The resistor R2 is 100 omega, the resistor R6 is 5k omega, the maximum gain is 2 multiplied by R6/R2, namely 100V/V, the control voltage of the gain is 0-2V, and the gain is continuously controllable. The SPI clock, data, chip select, and frame sync terminals of the digital-to-analog converter U5 are connected to the SPI interface controlled by the MCU, i.e., the gain adjustment interface P3, respectively. The resistors R16 and R9 are impedance matching resistors, so that signal reflection phenomena such as ringing, overshoot and the like are avoided. The resistor R17 is a resistor matching the offset current of the voltage-controlled amplifier U4, and reduces the offset voltage difference between the positive phase end and the negative phase end. The capacitor C11 is a power supply filter capacitor for filtering power supply ripples. The two-stage program control amplification mode can ensure flexible gain and improve the signal amplification range.

As shown in fig. 6, the input SIGNAL of the two-stage autocorrelation detecting circuit unit is SIGNAL _ V3, the output SIGNAL is SIGNAL _ OUT, and the two-stage autocorrelation detecting circuit unit includes a delay line chip K2 and an analog multiplier chip U3. The analog multiplier in the second-stage analog autocorrelation circuit multiplies an input signal of a channel 1 and an input signal of a channel 2, which passes through an ELMEC of a 8.5ns delay line core chip, and then an integrator formed by an input resistor R15 and a capacitor C7 performs integration operation to realize autocorrelation processing on hardware and filter noise signals irrelevant to useful signals, wherein the first-stage autocorrelation filtering mainly removes Gaussian white noise influence in the environment, and the second-stage autocorrelation filtering mainly removes random noise introduced by the processing circuit. The resistor R21 and the resistor R22 are divided and input into the adjusting end of the analog multiplier U3, so that the scaling coefficient U of the analog multiplier is set to 1. The resistors R13 and R19 are impedance matching resistors, so that signal reflection phenomena such as ringing, overshoot and the like are avoided. The capacitors C4, C9, E3 and E6 are power supply filter capacitors for filtering power supply ripples.

As shown in FIG. 7, the interface unit includes connector row seats P1, P2, P3, P4. The 1 st pin of the power interface P1 is connected with the 5V output end of the power module, the 2 nd pin is connected with the-5V output end of the power module, the 3 rd pin is connected with the VCC3V3 output end of the power module, and the 4 th pin is connected with the ground wire end of the power module. The 1 st pin of the signal interface is connected with the output end of a signal, the 2 nd pin is connected with the output end of the adjustable resistor array, the 3 rd pin is connected with the input end of the signal, and the 4 th pin is connected with a ground wire end.

Pins

1, 2, 3 and 4 of the first MCU gain adjustment interface P2 are respectively connected to pins MOS switch interface MOS _ KEY0, MOS _ KEY1, MOS _ KEY2 and MOS _ KEY3 of the MCU control circuit.

Pins

1, 2, 3, 4 of the second MCU gain adjustment interface P3 are connected to SPI communication interfaces TLV5636_ SCLK, TLV5636_ DIN, TLV5636_ CS, TLV5636_ FS, respectively, of the MCU control circuit.

As shown in fig. 8, (a) in fig. 8 is the input original signal, and fig. 8(b) is the output signal waveform conditioned by the signal of the present invention, it can be found that the signal processed by the present circuit can realize the signal amplification and digital filtering with better performance.

The working process of the invention is as follows: the narrow pulse weak signal realizes pre-amplification through a pre-amplifier unit, and the pre-amplification gain is flexibly set by an adjustable resistor array unit controlled by an MCU. The signal output by the pre-amplifier unit is subjected to autocorrelation filtering by a first-stage autocorrelation detection circuit unit, so that background noise is suppressed. The signal output by the first-stage autocorrelation detection circuit unit is input to a voltage-controlled gain amplifier unit, and the gain of the voltage-controlled gain amplifier unit is set by a digital-to-analog converter DAC controlled by the MCU. The first stage of autocorrelation filtering is mainly used for removing the influence of white Gaussian noise in the environment, the second stage of autocorrelation filtering is mainly used for removing random noise introduced by the processing circuit, signals output by the voltage-controlled gain amplifier unit are input to the second stage of autocorrelation detection circuit unit for secondary autocorrelation filtering, background noise caused by the circuit is suppressed again, and finally, complete, amplified and clean narrow pulse signals are output.

Claims

1. The utility model provides a weak signal conditioning circuit of narrow pulse, includes interface unit, adjustable resistance array unit, preceding amplifier unit, one-level autocorrelation detection circuitry unit, voltage-controlled gain amplifier unit and second grade autocorrelation detection circuitry unit, its characterized in that:

the narrow pulse weak signal realizes pre-stage amplification through a pre-stage amplifier unit, the gain of the pre-stage amplifier is set by an adjustable resistor array unit controlled by a single-chip microcomputer MCU, and the signal output by the pre-stage amplifier unit is subjected to autocorrelation filtering through a first-stage autocorrelation detection circuit unit to suppress background noise;

the signal output by the first-stage autocorrelation detection circuit unit is input to a voltage-controlled gain amplifier unit, and the gain of the voltage-controlled gain amplifier is set by a digital-to-analog converter DAC controlled by a single-chip microcomputer MCU; and the signal output by the voltage-controlled gain amplifier unit is input to a secondary autocorrelation detection circuit unit for secondary autocorrelation filtering, the background noise caused by the circuit is suppressed again, and finally the conditioned narrow pulse signal is obtained.

2. The narrow-pulse weak-signal conditioning circuit according to claim 1, wherein:

the pre-amplifier unit adopts an operational amplifier with the model of OPA842, and comprises resistors R1, R3 and R11, and filter capacitors C1, E1, C5, E4 and C3; the positive power supply end of the operational amplifier U1A is connected with a 5V power supply pin of the power interface, the negative power supply end is connected with a-5V power supply pin of the power interface, the negative input end is connected with the output end of the adjustable resistor array and the 2 nd pin of the resistor R1, the positive input end is connected with the input end of a signal and the 2 nd pin of the resistor R11, and the output end is connected with the 1 st pins of the R1 and the R3; the 1 st pin of the resistor R11 is connected to the ground wire; the 1 st pin of the filter capacitor C3 is connected to the 2 nd pin of the R3 as the output SIGNAL SIGNAL _ V1 of the pre-amplifier unit, and the 2 nd pin is connected to the SIGNAL input end of the first-stage autocorrelation detection circuit unit; the filter capacitors C1 and E1 are respectively connected between the positive power supply end of the operational amplifier and the ground wire, and the filter capacitors C5 and E4 are respectively connected between the negative power supply end of the operational amplifier and the ground wire.

3. The narrow-pulse weak-signal conditioning circuit according to claim 2, characterized in that:

the first-stage autocorrelation detection circuit unit comprises a delay line chip and an analog multiplier chip; the voltage reference end of the delay line chip K1 is connected with the ground wire, the input end of the delay line chip K1 is connected with the SIGNAL output end SIGNAL _ V1 of the pre-amplifier unit and the 1 st pin of the resistor R4, and the output end of the delay line chip K1 is connected with the 1 st pin of the resistor R8; the positive power supply end of the analog multiplier chip U2 is connected with a VCC5V power supply pin of a power interface, the reverse power supply end is connected with a VCC-5V power supply pin of the power interface, the positive phase input end of the channel 1 is connected with a resistor R4 and a 2 nd pin of a resistor R5, and the reverse phase input end of the channel 1 is connected with a 1 st pin of the resistor R5 and a ground wire; the positive phase input end of the channel 2 is connected with the 2 nd pins of the resistor R8 and the resistor R12, the negative phase input end of the channel 2 is connected with the 1 st pin of the resistor R12 and the ground wire, the adjusting end is connected with the 1 st pin of the resistor R14 and the 2 nd pin of the resistor R20, and the output end is connected with the 2 nd pins of the resistor R14 and the resistor R7; the 1 st pin of the resistor R7 is connected to the 2 nd pin of the capacitor C6, which is also the SIGNAL output terminal SIGNAL _ V2 of the first-stage autocorrelation detecting circuit unit, and is connected to the SIGNAL input terminal of the voltage-controlled gain amplifier unit; the 1 st pin of the resistor R20 and the 1 st pin of the capacitor C6 are connected with the ground wire; the filter capacitors C2 and E2 are respectively connected between the forward power supply end of the analog multiplier U2 and the ground wire, and the filter capacitors C8 and E5 are respectively connected between the reverse power supply end of the analog multiplier U2 and the ground wire.

4. The narrow-pulse weak-signal conditioning circuit according to claim 3, wherein:

the voltage-controlled gain amplifier unit mainly comprises a voltage-controlled gain amplifier and a digital-to-analog converter; the inverting input end of the voltage-controlled gain amplifier U4A is connected with the signal output end of the first-stage autocorrelation detection circuit unit and the 1 st pin of the resistor R16, the non-inverting input end is connected with the 1 st pin of the resistor R17, the voltage input end is connected with the 7 th pin voltage output end of the digital-to-analog converter U5, the gain resistor is provided with a positive end and a negative end which are respectively connected with two ends of the resistor R2, the feedback resistor input end is connected with the 1 st pin of the resistor R6, and the output end is connected with the 2 nd pin of the resistor R6 and the 1 st pin of the resistor R9; the 2 nd pin of the resistor R9 is the SIGNAL output terminal SIGNAL _ V3 of the voltage-controlled gain amplifier unit, and is also the SIGNAL input terminal of the two-stage autocorrelation detection circuit unit.

5. The narrow-pulse weak-signal conditioning circuit according to claim 4, wherein:

the second-stage autocorrelation detection circuit unit comprises a delay line chip and an analog multiplier chip; the voltage reference end of the delay line chip P2 is connected with the ground wire, the input end is connected with the SIGNAL output end SIGNAL _ V3 of the voltage-controlled gain amplifier unit and the 1 st pin of the resistor R10, and the output end is connected with the 1 st pin of the resistor R18;

the positive power supply end of the analog multiplier chip U3 is connected with a VCC5V power supply pin of a power interface, the reverse power supply end is connected with a VCC-5V power supply pin of the power interface, the positive phase input end of the channel 1 is connected with a resistor R10 and a 2 nd pin of a resistor R13, and the reverse phase input end of the channel 1 is connected with a 1 st pin of the resistor R13 and a ground wire; the positive phase input end of the channel 2 is connected with the 2 nd pins of the resistor R18 and the resistor R19, the negative phase input end of the channel 2 is connected with the 1 st pin of the resistor R19 and the ground wire, the adjusting end is connected with the 1 st pin of the resistor R21 and the 2 nd pin of the resistor R22, and the output end is connected with the 2 nd pins of the resistor R21 and the resistor R15; a 1 st pin of the resistor R15 is connected to a 2 nd pin of the capacitor C7, and is also connected to a 3 rd pin of the SIGNAL interface through the conditioning SIGNAL output terminal SIGNAL _ OUT; the 1 st pin of the resistor R22 and the 1 st pin of the capacitor C7 are connected with the ground wire; the filter capacitors C4 and E3 are respectively connected between the positive power supply end of the analog multiplier chip U3 and the ground, and the filter capacitors C9 and E6 are respectively connected between the negative power supply end of the analog multiplier U3 and the ground.

6. The narrow-pulse weak-signal conditioning circuit according to claim 5, wherein:

the adjustable resistor array unit comprises 4 MOSFET switches and resistors R23, R24, R25, R26, R27, R30, R31 and R32; the 1 st pin of the resistors R23, R24, R25, R26 and R27 is used as an output end RES _ IN of the adjustable resistor array, and the 2 nd pin is respectively connected to the 2 nd pin of R30, the 1 st pin of the MOS switch Q1, the 1 st pin of the MOS switch Q2, the 1 st pin of the MOS switch Q3 and the 1 st pin of the MOS switch Q4; the 2 nd pins of MOS switches Q1, Q2, Q3 and Q4 are respectively connected to an MOS switch interface controlled by the MCU of the single chip microcomputer, and the 3 rd pin is respectively connected to the 2 nd pin of R30, the 2 nd pin of R31, the 2 nd pin of R32 and the ground wire GND; the 1 st pin of the resistor R30 is connected to the 2 nd pin of the resistor R31, the 1 st pin of the resistor R31 is connected to the 2 nd pin of the resistor R32, and the 1 st pin of the resistor R32 is connected to the ground.