CN114050713A - Bootstrap circuit in high-voltage integrated circuit and charging method - Google Patents

Abstract

The application discloses a bootstrap circuit and a charging method in a high-voltage integrated circuit, and belongs to the technical field of integrated circuits. A power supply port of a preceding stage circuit in the bootstrap circuit is connected with a power supply VCC, at least one control port is connected with a control signal output port, a first output port is connected with a source electrode of a first NMOS tube, and a second output port is connected with an input port of a first booster circuit; the output port of the first booster circuit is connected with the grid electrode, the substrate is connected to a power supply VCC through a resistor, and the drain electrode serving as the output port of the bootstrap circuit is connected with the high-side circuit; the front-stage circuit comprises a medium-voltage device or a low-voltage device; when the second output port outputs a high level, the first voltage booster circuit turns on the first NMOS tube to charge the high-side circuit; when the second output port outputs a low level, the first voltage boosting circuit turns off the first NMOS transistor to stop charging the high-side circuit. The circuit has the advantages of large charging current, high reliability and small quiescent current.

Description

Bootstrap circuit in high-voltage integrated circuit and charging method

Technical Field

The embodiment of the application relates to the technical field of integrated circuits, in particular to a bootstrap circuit and a charging method in a high-voltage integrated circuit.

Background

A typical HVIC (High Voltage Integrated Circuit) and peripheral Circuit structure is shown in fig. 1, and the output (VS) is generally connected to an inductive load, which can be used as a motor drive. In this configuration, a high voltage bootstrap Diode (DBS) external to the HVIC is used to charge the high side circuit floating power supply (VB-VS), and a bootstrap Capacitor (CBS) acts as a battery to power the high side circuit, especially after the VS voltage is boosted.

In order to reduce the volume of a PCB (Printed Circuit Board), a high voltage bootstrap Diode (DBS) may be integrated into the HVIC, which is difficult to integrate due to the oversized bootstrap Capacitors (CBS) and power devices (M1, M2), as shown in fig. 2. Currently, there are several implementations of integrating a high voltage bootstrap diode in an HVIC. The simplest approach is to integrate a true high voltage diode into the HVIC, but this approach can result in a significant increase in the overall chip area of the HVIC, thereby increasing chip cost.

A bootstrap circuit is proposed in the prior art, which specifically includes: the medium-voltage diode is connected with the high-voltage JFET in series to realize the function of the high-voltage bootstrap diode, so that the function of the bootstrap circuit can be realized by using a small number of devices. However, the structure has the problem of weak charging current, and meanwhile, the JFET pinch-off voltage, the medium-voltage diode breakdown voltage and the JFET conduction current have contradiction relations, so that the reliability of the structure is influenced.

Disclosure of Invention

The embodiment of the application provides a bootstrap circuit and a charging method in a high-voltage integrated circuit, which are used for solving the problems of weak charging current and unstable structure of the existing bootstrap circuit. The technical scheme is as follows:

in one aspect, a bootstrap circuit in a high voltage integrated circuit is provided, the bootstrap circuit including: the device comprises a preceding stage circuit, a first booster circuit, a first NMOS (N-channel metal oxide semiconductor) tube and a resistor;

a power supply port of the preceding stage circuit is connected with a power supply VCC, at least one control port of the preceding stage circuit is connected with a control signal output port, a first output port of the preceding stage circuit is connected with a source electrode of the first NMOS tube, a second output port of the preceding stage circuit is connected with an input port of the first booster circuit, an output port of the first booster circuit is connected with a grid electrode of the first NMOS tube, a substrate of the first NMOS tube is connected to the power supply VCC through the resistor, and a drain electrode of the first NMOS tube is used as an output port of the bootstrap circuit and is connected with a high-side circuit; the front-stage circuit comprises a medium-voltage device or a low-voltage device;

when the second output port of the preceding stage circuit outputs a high level, the first voltage boosting circuit turns on the first NMOS tube under the control of the high level so as to charge the high-side circuit; when the second output port of the preceding stage circuit outputs a low level, the first voltage boosting circuit turns off the first NMOS tube under the control of the low level so as to stop charging the high-side circuit.

In one possible implementation, the front-stage circuit includes: the circuit comprises a first diode, a clamping protection circuit and a buffer;

the positive end of the first diode is a power supply port of the front-stage circuit, the negative end of the first diode is connected with the clamping protection circuit, and the negative end of the first diode is a first output port of the front-stage circuit;

the input port of the buffer is a control port of the preceding stage circuit, and the output port of the buffer is a second output port of the preceding stage circuit.

In one possible implementation, the front-stage circuit includes: the circuit comprises a clamping protection circuit, a second booster circuit, an input logic circuit and a second NMOS tube;

a first input port of the input logic circuit is a first control port of the preceding stage circuit, a second input port of the input logic circuit is a second control port of the preceding stage circuit, a first output port of the input logic circuit is connected with an input port of the second booster circuit, and a second output port of the input logic circuit is a second output port of the preceding stage circuit;

the output port of the second booster circuit is connected with the grid electrode of the second NMOS tube, the source electrode of the second NMOS tube is in short circuit with the substrate and then serves as the power supply port of the preceding stage circuit, and the drain electrode of the second NMOS tube is connected with the clamping protection circuit and then serves as the first output port of the preceding stage circuit.

In one possible implementation manner, when the input of the first input port of the input logic circuit is high level, the output of the first output port and the second output port of the input logic circuit is low level;

when the first input port of the input logic circuit inputs a low level and the second input port inputs a high level, the first output port and the second output port of the input logic circuit output a high level;

when the first input port of the input logic circuit inputs a low level and the second input port inputs a low level, the first output port of the input logic circuit outputs a low level and the second output port outputs a high level.

In one possible implementation, the front-stage circuit includes: the input and feedback logic circuit, the second booster circuit, the clamping and voltage detection circuit and the second NMOS tube;

the input port of the input and feedback logic circuit is the control port of the preceding stage circuit, the first output port of the input and feedback logic circuit is connected with the input port of the second booster circuit, the second output port of the input and feedback logic circuit is the second output port of the preceding stage circuit, and the feedback control port of the input and feedback logic circuit is connected with the output port of the clamping and voltage detecting circuit;

the output port of the second booster circuit is connected with the grid electrode of the second NMOS tube, the source electrode of the second NMOS tube is in short circuit with the substrate and then serves as the power supply port of the preceding stage circuit, and the drain electrode of the second NMOS tube is connected with the input end of the clamping and voltage detecting circuit and then serves as the first output port of the preceding stage circuit.

In one possible implementation, when the input of the input port of the input and feedback logic circuit is a high level, the output of the first output port and the second output port of the input and feedback logic circuit is a low level;

when the input of the input port of the input and feedback logic circuit is low level, the output of the second output port of the input and feedback logic circuit is high level;

when the input of the input port of the input and feedback logic circuit is low level and the input of the feedback control port of the input and feedback logic circuit is high level, the output of the first output port of the input and feedback logic circuit is high level.

In one possible implementation, the first boost circuit includes: the circuit comprises a delay circuit, a logic circuit, an oscillator, a counter, a power failure detection circuit, a clamping and overvoltage detection circuit, a first capacitor, a second diode, a third diode, a fourth diode, a first switch and a second switch;

the input port of the delay circuit is connected with the first set input port of the logic circuit and then is the input port of the first booster circuit, the output port of the delay circuit is connected with one end of the first capacitor, and the other end of the first capacitor is connected with the cathode of the second diode, the cathode of the fourth diode, one end of the second switch, the input port of the clamping and overvoltage detection circuit and the input port of the power failure detection circuit respectively and then is used as the output port of the first booster circuit;

a second set input port of the logic circuit is respectively connected with an output end of the power failure detection circuit and a zero clearing input end of the counter, a first reset input port of the logic circuit is connected with an output end of the counter, a second reset input port of the logic circuit is connected with an output port of the clamping and overvoltage detection circuit, and an output port of the logic circuit is connected with an enable input port of the oscillator; the output port of the oscillator is respectively connected with the pulse input port of the counter and one end of the second capacitor, and the other end of the second capacitor is respectively connected with the cathode of the third diode and the anode of the fourth diode;

one end of the first switch is connected with the power supply VCC, and the other end of the first switch is connected with the anode of the second diode and the anode of the third diode respectively.

In a possible implementation manner, when the input port of the first voltage boost circuit inputs a high level, after a predetermined period of time, the output port of the first voltage boost circuit outputs a voltage value higher than the power supply voltage value of the power supply VCC and smaller than 2 times the power supply voltage value;

when the input end of the first booster circuit inputs a low level, the output end of the first booster circuit outputs a low level.

In a possible implementation manner, the substrate in the first NMOS transistor is connected to the power source VCC through the resistor; or the substrate in the first NMOS tube is connected to the source electrode through the resistor; or, the substrate in the first NMOS tube is grounded.

In another aspect, there is provided a charging method for use in the bootstrap circuit as described above, the method comprising:

when the second output port of the preceding stage circuit outputs a high level, the first voltage boosting circuit turns on the first NMOS tube under the control of the high level so as to charge the high-side circuit;

when the second output port of the preceding stage circuit outputs a low level, the first voltage boosting circuit turns off the first NMOS tube under the control of the low level so as to stop charging the high-side circuit.

The technical scheme provided by the embodiment of the application has the beneficial effects that at least:

1. because the first diode or the second NMOS tube in the preceding stage circuit is a medium-voltage device or a low-voltage device, the influence on the charging current is small, and the first NMOS tube can obtain the maximum area utilization rate; in addition, a unique back gate (substrate) control circuit in the first NMOS transistor can greatly improve the charging current.

2. The clamping protection circuit can effectively protect medium-voltage devices or low-voltage devices and improve the reliability of the circuit;

3. because no extra analog circuit module is arranged, the oscillator is in a static state under the static state for a long time, redundant current can not be consumed, and in addition, the current leakage is also greatly limited by the resistor, so that the static current is smaller.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic circuit diagram of a conventional HVIC external bootstrap diode;

FIG. 2 is a schematic circuit diagram of a conventional HVIC integrated bootstrap diode;

FIG. 3 is a diagram illustrating an exemplary bootstrap circuit configuration;

FIG. 4 is a diagram showing a first structure of a front-end stage in a bootstrap circuit;

FIG. 5 is a diagram of a second architecture of a preceding stage in the bootstrap circuit;

FIG. 6 is a diagram showing a third configuration of a preceding stage in the bootstrap circuit;

FIG. 7 is a schematic diagram of a first boost circuit in a bootstrap circuit;

FIG. 8 is a schematic diagram of a first NMOS transistor in a bootstrap circuit;

FIG. 9 is a schematic diagram of three connection modes of the substrate in the first NMOS transistor;

FIG. 10 is a waveform diagram illustrating the operation of the first boost circuit;

FIG. 11 is a waveform diagram illustrating operation of the first boost circuit in response to an overvoltage;

FIG. 12 is a waveform diagram showing the operation of a bootstrap circuit constituted by a first preceding stage circuit;

FIG. 13 is a waveform diagram showing the operation of a bootstrap circuit constituted by a second prior-stage circuit;

FIG. 14 is a waveform diagram showing the operation of a bootstrap circuit constituted by a third previous-stage circuit;

fig. 15 is a schematic flow chart of charging by using a bootstrap circuit.

Detailed Description

To make the objects, technical solutions and advantages of the embodiments of the present application more clear, the embodiments of the present application will be further described in detail with reference to the accompanying drawings.

Referring to fig. 3, a schematic diagram of a bootstrap circuit in a high-voltage integrated circuit according to an embodiment of the present application is shown. The bootstrap circuit may include: the preceding stage circuit 100, the first booster circuit 200, the first NMOS transistor 300, and the resistor 400, and the connection relationship between these two circuits and two devices will be described below.

The power port of the front-stage circuit 100 is connected to a power VCC, and at least one control port of the front-stage circuit 100 is connected to a control signal output port for outputting a control signal to a corresponding control port. It should be noted that different configurations of front-stage circuit 100 may have different numbers of control ports, as described in detail below.

A first output port of the preceding stage circuit 100 is connected with a source electrode of the first NMOS transistor 300, a second output port of the preceding stage circuit 100 is connected with an input port of the first booster circuit 200, an output port of the first booster circuit 200 is connected with a gate electrode of the first NMOS transistor 300, a substrate of the first NMOS transistor 300 is connected to a power supply VCC through a resistor 400, and a drain electrode of the first NMOS transistor 300 serving as an output port of a bootstrap circuit is connected to a high-side circuit (VB); the front-stage circuit 100 includes a medium-voltage device or a low-voltage device.

In this embodiment, when the second output port of the front-stage circuit 100 outputs a high level, the first voltage boost circuit 200 turns on the first NMOS transistor 300 under the control of the high level to charge the high-side circuit (VB); when the second output port of the front-stage circuit 100 outputs a low level, the first voltage boosting circuit 200 turns off the first NMOS transistor 300 under the control of the low level to stop charging the high-side circuit (VB).

The front-stage circuit 100 has three circuit configurations, which will be described below.

1. As shown in fig. 4, the front-stage circuit 100 may include: a first diode 101, a clamp protection circuit 102, and a buffer 103. The positive end of the first diode 101 is a power supply port of the front-stage circuit 100, the negative end of the first diode 101 is connected with the clamping protection circuit 102, and the negative end of the first diode 101 is a first output port of the front-stage circuit 100; an input port of buffer 103 is a control port of pre-stage circuit 100, and an output port of the buffer is a second output port of pre-stage circuit 100.

Note that the first diode 101 in the front-stage circuit 100 is a medium-voltage device or a low-voltage device.

2. As shown in fig. 5, the front-stage circuit 100 may include: the circuit comprises a clamp protection circuit 102, a second booster circuit 104, an input logic circuit 105 and a second NMOS transistor 106. The preceding stage circuit 100 has two control ports, a first input port of the input logic circuit 105 is a first control port of the preceding stage circuit 100, a second input port of the input logic circuit 105 is a second control port of the preceding stage circuit 100, a first output port of the input logic circuit 105 is connected to an input port of the second boost circuit 104, and a second output port of the input logic circuit 105 is a second output port of the preceding stage circuit 100; an output port of the second boost circuit 104 is connected to a gate of the second NMOS transistor 106, a source of the second NMOS transistor 106 is shorted to a substrate to form a power supply port of the front-stage circuit 100, and a drain of the second NMOS transistor 106 is connected to the clamp protection circuit 102 to form a first output port of the front-stage circuit 100.

3. As shown in fig. 6, the front-stage circuit 100 may include: an input and feedback logic circuit 107, a second boost circuit 104, a clamping and voltage detection circuit 108 and a second NMOS transistor 106. Wherein, the input port of the input and feedback logic circuit 107 is the control port of the preceding stage circuit 100, the first output port of the input and feedback logic circuit 107 is connected to the input port of the second boost circuit 104, the second output port of the input and feedback logic circuit 107 is the second output port of the preceding stage circuit 100, and the feedback control port of the input and feedback logic circuit 107 is connected to the output port of the clamp and voltage detection circuit 108; an output port of the second boost circuit 104 is connected to a gate of the second NMOS transistor 106, a source of the second NMOS transistor 106 is shorted to a substrate to form a power port of the front-stage circuit 100, and a drain of the second NMOS transistor 106 is connected to an input terminal of the clamp and voltage detection circuit 108 to form a first output port of the front-stage circuit 100.

It should be noted that the second NMOS transistor 106 in the preceding stage circuit 100 is a medium voltage device or a low voltage device.

The circuit configuration of the first booster circuit 200 will be explained below. As shown in fig. 7, the first boost circuit 200 may include: delay circuit 201, logic circuit 202, oscillator 203, counter 204, power down detection circuit 205, clamping and overvoltage detection circuit 206, first capacitor 207, second capacitor 208, second diode 209, third diode 210, fourth diode 211, first switch 212, and second switch 213. An input port of the delay circuit 201 is connected with a first set input port of the logic circuit 202 and then is an input port of the first booster circuit 200, an output port of the delay circuit 201 is connected with one end of the first capacitor 207, and the other end of the first capacitor 207 is connected with a cathode of the second diode 209, a cathode of the fourth diode 211, one end of the second switch 213, an input port of the clamp and overvoltage detection circuit 206 and an input port of the power failure detection circuit 205 respectively and then is used as an output port of the first booster circuit 200; a second set input port of the logic circuit 202 is connected with an output end of the power failure detection circuit 205 and a clear input end of the counter 204 respectively, a first reset input port of the logic circuit 202 is connected with an output end of the counter 204, a second reset input port of the logic circuit 202 is connected with an output port of the clamping and overvoltage detection circuit 206, and an output port of the logic circuit 202 is connected with an enable input port of the oscillator 203; an output port of the oscillator 203 is respectively connected with a pulse input port of the counter 204 and one end of a second capacitor 208, and the other end of the second capacitor 208 is respectively connected with a cathode of a third diode 210 and an anode of a fourth diode 211; the first switch 212 has one terminal connected to the power source VCC and the other terminal connected to the anode of the second diode 209 and the anode of the third diode 210, respectively.

The structure of the first NMOS transistor 300 will be explained below. As shown in fig. 8, the parasitic transistor of the first NMOS transistor 300 includes an NPN transistor QN and a PNP transistor QP, and the substrate may be grounded to prevent the QN and the QP from being turned on, but the substrate bias effect greatly reduces the on-state current, so that the substrate may be connected to the power VCC or the source through the resistor 400 to prevent the leakage current while increasing the on-state current. That is, the substrate in the first NMOS transistor 300 is connected to the power source VCC through the resistor 400; alternatively, the substrate in the first NMOS transistor 300 is connected to the source through the resistor 400; alternatively, the substrate in the first NMOS transistor 300 is grounded, and these three connection modes are shown in fig. 9.

The operation principle of the first booster circuit 200 will be explained below. In summary, when the input port of the first voltage boosting circuit 200 inputs a high level, after a predetermined period of time, the output port of the first voltage boosting circuit 200 outputs a voltage value higher than the power supply voltage value of the power supply VCC and smaller than 2 times the power supply voltage value; when the input port of the first voltage boosting circuit 200 inputs a low level, the output port of the first voltage boosting circuit 200 outputs a low level. That is, when the input of the first boost circuit 200 is at a high level, the first boost circuit starts to operate, and after a certain period of time, outputs a certain voltage higher than VCC but less than 2 times VCC; when the input is low, the output immediately goes low.

Specifically, when the Input (IN) is at a high level, the first switch 212 is turned on, the second switch 213 is turned off, the power source VCC charges Vbst through the first switch 212 and the second diode 209, Vbst can quickly reach a voltage close to VCC (VCC-VDIO, VDIO represents a diode drop), and then the output of the delay circuit 201 changes from a low level to a high level. Because the voltage at the two ends of the capacitor is not mutable, the Vbst voltage can increase VCC, and in practice, because of the existence of the gate capacitor of the first NMOS transistor 300, and meanwhile, in order to not increase the layout area too much, the area of the first capacitor 207 cannot be too large, and therefore, the value of the Vbst voltage increase is far smaller than VCC. For this reason, Vbst is continuously charged to the desired value (2 VCC-2 VDIO, VDIO representing the diode drop) by means of the control of oscillator 203. IN order to reduce the quiescent current when the Input (IN) is at a high level, the counter 204 counts the pulses output from the oscillator 203, and when the count reaches N, the control logic circuit 202 turns off the oscillator 203, and the value of N needs to be set to ensure that Vbst can be charged to the desired voltage (2 × VCC-2 × VDIO), where N is typically several tens. Meanwhile, in order to protect the gate of the first NMOS transistor 300 and other medium voltage devices or low voltage devices, a clamping and overvoltage detection circuit 206 is provided, whose clamping voltage (Vclmp) is less than the breakdown voltage of the medium voltage devices or low voltage devices, but greater than the highest operating voltage of the power supply VCC. In this way, the clamping and overvoltage detection circuit 206 can perform overvoltage detection on the input voltage, and when the input voltage exceeds the clamping voltage (Vclmp), a high level is output to control the logic circuit 202 to turn off the oscillator 203. In addition to the normal leakage current of the device, the Vbst port has no current to the ground, so that the Vbst voltage can be maintained to be constant for a long time, but the Vbst voltage also drops when the time is too long, especially the operation is performed at a high temperature, so that a power down detection circuit 205 is added, and when the power down detection circuit 205 detects that the Vbst voltage drops to a power down threshold (VCC + VT 1), a high level is output to control the logic circuit 202 to turn on the oscillator 203, and meanwhile, the counter 204 is cleared to start a new round of charging operation. When the Input (IN) is low, the first switch 212 is turned off, the second switch 213 is turned on, and the charging operation is stopped.

The logic circuit 202 may control the operating state of the oscillator 203. Specifically, when there is a rising edge at the first set input port or the second set input port of the logic circuit 202, the output is at a high level, so that the input at the enable input port of the oscillator 203 is at a high level, thereby controlling the oscillator 203 to start operating. When the first set input port is at a low level or the first reset input port is at a rising edge or the second reset input port is at a rising edge, the output is at a low level, so that the input of the enable input port of the oscillator 203 is at a low level, and the oscillator 203 is controlled to stop working.

The pulse input port of the counter 204 counts the pulses output by the oscillator 203, stops counting when the count value is N, and outputs a high level to control the logic circuit 202 to turn off the oscillator 203; when the input to the clear input port is a rising edge, the counter 204 performs a clear operation.

When the input is changed to a high level, the oscillator 203 starts to work, and if the output voltage does not exceed the clamp voltage (Vclmp), the oscillator 203 stops working after working for N cycles; if the output voltage during the operation of the oscillator 203 exceeds the clamp voltage (Vclmp), the oscillator 203 immediately stops operating; after a long time, when the output voltage drops to the power-down threshold (VCC + VT 1), the counter 204 is cleared and the oscillator 203 is started, and so on. The operation waveforms of the first boost circuit 200 are shown in fig. 10 and 11, where fig. 10 shows a waveform when the output voltage does not exceed the clamp voltage, and fig. 11 shows a waveform when the output voltage reaches the clamp voltage.

The operation principle of the three kinds of front-stage circuits 100 will be explained below.

1. Let the control signal of the first previous stage circuit 100 be HIN, which represents the high-side input signal of the High Voltage Integrated Circuit (HVIC), and when HIN is high, the output of the HVIC is high. As shown in fig. 12, when HIN is at a high level, the output Vbst of the first boost circuit 200 becomes a high level, that is, the gate of the first NMOS transistor 300 becomes a high level; when HIN goes low, Vbst immediately drops to low.

2. Let the two control signals of second type of pre-stage circuit 100 be HIN and LIN, respectively, which are the high-side and low-side input signals of the HVIC circuit, in-phase relationship with the outputs HO and LO, respectively. As shown in fig. 13. When HIN is low and LIN is low, the first output port VO1 of the input logic circuit 105 outputs low, the second output port VO2 outputs high, the gate voltage Vbst1 of the first NMOS transistor 300 is high, and the gate voltage Vbst2 of the second NMOS transistor 106 is low; when the HIN is high, VO1 and VO2 output low, and Vbst1 and Vbst2 output low; when HIN is low and LIN is high, VO1 and VO2 output high, Vbst1 and Vbst2 are high.

3. Let the control signal of the third pre-stage circuit 100 be HIN and the output of the clamp and voltage detection circuit 108 be SEN. As shown in fig. 14, when HIN is high level, the first output port and the second output port of the input and feedback logic circuit 107 output low level, and the output Vbst1 of the first boost circuit 200 and the output Vbst2 of the second boost circuit 104 are both low level; when HIN is low, the output of the second output port of the input and feedback logic circuit 107 is high, and Vbst1 is high; when HIN is low and SEN is high, the first output port of the input and feedback logic circuit 107 outputs high, and Vbst2 is high. When the source voltage VD of the first NMOS transistor 300 is less than the voltage (VCC-VT 2), it means that the high side voltage VB is less than VCC and SEN becomes high. The clamping and voltage detecting circuit 108 is configured to clamp and protect an input voltage, and output a high level when the input voltage is smaller than a charging threshold.

Referring to fig. 15, a flowchart of a charging method according to an embodiment of the present application is shown. The charging method can comprise the following steps:

in step 1501, when the second output port of the front-stage circuit outputs a high level, the first voltage boost circuit turns on the first NMOS transistor under the control of the high level to charge the high-side circuit.

In step 1502, when the second output port of the front-stage circuit outputs a low level, the first voltage boost circuit turns off the first NMOS transistor under the control of the low level to stop charging the high-side circuit.

The working principle of the bootstrap circuit may refer to the description above, and is not described herein again.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

The above description should not be taken as limiting the embodiments of the present application, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the embodiments of the present application should be included in the scope of the embodiments of the present application.

Claims (10)

1. A bootstrap circuit in a high voltage integrated circuit, the bootstrap circuit comprising: the device comprises a preceding stage circuit, a first booster circuit, a first NMOS (N-channel metal oxide semiconductor) tube and a resistor;

a power supply port of the preceding stage circuit is connected with a power supply VCC, at least one control port of the preceding stage circuit is connected with a control signal output port, a first output port of the preceding stage circuit is connected with a source electrode of the first NMOS tube, a second output port of the preceding stage circuit is connected with an input port of the first booster circuit, an output port of the first booster circuit is connected with a grid electrode of the first NMOS tube, a substrate of the first NMOS tube is connected to the power supply VCC through the resistor, and a drain electrode of the first NMOS tube is used as an output port of the bootstrap circuit and is connected with a high-side circuit; the front-stage circuit comprises a medium-voltage device or a low-voltage device;

when the second output port of the preceding stage circuit outputs a high level, the first voltage boosting circuit turns on the first NMOS tube under the control of the high level so as to charge the high-side circuit; when the second output port of the preceding stage circuit outputs a low level, the first voltage boosting circuit turns off the first NMOS tube under the control of the low level so as to stop charging the high-side circuit.

2. The circuit of claim 1, wherein the front-stage circuit comprises: the circuit comprises a first diode, a clamping protection circuit and a buffer;

the positive end of the first diode is a power supply port of the front-stage circuit, the negative end of the first diode is connected with the clamping protection circuit, and the negative end of the first diode is a first output port of the front-stage circuit;

the input port of the buffer is a control port of the preceding stage circuit, and the output port of the buffer is a second output port of the preceding stage circuit.

3. The circuit of claim 1, wherein the front-stage circuit comprises: the circuit comprises a clamping protection circuit, a second booster circuit, an input logic circuit and a second NMOS tube;

a first input port of the input logic circuit is a first control port of the preceding stage circuit, a second input port of the input logic circuit is a second control port of the preceding stage circuit, a first output port of the input logic circuit is connected with an input port of the second booster circuit, and a second output port of the input logic circuit is a second output port of the preceding stage circuit;

the output port of the second booster circuit is connected with the grid electrode of the second NMOS tube, the source electrode of the second NMOS tube is in short circuit with the substrate and then serves as the power supply port of the preceding stage circuit, and the drain electrode of the second NMOS tube is connected with the clamping protection circuit and then serves as the first output port of the preceding stage circuit.

4. The circuit of claim 3,

when the input of the first input port of the input logic circuit is high level, the output of the first output port and the second output port of the input logic circuit is low level;

when the first input port of the input logic circuit inputs a low level and the second input port inputs a high level, the first output port and the second output port of the input logic circuit output a high level;

when the first input port of the input logic circuit inputs a low level and the second input port inputs a low level, the first output port of the input logic circuit outputs a low level and the second output port outputs a high level.

5. The circuit of claim 1, wherein the front-stage circuit comprises: the input and feedback logic circuit, the second booster circuit, the clamping and voltage detection circuit and the second NMOS tube;

the input port of the input and feedback logic circuit is the control port of the preceding stage circuit, the first output port of the input and feedback logic circuit is connected with the input port of the second booster circuit, the second output port of the input and feedback logic circuit is the second output port of the preceding stage circuit, and the feedback control port of the input and feedback logic circuit is connected with the output port of the clamping and voltage detecting circuit;

the output port of the second booster circuit is connected with the grid electrode of the second NMOS tube, the source electrode of the second NMOS tube is in short circuit with the substrate and then serves as the power supply port of the preceding stage circuit, and the drain electrode of the second NMOS tube is connected with the input end of the clamping and voltage detecting circuit and then serves as the first output port of the preceding stage circuit.

6. The circuit of claim 5,

when the input of the input port of the input and feedback logic circuit is high level, the output of the first output port and the second output port of the input and feedback logic circuit is low level;

when the input of the input port of the input and feedback logic circuit is low level, the output of the second output port of the input and feedback logic circuit is high level;

when the input of the input port of the input and feedback logic circuit is low level and the input of the feedback control port of the input and feedback logic circuit is high level, the output of the first output port of the input and feedback logic circuit is high level.

7. The circuit of claim 1, wherein the first boost circuit comprises: the circuit comprises a delay circuit, a logic circuit, an oscillator, a counter, a power failure detection circuit, a clamping and overvoltage detection circuit, a first capacitor, a second diode, a third diode, a fourth diode, a first switch and a second switch;

the input port of the delay circuit is connected with the first set input port of the logic circuit and then is the input port of the first booster circuit, the output port of the delay circuit is connected with one end of the first capacitor, and the other end of the first capacitor is connected with the cathode of the second diode, the cathode of the fourth diode, one end of the second switch, the input port of the clamping and overvoltage detection circuit and the input port of the power failure detection circuit respectively and then is used as the output port of the first booster circuit;

a second set input port of the logic circuit is respectively connected with an output end of the power failure detection circuit and a zero clearing input end of the counter, a first reset input port of the logic circuit is connected with an output end of the counter, a second reset input port of the logic circuit is connected with an output port of the clamping and overvoltage detection circuit, and an output port of the logic circuit is connected with an enable input port of the oscillator; the output port of the oscillator is respectively connected with the pulse input port of the counter and one end of the second capacitor, and the other end of the second capacitor is respectively connected with the cathode of the third diode and the anode of the fourth diode;

one end of the first switch is connected with the power supply VCC, and the other end of the first switch is connected with the anode of the second diode and the anode of the third diode respectively.

8. The circuit of claim 7,

when the input end of the first booster circuit is in a high level, after a preset time period, the output end of the first booster circuit outputs a voltage value which is higher than the power supply voltage value of the power supply VCC and is less than 2 times of the power supply voltage value;

when the input end of the first booster circuit inputs a low level, the output end of the first booster circuit outputs a low level.

9. The circuit according to any one of claims 1 to 8,

the substrate in the first NMOS tube is connected to the power supply VCC through the resistor; alternatively, the first and second electrodes may be,

the substrate in the first NMOS tube is connected to the source electrode through the resistor; alternatively, the first and second electrodes may be,

the substrate in the first NMOS tube is grounded.

10. A charging method for use in a bootstrap circuit as claimed in any one of claims 1 to 9, the method comprising:

when the second output port of the preceding stage circuit outputs a high level, the first voltage boosting circuit turns on the first NMOS tube under the control of the high level so as to charge the high-side circuit;

when the second output port of the preceding stage circuit outputs a low level, the first voltage boosting circuit turns off the first NMOS tube under the control of the low level so as to stop charging the high-side circuit.

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