CN114050138A - Semiconductor package structure and manufacturing method thereof - Google Patents

Semiconductor package structure and manufacturing method thereof Download PDF

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Publication number
CN114050138A
CN114050138A CN202111188724.XA CN202111188724A CN114050138A CN 114050138 A CN114050138 A CN 114050138A CN 202111188724 A CN202111188724 A CN 202111188724A CN 114050138 A CN114050138 A CN 114050138A
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China
Prior art keywords
semiconductor package
package structure
lead
wire
electronic element
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CN202111188724.XA
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Chinese (zh)
Inventor
涂顺财
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to CN202111188724.XA priority Critical patent/CN114050138A/en
Publication of CN114050138A publication Critical patent/CN114050138A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H01L23/4855—Overhang structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02333—Structure of the redistribution layers being a bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02335—Free-standing redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The semiconductor package structure and the manufacturing method thereof provided by the present disclosure utilize a wire bond (wire bond) process to simultaneously manufacture the conductive posts for the upper and lower connection and the electrical connection members for connecting the electronic elements and the redistribution layer, thereby improving the process efficiency, and thus avoiding the pillar collapse phenomenon caused by the photoresist stripping (Stripe) process.

Description

Semiconductor package structure and manufacturing method thereof
Technical Field
The disclosure relates to the technical field of semiconductors, and particularly relates to a semiconductor packaging structure and a manufacturing method thereof.
Background
With the development of semiconductor packaging technology, various three-dimensional packaging technologies, such as Fan-Out Package on Package (FOPoP), have been developed to improve electrical performance and save packaging space.
In the Chip First (Chip First) process, if the FOPoP structure is to be formed, the conductive Pillar (pilar) for connecting up and down needs to be formed First, and then the Chip pickup operation is performed, however, the manufacturing of the conductive Pillar (pilar) is time-consuming and labor-consuming, and when the conductive Pillar with the diameter smaller than 70um is manufactured, the problem of Pillar collapse occurs in the photoresist stripping (Stripe) process because the conductive Pillar is too thin and the adhesion capability of the carrier plate is not strong. In addition, it is difficult to fabricate the conductive pillars with high Aspect Ratio (Aspect Ratio), i.e., the conductive pillars with smaller diameter.
Disclosure of Invention
The present disclosure provides a semiconductor package structure and a method of manufacturing the same.
In a first aspect, the present disclosure provides a semiconductor package structure, including:
an electronic component;
the first lead is arranged on one side of the electronic element;
the second lead is arranged on the active surface of the electronic element and is electrically connected with the electronic element, and the second lead is inclined relative to the first lead;
and the mold sealing layer covers the electronic element, the first lead and the second lead and exposes the end part of the first lead and the end part of the second lead.
In some optional embodiments, the semiconductor package structure further comprises:
and the rewiring layer is arranged on the mold sealing layer and is electrically connected with the first lead and the second lead respectively.
In some alternative embodiments, the first and second wires are formed from primary leads.
In some alternative embodiments, the first bonding end of the first wire to the bottom surface of the molding layer includes a first nodule, and an angle between the first nodule and the bottom surface of the molding layer is between 87 degrees and 92 degrees.
In some alternative embodiments, the second bonding end of the second wire to the electronic component includes a second wire cut region and a second knob.
In some alternative embodiments, the second knot ball is disposed on the second wire cutting region.
In some alternative embodiments, the second wire cut region is provided on the second stud ball.
In some optional embodiments, the semiconductor package structure further comprises:
a heat dissipation structure to which heat of the electronic element is transferred through the second conductive line.
In some optional embodiments, the semiconductor package structure further comprises:
and the external electric connector is arranged on the redistribution layer and is electrically connected with the redistribution layer.
In a second aspect, the present disclosure provides a method of manufacturing a semiconductor package structure, comprising:
placing electronic components on a carrier plate;
connecting two ends of a lead to the carrier plate and the electronic element respectively;
forming a mold sealing layer for coating the electronic element and the lead;
and thinning the molding sealing layer to expose the first conducting wire and the second conducting wire.
In some optional embodiments, the connecting both ends of the conductive wire to the carrier board and the electronic component respectively includes:
and firstly, jointing one end of the lead to the carrier plate, and then jointing the other end of the lead to the electronic element.
In some alternative embodiments, said bonding the other end of said wire to said electronic component further comprises:
and after the lead is vertically pulled up, the other end of the lead is jointed on the electronic element.
In some optional embodiments, the method further comprises:
and forming a rewiring layer on the molding layer.
In some optional embodiments, the method further comprises:
forming an external electrical connection on the redistribution layer.
The semiconductor package structure and the manufacturing method thereof provided by the present disclosure utilize a wire bond (wire bond) process to simultaneously manufacture the conductive posts for the upper and lower connection and the electrical connection members for connecting the electronic elements and the redistribution layer, thereby improving the process efficiency, and thus avoiding the pillar collapse phenomenon caused by the photoresist stripping (Stripe) process.
Drawings
Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
fig. 1 is a first structural schematic diagram of a semiconductor package structure according to the present disclosure;
FIG. 2 is a schematic structural view of a first mating end and a second mating end according to the present disclosure;
fig. 3 is a second schematic structural view of a semiconductor package structure according to the present disclosure;
fig. 4 is a third structural schematic of a semiconductor package structure according to the present disclosure;
fig. 5 to 11 are schematic structural views in the manufacturing process of the semiconductor package structure according to the present disclosure.
Description of the symbols:
1-electronic component, 2-first wire, 3-second wire, 4-molding layer, 5-rewiring layer, 6-first bonding ball, 7-second bonding ball, 8-second wire cutting area, 9-external electrical connector, 10-carrier plate, 11-temporary adhesive layer, 12-adhesive layer, 13-wire, 14-heat dissipation structure.
Detailed Description
The following description of the embodiments of the present disclosure will be provided in conjunction with the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems and effects of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.
It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the conditions under which the present disclosure can be implemented, so they are not technically significant, and any modifications of the structures, changes in the proportions and adjustments of the dimensions should be made without affecting the efficacy and attainment of the same. In addition, the terms "above", "first", "second" and "a" as used herein are for the sake of clarity only, and are not intended to limit the scope of the present disclosure, and changes or modifications of the relative relationship may be made without substantial changes in the technical content.
In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
As shown in fig. 1, the semiconductor package structure may include: electronic component 1, first wire 2, second wire 3, mold layer 4, redistribution layer 5 and external electrical connection 9. Wherein the first conducting wire 2 can be arranged at one side of the electronic component 1. The second conductive line 3 may be disposed on the active surface of the electronic component 1 and electrically connected to the electronic component 1. The second conductive line 3 may be inclined with respect to the first conductive line 2, and the second conductive line 3 may be inclined toward the first conductive line 2 (refer to fig. 6 further). The mold seal 4 may cover the electronic component 1, the first conductive line 2, and the second conductive line 3, and the mold seal 4 may expose an end of the first conductive line 2 and an end of the second conductive line 3. A rewiring layer 5 may be provided on the mold seal and electrically connected to the first and second wires 2 and 3, respectively. The external electrical connection 9 may be provided on the rewiring layer 5 and electrically connected to the rewiring layer 5.
In the present embodiment, the electronic component 1 may be a chip with various functions, such as an Electronic Integrated Circuit (EIC) chip and a Power Management Integrated Circuit (PMIC) chip.
In the present embodiment, the first wire 2 and the second wire 3 may be formed of a primary lead. Specifically, the end portions and the sidewalls of the first conductive lines 2 and the second conductive lines 3 have no seed layer, so that the first conductive lines 2 and the second conductive lines 3 are not formed by a photolithography process, nor formed by a Through Mold Via (TMV) process, but the first conductive lines 2 and the second conductive lines 3 are simultaneously formed by a wire bond (wire bond) process.
In the present embodiment, the external electrical connection members 9 may be solder balls, Ball Grid Array (BGA) balls, controlled collapse chip connection (C4) bumps or micro bumps, for example.
As shown in fig. 2 (a), the first bonding end of the first wire 2 and the bottom surface of the mold layer 4 may include a first nodule 6, and an angle θ between the first nodule 6 and the bottom surface of the mold layer 4 is between 87 degrees and 92 degrees.
As shown in fig. 2 (b), the second bonding end of the second wire 3 and the electronic component 1 may include a second wire cutting region 8 and a second knob 7. The second stud ball 7 may be provided on the second wire cutting region 8.
As shown in fig. 2 (c), a second wire cutting region 8 may be provided on the second stud bump 7.
As shown in fig. 3, the first bonding ends of the first wires 2 and the bottom surface of the mold layer 4 in the semiconductor package structure shown in fig. 3 may not include the nodules, as compared to the semiconductor package structure shown in fig. 1, because the nodules may be ground away during the process of thinning the mold layer 4.
As shown in fig. 4, the semiconductor package structure shown in fig. 4 may further include a heat dissipation structure 14, as opposed to the semiconductor package structure shown in fig. 1. The heat dissipating structure 14 may perform a heat dissipating function and may be a heat sink or other conductive material such as aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni), stainless steel, etc. Here, the first wire 2 may serve as a heat transfer path (heat dissipation path) from the electronic element 1 to the heat dissipation structure 14.
In other cases, the first wire 2 may also serve as an antenna conductor.
Fig. 5 to 11 are schematic structural views in the manufacturing process of the semiconductor package structure according to the present disclosure.
As shown in fig. 5, the electronic component 1 is placed on a carrier board 10.
Here, the carrier plate may have a temporary adhesive layer 11 (e.g. a glue strip). The electronic component 1 may be fixed to the carrier board by an adhesive layer 12, such as a Die Attach Film (DAF).
As shown in fig. 6, both ends of the wire 13 are connected to the carrier board 10 and the electronic component 1, respectively.
Specifically, one end of the wire 13 is bonded to the carrier 10, the wire 13 is pulled vertically, and then the other end of the wire 13 is bonded to the electronic component 1. The first conductive line 2 may be a portion formed before the conductive line 13 is pulled up, and the second conductive line 3 may be a portion formed after the conductive line 13 is pulled up.
As shown in fig. 7, the mold coat 4 covering the electronic component 1 and the wires 13 is formed.
As shown in fig. 8, the mold seal layer 4 is thinned to expose the first and second conductive lines 2 and 3.
Specifically, the thinning process may be, for example, a Grinding (Grinding) or Chemical Mechanical Polishing (CMP) process.
As shown in fig. 9, a rewiring layer 5 is formed on the mold seal layer 4.
As shown in fig. 10, an external electrical connection member 9 is formed on the rewiring layer 5.
As shown in fig. 11, the cutting is individualized.
The semiconductor package structure and the manufacturing method thereof provided by the present disclosure utilize a wire bond (wire bond) process to simultaneously manufacture the conductive posts for the upper and lower connection and the electrical connection members for connecting the electronic elements and the redistribution layer, thereby improving the process efficiency, and thus avoiding the pillar collapse phenomenon caused by the photoresist stripping (Stripe) process.
While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction in the present disclosure and the actual device due to variables in the manufacturing process and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed in this disclosure have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated in the present disclosure, the order and grouping of the operations is not a limitation of the present disclosure.

Claims (10)

1. A semiconductor package structure, comprising:
an electronic component;
the first lead is arranged on one side of the electronic element;
the second lead is arranged on the active surface of the electronic element and is electrically connected with the electronic element, and the second lead is inclined relative to the first lead;
and the mold sealing layer covers the electronic element, the first lead and the second lead and exposes the end part of the first lead and the end part of the second lead.
2. The semiconductor package structure of claim 1, wherein the semiconductor package structure further comprises:
and the rewiring layer is arranged on the mold sealing layer and is electrically connected with the first lead and the second lead respectively.
3. The semiconductor package structure of claim 1, wherein the first and second wires are formed from primary leads.
4. The semiconductor package structure of claim 1, wherein the first bonding end of the first wire to the bottom surface of the mold seal comprises a first nodule, and an angle between the first nodule and the bottom surface of the mold seal is between 87 degrees and 92 degrees.
5. The semiconductor package structure of claim 1, wherein the second bonding end of the second wire and the electronic component comprises a second wire cut region and a second ball.
6. The semiconductor package structure of claim 5, wherein the second ball is disposed on the second wire cut region.
7. The semiconductor package structure of claim 5, wherein the second wire cut region is disposed on the second ball.
8. The semiconductor package structure of claim 1, wherein the semiconductor package structure further comprises:
a heat dissipation structure to which heat of the electronic element is transferred through the first conductive line.
9. The semiconductor package structure of claim 2, wherein the semiconductor package structure further comprises:
and the external electric connector is arranged on the redistribution layer and is electrically connected with the redistribution layer.
10. A method of fabricating a semiconductor package structure, comprising:
placing electronic components on a carrier plate;
connecting two ends of a lead to the carrier plate and the electronic element respectively;
forming a mold sealing layer for coating the electronic element and the lead;
and thinning the molding sealing layer to expose the first conducting wire and the second conducting wire.
CN202111188724.XA 2021-10-12 2021-10-12 Semiconductor package structure and manufacturing method thereof Pending CN114050138A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111188724.XA CN114050138A (en) 2021-10-12 2021-10-12 Semiconductor package structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111188724.XA CN114050138A (en) 2021-10-12 2021-10-12 Semiconductor package structure and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN114050138A true CN114050138A (en) 2022-02-15

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