CN114050115A - Defect detection method, memory and manufacturing method thereof - Google Patents

Defect detection method, memory and manufacturing method thereof Download PDF

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Publication number
CN114050115A
CN114050115A CN202111372327.8A CN202111372327A CN114050115A CN 114050115 A CN114050115 A CN 114050115A CN 202111372327 A CN202111372327 A CN 202111372327A CN 114050115 A CN114050115 A CN 114050115A
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semiconductor layer
layer
semiconductor substrate
semiconductor
defects
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陈洁
邢彦召
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2648—Characterising semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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  • Semiconductor Memories (AREA)

Abstract

The invention provides a defect detection method, a memory and a manufacturing method thereof. The defect detection method comprises the following steps: providing a semiconductor substrate with a stacking structure on the surface, wherein the semiconductor substrate has a first doping type, a channel through hole penetrating through the semiconductor substrate is formed in the stacking structure, and a semiconductor layer is formed at the bottom of the channel through hole; doping the semiconductor layer to make the semiconductor layer have a second doping type, the semiconductor layer being in contact with the semiconductor substrate to form a PN junction; and testing the electrical property of the PN junction to characterize the defects in the semiconductor layer. The method can detect the quality of the semiconductor layer which is selectively epitaxially grown in the process of the memory, thereby improving the performance of the device and the yield of the product.

Description

Defect detection method, memory and manufacturing method thereof
Technical Field
The invention relates to the technical field of memories, in particular to a defect detection method, a memory and a manufacturing method thereof.
Background
In the prior art process for manufacturing a NAND memory, a semiconductor layer is Selectively Epitaxially Grown (SEG) on the bottom of a trench via, and then a memory structure is formed on the semiconductor layer in the trench via, wherein the existence of defects in the semiconductor layer plays an important role in a memory cell. The fewer defects in the semiconductor layer, the better the effect of suppressing the leakage current; the carrier migration rate of the tube determines the turn-off speed of a Bottom Select Gate (BSG); in addition, the semiconductor layer with fewer defects can also effectively support the upper storage structure.
However, it is only possible to characterize whether the semiconductor layer meets the quality requirements by its structure itself, for example, the height of the semiconductor layer is about 127nm, the diameter of the void (void) is >30nm, there is no obvious defect in the structure, etc. The most important electrical test can only be fed back in the final Wafer Acceptance Test (WAT) process, and although the above requirements can ensure the quality of the semiconductor layer to a certain extent, if defects, such as fine voids, exist in the semiconductor layer, they are often found in the final WAT test, which greatly affects the device performance and the product yield.
Therefore, there is a need for a method for detecting the electrical property of the semiconductor layer at the bottom of the trench via in the memory in real time to characterize the quality of the semiconductor layer and to compare the effectiveness of different pretreatment methods in the semiconductor layer preparation process.
Disclosure of Invention
The invention mainly aims to provide a defect detection method, a memory and a manufacturing method thereof, and aims to solve the problem that the quality of a semiconductor layer grown through selective epitaxy cannot be detected in the process of manufacturing the memory in the prior art, so that the performance of a device and the yield of products are influenced.
In order to achieve the above object, according to one aspect of the present invention, there is provided a defect detection method including the steps of: providing a semiconductor substrate with a stacking structure on the surface, wherein the semiconductor substrate has a first doping type, a channel through hole penetrating through the semiconductor substrate is formed in the stacking structure, and a semiconductor layer is formed at the bottom of the channel through hole; doping the semiconductor layer to make the semiconductor layer have a second doping type, the semiconductor layer being in contact with the semiconductor substrate to form a PN junction; and testing the electrical property of the PN junction to characterize the defects in the semiconductor layer.
Further, the semiconductor layer is a selective epitaxial growth silicon layer.
Further, testing the electrical properties of the PN junction to characterize defects in the semiconductor layer, including: forming a conductor layer on the semiconductor layer in the trench via; conducting the PN junction; obtaining an ideal factor of the PN junction by measuring the current value of the conductor layer; and (4) according to the ideal factor, characterizing whether defects exist in the semiconductor layer.
Further, characterizing the presence or absence of defects in the semiconductor layer according to an ideality factor includes: characterizing the presence of defects in the semiconductor layer if the ideal factor is greater than 1; in the case where the ideal factor is equal to 1, the absence of defects in the semiconductor layer is characterized.
Further, the defect detection method further comprises the step of characterizing the number of defects in the semiconductor layer at the bottom of the different channel vias: acquiring ideal factors of PN junctions corresponding to different semiconductor layers; the ideality factors are sorted from large to small, and the number of defects in the semiconductor layer corresponding to each ideality factor is decreased in sequence.
Further, the material forming the conductor layer includes any one or more of metals W, Al, Cu, Ti, Ag, Au, Pt, and Ni.
Further, the first doping type is N type, and the semiconductor layer is doped by P type dopant ions so as to enable the semiconductor layer to have a second doping type, wherein the P type dopant ions comprise any one or more of B, Al, Ga and In; or the first doping type is P-type, and the semiconductor layer is doped with N-type dopant ions including any one or more of P, As, N, and Sb to make the semiconductor layer have the second doping type.
According to another aspect of the present invention, there is provided a method for manufacturing a memory, including the steps of: providing a semiconductor substrate with a stacking structure on the surface, wherein the semiconductor substrate is provided with a first doping type, and the stacking structure comprises a sacrificial layer and an isolation layer which are alternately stacked along the direction far away from the semiconductor substrate; forming a channel through hole penetrating to the semiconductor substrate in the stacked structure, and forming a semiconductor layer at the bottom of the channel through hole; whether the defects exist in the semiconductor layer is represented by the defect detection method; forming a memory structure in contact with the semiconductor layer in the trench via without defects in the characterizing semiconductor layer; and removing the sacrificial layer, and forming a gate structure at the position corresponding to the sacrificial layer.
Further, removing the sacrificial layer, and forming a gate structure at a position corresponding to the sacrificial layer, including: forming a gate spacer penetrating the stacked structure to the semiconductor substrate; replacing the sacrificial layer with a gate structure; a common source is formed in the gate spacer.
According to another aspect of the present invention, there is also provided a memory including: the semiconductor substrate is provided with a gate stack structure on the surface, the semiconductor substrate is provided with a first doping type, and the stack structure comprises gate structures and isolating layers which are alternately stacked along the direction far away from the semiconductor substrate; a trench via penetrating the stacked structure to the semiconductor substrate; the semiconductor layer is arranged at the bottom of the channel through hole, has a second doping type and forms a PN junction through being in contact with the semiconductor substrate; and the storage structure is arranged in the channel through hole and is in contact with the semiconductor layer.
The technical scheme of the invention provides a defect detection method, which can be applied to the process of forming a memory, wherein after a semiconductor layer is formed at the bottom of a channel through hole, the semiconductor layer is doped firstly so as to have a second doping type, so that the semiconductor layer is contacted with a semiconductor substrate to form a PN junction, then the PN junction is conducted to obtain an ideal factor of the PN junction, and whether a defect exists in the semiconductor layer is represented according to the ideal factor. According to the formula of the ideality factor, when the recombination current is dominant, the ideality factor is close to 2, when the diffusion current is dominant, the ideality factor is close to 1, and usually, the ideality factor is between 1 and 2. Therefore, the method can detect the quality of the semiconductor layer which is selectively and epitaxially grown in the process of the memory, and further improves the performance of the device and the yield of products.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic cross-sectional view illustrating a base after a semiconductor substrate having a stacked structure on a surface thereof is provided, wherein the semiconductor substrate has a first doping type, a channel via penetrating through the semiconductor substrate is formed in the stacked structure, and a semiconductor layer is formed at a bottom of the channel via;
FIG. 2 is a schematic cross-sectional view of the substrate after forming a conductor layer on the semiconductor layer in the trench via shown in FIG. 1;
fig. 3 is a schematic cross-sectional view illustrating a base after a semiconductor substrate having a stacked structure on a surface thereof is provided in a method for manufacturing a memory according to an embodiment of the present disclosure, wherein the semiconductor substrate has a first doping type, and the stacked structure includes a sacrificial layer and an isolation layer alternately stacked in a direction away from the semiconductor substrate;
FIG. 4 is a schematic cross-sectional view illustrating a substrate after forming a channel via penetrating to a semiconductor substrate and forming a semiconductor layer at the bottom of the channel via in the stacked structure shown in FIG. 3;
FIG. 5 is a schematic cross-sectional view of the substrate after forming a memory structure in the trench via shown in FIG. 4;
FIG. 6 is a schematic cross-sectional view of the body after forming gate spacers through the stacked structure of FIG. 5 to a semiconductor substrate;
FIG. 7 is a schematic cross-sectional view of the substrate after the sacrificial layer of FIG. 6 is replaced with a gate structure;
fig. 8 is a schematic diagram showing a cross-sectional structure of the substrate after forming a common source in the gate spacer shown in fig. 7.
Wherein the figures include the following reference numerals:
10. a semiconductor substrate; 20. a stacked structure; 210. a sacrificial layer; 220. an isolation layer; 230. a trench via; 30. a semiconductor layer; 40. a conductor layer; 50. a storage structure; 60. a gate spacer; 70. a doped region; 80. selecting a gate dielectric layer; 90. a gate structure; 100. back etching the channel; 110. an insulating material; 120. a common source.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As described in the background art, there is a need in the art for a method for detecting the electrical properties of a semiconductor layer grown by selective epitaxy in a memory in real time to characterize the quality of the semiconductor layer and to compare the effectiveness of different pretreatment methods in the semiconductor layer manufacturing process.
The inventor of the present invention has studied the above problems and proposed a defect detection method comprising the steps of: providing a semiconductor substrate with a stacking structure on the surface, wherein the semiconductor substrate has a first doping type, a channel through hole penetrating through the semiconductor substrate is formed in the stacking structure, and a semiconductor layer is formed at the bottom of the channel through hole; doping the semiconductor layer to make the semiconductor layer have a second doping type, the semiconductor layer being in contact with the semiconductor substrate to form a PN junction; and testing the electrical property of the PN junction to characterize the defects in the semiconductor layer.
According to the defect detection method, the semiconductor layer is contacted with the semiconductor substrate to form the PN junction, then the PN junction is conducted to obtain the ideal factor of the PN junction, according to the formula of the ideal factor, when the recombination current is main, the ideal factor is close to 2, when the diffusion current is main, the ideal factor is close to 1, usually, the ideal factor is between 1 and 2, because the recombination depends on the number of recombination centers, namely the defect number of a barrier region, the more defects, the more recombination centers, the larger recombination current, when no recombination centers exist, the carriers are hardly recombined, the recombination current is zero, only the diffusion current exists, and therefore, whether the defects exist in the semiconductor layer at the bottom of a channel through hole can be represented through the value of the ideal factor. Therefore, the method is different from the prior art that the quality of the semiconductor layer can be represented only through the semiconductor layer itself or through the WAT test at last, and the quality of the semiconductor layer which is selectively epitaxially grown can be detected in the process of the memory, so that the performance of the device and the yield of the product are improved.
Exemplary embodiments of a defect detection method provided according to the present invention will be described in more detail below with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
First, a semiconductor substrate 10 having a stacked structure on a surface thereof is provided, the semiconductor substrate 10 having a first doping type, a channel via 230 penetrating the semiconductor substrate 10 is formed in the stacked structure 20, and a semiconductor layer 30 is formed at a bottom of the channel via 230, as shown in fig. 1.
The material of the semiconductor substrate 10 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide.
The semiconductor substrate 10 has a first doping type, which may be P-type or N-type, and is not limited herein. The P-type doped semiconductor substrate 10 may be formed by ion implantation of an N-type dopant such as phosphorus, arsenic, nitrogen, or antimony, and the N-type doped semiconductor substrate 10 may be formed by ion implantation of a P-type dopant such as boron, aluminum, gallium, or indium.
The semiconductor substrate 10 is formed with a stacked structure 20, and the isolation layer 220 and the sacrificial layer 210 in the stacked structure 20 can be formed by a conventional deposition process in the prior art, such as a chemical vapor deposition process. Those skilled in the art can set the number of the sacrificial layer 210 and the isolation layer 220 according to actual requirements, and those skilled in the art can select the types of the isolation layer 220 and the sacrificial layer 210 according to the prior art, where the isolation layer 220 may be SiO2The sacrificial layer 210 may be SiN.
The portion of the channel via 230 in the semiconductor substrate 10 is a first groove in which the semiconductor layer 30 is formed, and the semiconductor layer may be a silicon epitaxial layer obtained by performing Selective Epitaxial Growth (SEG).
After the step of providing the semiconductor layer 30 at the bottom of the channel via 230 as described above, the semiconductor layer 30 is doped so that the semiconductor layer 30 has the second doping type, and the semiconductor layer 30 is in contact with the semiconductor substrate 10 to form a PN junction.
The semiconductor layer 30 has a second doping type, and the second doping type is a P type or an N type different from the first doping type in order to form a PN junction at a boundary between the semiconductor substrate 10 and the semiconductor layer, and the second doping type is an N type when the first doping type is a P type, or the second doping type is a P type when the first doping type is an N type, which is not limited herein. The P-type doped semiconductor layer 30 may be formed by ion implantation of an N-type dopant such As phosphorus (P), arsenic (As), nitrogen (N), or antimony (Sb), and the N-type doped semiconductor layer 30 may be formed by ion implantation of a P-type dopant such As boron (B), aluminum (Al), gallium (Ga), or indium (In).
In order to provide the semiconductor layer with the second doping type, in a preferred embodiment, the doping of the semiconductor layer 30 comprises: the semiconductor layer 30 is ion implanted and annealed to activate the semiconductor layer 30 to form P-type doping or N-type doping. The annealing treatment may be Rapid Thermal Annealing (RTA), and specific process conditions may refer to the prior art and are not described herein again.
After the step of forming the PN junction, the PN junction is conducted to obtain the ideal factor of the PN junction. The ideal factor of the PN junction has a general formula as follows: n ═ q/kT × dV/d (ln i)), where q/kT is a constant, and dV/d (ln i) can be obtained from the IV characteristic curve of the PN junction, and the specific calculation method may include: firstly measuring an I-V characteristic curve of the PN junction, then changing the value of the current I into lnI through software such as ORIGIN and the like so as to obtain a corresponding V-lnI characteristic curve, and obtaining the value of dV/d (lnI) through the slope of the midpoint of the curve.
When the composite current is dominant, the ideality factor n is close to 2; when the diffusion current is dominant, n is close to 1; typically n is between 1 and 2. Since recombination depends on the number of recombination centers, i.e. the number of defects in the barrier region, the more defects and the more recombination centers, the larger the recombination current, and n is close to 2; when no recombination center exists, the carriers are hardly recombined, the recombination current is zero, only the diffusion current exists, and n is 1; in practice, a PN junction barrier region always has a recombination center, so n is between 1 and 2 in general; n-1 represents a defect-free PN junction.
When the first doping type of the semiconductor substrate 10 is P-type doping and the second doping type of the semiconductor layer is N-type doping, in a preferred embodiment, the turning on of the PN junction to obtain the ideality factor of the PN junction includes: forming a conductor layer 40 on the semiconductor layer 30 in the trench via 230, as shown in fig. 2; applying a forward voltage to the semiconductor substrate 10 (the semiconductor substrate 10 side is connected to the positive electrode, and the conductor layer 40 side is connected to the negative electrode) to turn on the PN junction; by measuring the current value of the conductor layer 40, the ideality factor of the PN junction is obtained.
When the first doping type of the semiconductor substrate 10 is N-type doping and the second doping type of the semiconductor layer is P-type doping, in a preferred embodiment, the turning on of the PN junction to obtain the ideality factor of the PN junction includes: forming a conductor layer 40 on the semiconductor layer 30 in the trench via 230, as shown in fig. 2; applying a reverse bias voltage to the semiconductor substrate 10 (the conductor layer 40 side is connected to the positive electrode, and the semiconductor substrate 10 side is connected to the negative electrode) to turn on the PN junction; by measuring the current value of the conductor layer 40, the ideality factor of the PN junction is obtained.
In the above preferred embodiment, the material forming the conductor layer 40 may include any one or more of W, Al, Cu, Ti, Ag, Au, Pt and Ni. But not limited to the above, the person skilled in the art can make appropriate selections of the conductor material according to the prior art.
In a preferred embodiment, the above defect detection method of the present invention further comprises the step of characterizing the number of defects in the semiconductor layer 30 at the bottom of the different channel vias 230: acquiring ideal factors of PN junctions corresponding to different semiconductor layers 30; the ideality factors are ranked from large to small, and the number of defects in the semiconductor layer 30 corresponding to each ideality factor decreases in order.
Illustratively, the ideality factor n of the corresponding PN junction of the first semiconductor layer is obtained1，n1Obtaining an ideal factor n of a PN junction corresponding to the second semiconductor layer as 1.42，n2Obtaining an ideal factor n of a PN junction corresponding to the third semiconductor layer as 1.83，n31, mixing n with the above-mentioned solvent1、n2And n3In descending order, i.e. n2＞n1＞n3Due to the ideality factor n of the PN junction corresponding to the third semiconductor layer3And 1, defect-free in the third semiconductor layer can be characterized, and the number of defects in the second semiconductor layer is larger than that in the first semiconductor layer because the ideality factor of the PN junction corresponding to the second semiconductor layer is larger than that of the PN junction corresponding to the first semiconductor layer.
According to another aspect of the present invention, there is also provided a method for manufacturing a memory, including the steps of: providing a semiconductor substrate with a stacking structure on the surface, wherein the semiconductor substrate is provided with a first doping type, and the stacking structure comprises a sacrificial layer and an isolation layer which are alternately stacked along the direction far away from the semiconductor substrate; forming a channel through hole penetrating to the semiconductor substrate in the stacked structure, and forming a semiconductor layer at the bottom of the channel through hole; whether the defects exist in the semiconductor layer is represented by the defect detection method; forming a memory structure in contact with the semiconductor layer in the trench via without defects in the characterizing semiconductor layer; and removing the sacrificial layer, and forming a gate structure at the position corresponding to the sacrificial layer.
The method can detect the quality of the semiconductor layer in the process of the memory, thereby improving the performance of the device and the yield of products.
Exemplary embodiments of a method of fabricating a memory provided according to the present invention will be described in more detail below with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
First, a semiconductor substrate 10 having a stack structure 20 on a surface thereof is provided, the semiconductor substrate 10 having a first doping type, and the stack structure 20 includes a sacrificial layer 210 and an isolation layer 220 alternately stacked in a direction away from the semiconductor substrate 10, as shown in fig. 3.
The semiconductor substrate 10 is formed with a stacked structure 20, and the isolation layer 220 and the sacrificial layer 210 in the stacked structure 20 can be formed by a conventional deposition process in the prior art, such as a chemical vapor deposition process. Those skilled in the art can set the number of the sacrificial layer 210 and the isolation layer 220 according to actual requirements, and those skilled in the art can select the types of the isolation layer 220 and the sacrificial layer 210 according to the prior art, where the isolation layer 220 may be SiO2The sacrificial layer 210 may be SiN.
After the above step of providing the semiconductor substrate 10 having the stacked structure 20 on the surface, the channel via 230 penetrating to the semiconductor substrate 10 is formed in the stacked structure 20, and the semiconductor layer 30 is formed at the bottom of the channel via 230, as shown in fig. 4.
The portion of the trench via 230 in the semiconductor substrate 10 is a first recess, the semiconductor layer 30 is formed in the first recess, and the semiconductor layer 30 may be a silicon epitaxial layer obtained by performing Selective Epitaxial Growth (SEG) for connecting the source of the memory string after the memory is manufactured.
After the step of forming the semiconductor layer 30 at the bottom of the trench via 230, doping the semiconductor layer 30 to make the semiconductor layer 30 have the second doping type, contacting the semiconductor layer 30 with the semiconductor substrate 10 to form a PN junction, and testing the electrical property of the PN junction to characterize defects in the semiconductor layer 30.
In the defect detection method, the semiconductor layer 30 is doped to have a second doping type, and in order to form a PN junction at the boundary between the semiconductor substrate 10 and the semiconductor layer, the second doping type is a P type or an N type different from the first doping type, and when the first doping type is a P type, the second doping type is an N type, or when the first doping type is an N type, the second doping type is a P type, which is not limited herein. The P-type doped semiconductor layer may be formed by ion implantation of an N-type dopant such as phosphorus, arsenic, nitrogen, or antimony, and the N-type doped semiconductor layer may be formed by ion implantation of a P-type dopant such as boron, aluminum, gallium, or indium.
In order to make the semiconductor layer 30 have the second doping type, in a preferred embodiment, doping the semiconductor layer 30 includes: the semiconductor layer 30 is ion implanted and annealed to activate the semiconductor layer 30 to form a P-doped or N-doped semiconductor layer. The annealing treatment may be Rapid Thermal Annealing (RTA), and specific process conditions may refer to the prior art and are not described herein again.
Then, in the case where there is no defect in the characterization semiconductor layer 30, the memory structure 50 in contact with the semiconductor layer 30 is formed in the channel via 230, as shown in fig. 5.
In a preferred embodiment, the step of forming the memory structure 50 comprises: a charge blocking layer, an electron trapping layer, a tunneling layer, and a channel layer are sequentially formed on sidewalls of the channel hole in a stacked manner.
The material of each functional layer in the memory structure 50 can be reasonably selected by one skilled in the art according to the prior art, for example, the material of the charge blocking layer can be SiO2The charge trapping layer may be SiN and the tunneling layer may be SiO2The material of the channel layer may be polysilicon. Moreover, the above-mentioned memory structure 50 can be formed by a deposition process that is conventional in the art, and will not be described herein.
After the step of forming the memory structure 50 in the trench via 230, the sacrificial layer 210 is removed, and the gate structure 90 is formed at a position corresponding to the sacrificial layer 210, as shown in fig. 6 to 8.
The step S3 may further include forming a doped region 70 in the semiconductor substrate 10 in a region communicating with the gate spacer 60, the doped region 70 being of a doping type opposite to that of the semiconductor substrate 10; after the step of forming the doped region 70, the step S3 may further include a step of forming a select gate dielectric layer 80 on the doped region 70, as shown in fig. 6.
In a preferred embodiment, removing the sacrificial layer 210 and forming the gate structure 90 at a position corresponding to the sacrificial layer 210 includes: forming gate spacers 60 through the stacked structure 20 to the semiconductor substrate 10, as shown in fig. 6; replacing the sacrificial layer 210 with the gate structure 90; a common source 120 is formed in the gate spacer 60 as shown in fig. 7 and 8.
In the preferred embodiment, the gate isolation trench 60 is formed to allow the sacrificial layer 210 to have an exposed end surface, so that the sacrificial layer 210 can be wet-etched by using an etching solution from the exposed end surface to remove the sacrificial layer 210; moreover, by removing the sacrificial layer 210, a channel extending in the lateral direction can be formed at the position where the sacrificial layer 210 is removed, and the gate material can be deposited by using the channel as a deposition channel to obtain the gate structure 90, wherein the deposition process can be Atomic Layer Deposition (ALD); the material forming the gate structure 90 is typically a metal and may be selected from one or more of W, Al, Cu, Ti, Ag, Au, Pt and Ni.
After replacing the sacrificial layer 210 with the gate structure 90, the gate structure 90 may be etched back to form an etch-back channel 100 in communication with the gate spacer 60, as shown in fig. 7; filling the etch-back channel 100 and the gate spacer grooves 60 with an insulating material 110, and etching the insulating material 110 in the gate spacer grooves 60 to form an etched channel; a common source 120 is formed in the etched channel as shown in fig. 8.
According to another aspect of the present invention, there is also provided a memory including: the semiconductor substrate is provided with a gate stack structure on the surface, the semiconductor substrate is provided with a first doping type, and the stack structure comprises gate structures and isolating layers which are alternately stacked along the direction far away from the semiconductor substrate; a trench via penetrating the stacked structure to the semiconductor substrate; the semiconductor layer is arranged at the bottom of the channel through hole, has a second doping type and forms a PN junction through being in contact with the semiconductor substrate; and the storage structure is arranged in the channel through hole and is in contact with the semiconductor layer.
Since the semiconductor substrate in the above memory has the first doping type, the semiconductor layer has the second doping type, and the semiconductor layer is formed with a PN junction by being in contact with the semiconductor substrate, therefore, in the preparation process of the memory, the ideal factor of the PN junction can be obtained by conducting the PN junction, from the formula of the ideality factor, the ideality factor is close to 2 when the recombination current is dominant, and the ideality factor is close to 1 when the diffusion current is dominant, and usually the ideality factor is between 1 and 2, since the recombination depends on how many recombination centers, i.e., the number of defects in the barrier region, the more defects and recombination centers, the greater the recombination current, when no recombination centers are present, carriers are hardly recombined, the recombination current is zero, and then only diffusion current is present, the presence or absence of defects in the semiconductor layer at the bottom of the channel via can therefore be characterized by the value of the ideality factor. Therefore, the method is different from the prior art that the quality of the semiconductor layer can be represented only through the semiconductor layer itself or through the WAT test at last, and the quality of the semiconductor layer which is selectively epitaxially grown can be detected in the process of the memory, so that the performance of the device and the yield of the product are improved.
From the above description, it can be seen that the above-described embodiments of the present invention achieve the following technical effects:
the defect detection method is different from the prior art that the quality of the semiconductor layer can be represented only through the structure of the semiconductor layer or through the WAT test at last, and the quality of the semiconductor layer can be detected in the process of the memory, so that the performance of the device and the yield of products are improved.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A method of defect detection, comprising the steps of:
providing a semiconductor substrate with a stacking structure on the surface, wherein the semiconductor substrate is of a first doping type, a channel through hole penetrating through the semiconductor substrate is formed in the stacking structure, and a semiconductor layer is formed at the bottom of the channel through hole;
doping the semiconductor layer to make the semiconductor layer have a second doping type, the semiconductor layer being in contact with the semiconductor substrate to form a PN junction;
and testing the electrical property of the PN junction to characterize the defects in the semiconductor layer.
2. The defect detection method of claim 1, wherein the semiconductor layer is a selectively epitaxially grown silicon layer.
3. The method of claim 1, wherein testing the electrical properties of the PN junction to characterize defects in the semiconductor layer comprises:
forming a conductor layer on the semiconductor layer in the trench via;
conducting the PN junction;
obtaining an ideal factor of the PN junction by measuring the current value of the conductor layer;
and characterizing whether defects exist in the semiconductor layer according to the ideality factor.
4. The method of claim 3, wherein characterizing the presence or absence of defects in the semiconductor layer according to the ideality factor comprises:
characterizing the presence of defects in the semiconductor layer if the ideality factor is greater than 1;
characterizing the absence of defects in the semiconductor layer if the ideality factor is equal to 1.
5. The defect detection method of claim 3, further comprising the step of characterizing the number of defects in the semiconductor layer at different bottoms of the trench vias by:
acquiring ideal factors of the PN junctions corresponding to different semiconductor layers;
and sequencing the ideality factors from large to small, wherein the number of defects in the semiconductor layer corresponding to each ideality factor is reduced in sequence.
6. The defect detection method of claim 3, wherein a material forming the conductor layer comprises any one or more of metals W, Al, Cu, Ti, Ag, Au, Pt, and Ni.
7. The defect detection method according to any one of claims 1 to 6,
the first doping type is N type, the semiconductor layer is doped by P type dopant ions so as to enable the semiconductor layer to have the second doping type, and the P type dopant ions comprise any one or more of B, Al, Ga and In; or
The first doping type is P-type, and the semiconductor layer is doped with N-type dopant ions including any one or more of P, As, N, and Sb to have the second doping type.
8. A method for manufacturing a memory is characterized by comprising the following steps:
providing a semiconductor substrate with a stacking structure on the surface, wherein the semiconductor substrate is provided with a first doping type, and the stacking structure comprises a sacrificial layer and an isolation layer which are alternately stacked along the direction far away from the semiconductor substrate;
forming a channel through hole penetrating to the semiconductor substrate in the stacked structure, and forming a semiconductor layer at the bottom of the channel through hole;
characterizing the presence or absence of defects in the semiconductor layer using the defect detection method of any one of claims 1 to 7;
forming a memory structure in the channel via in contact with the semiconductor layer, in the absence of defects in the semiconductor layer being characterized;
and removing the sacrificial layer, and forming a gate structure at a position corresponding to the sacrificial layer.
9. The method of claim 8, wherein removing the sacrificial layer and forming a gate structure at a position corresponding to the sacrificial layer comprises:
forming gate spacers penetrating the stacked structure to the semiconductor substrate;
replacing the sacrificial layer with a gate structure;
a common source is formed in the gate spacer.
10. A memory, comprising:
a semiconductor substrate having a gate stack structure on a surface thereof, the semiconductor substrate having a first doping type, the stack structure including gate structures and isolation layers alternately stacked in a direction away from the semiconductor substrate;
a trench via penetrating the stacked structure to the semiconductor substrate;
the semiconductor layer is arranged at the bottom of the channel through hole, has a second doping type and forms a PN junction through being in contact with the semiconductor substrate;
and the storage structure is arranged in the channel through hole and is in contact with the semiconductor layer.
CN202111372327.8A 2021-11-18 2021-11-18 Defect detection method, memory and manufacturing method thereof Pending CN114050115A (en)

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