CN114048700A - Design method of semiconductor chip layout - Google Patents
Design method of semiconductor chip layout Download PDFInfo
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- CN114048700A CN114048700A CN202111287966.4A CN202111287966A CN114048700A CN 114048700 A CN114048700 A CN 114048700A CN 202111287966 A CN202111287966 A CN 202111287966A CN 114048700 A CN114048700 A CN 114048700A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/323—Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Architecture (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention provides a design method of a semiconductor chip layout, and relates to the technical field of semiconductors. The design method based on the semiconductor chip layout comprises the following design steps: s1, chip specification formulation, according to the design requirements proposed by the customer, and including the requirements of the chip in terms of specific functions and performance, making a design scheme and a specific implementation architecture, and dividing the module functions; s2, coding, namely, describing and implementing the module functions in the form of codes by using a Hardware Description Language (HDL); s3, verifying, performing simulation verification to check the correctness of the coding design, and performing logic synthesis after the simulation verification is passed; s4, layout planning, placing the macro-unit module of the chip, and determining the placing positions of various functional circuits on the whole; s5, wiring, clock wiring, normal signal wiring, and wiring for each standard cell. By the design method, the yield of the chip is effectively improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a design method of a semiconductor chip layout.
Background
The semiconductor refers to a material having a conductivity between a conductor and an insulator at normal temperature. Semiconductors are used in the fields of integrated circuits, consumer electronics, communication systems, photovoltaic power generation, lighting, high-power conversion, etc., for example, diodes are devices fabricated using semiconductors. The importance of semiconductors is enormous, both from a technological and economic point of view. Most electronic products, such as computers, mobile phones or digital audio recorders, have a core unit closely related to a semiconductor. Common semiconductor materials are silicon, germanium, gallium arsenide, etc., with silicon being one of the most influential of various semiconductor material applications.
A chip generally refers to a carrier for an integrated circuit, and is the result of the integrated circuit after design, fabrication, packaging, and testing, and is usually a stand-alone entity that can be used immediately. The two terms "chip" and "integrated circuit" are often used together, for example, in the commonly discussed topic, the integrated circuit design and the chip design are said to have one meaning, and the chip industry, the integrated circuit industry and the IC industry are also said to have one meaning. In fact, there is a link between these two words and a distinction is made. The integrated circuit entity is often in the form of a chip, because the narrow definition of the integrated circuit emphasizes the circuit itself, such as a phase-shifted oscillator formed by connecting only five elements together, which may also be called the integrated circuit when it is presented on the drawing, and when we want to use this small integrated circuit, it must be implemented as a separate entity, or embedded in a larger integrated circuit, depending on the chip; integrated circuits place more emphasis on circuit design and layout wiring, and chips place more emphasis on circuit integration, production, and packaging. While a generalized integrated circuit may also include various chip-related meanings when related to an industry (as distinguished from other industries)
However, the complexity of designing and manufacturing the chip is continuously increased at the present stage, which easily causes the yield of the chip to be reduced, and causes the performance effect of the chip to be poor, so a better design method of the semiconductor chip layout is required to solve the problem.
Disclosure of Invention
Technical problem to be solved
Aiming at the defects of the prior art, the invention provides a design method of a semiconductor chip layout, which solves the problems of high chip manufacturing difficulty and low yield.
(II) technical scheme
In order to achieve the purpose, the invention is realized by the following technical scheme: a design method of a semiconductor chip layout comprises the following design steps:
s1, chip specification formulation, according to the design requirements proposed by the customer, and including the requirements of the chip in terms of specific functions and performance, making a design scheme and a specific implementation architecture, and dividing the module functions;
s2, coding, namely, describing and implementing the module functions in the form of codes by using a Hardware Description Language (HDL);
s3, verifying, performing simulation verification to check the correctness of the coded design, performing logic synthesis after the simulation verification passes, translating the HDL code realized by the design into a gate-level netlist through the logic synthesis, setting constraint conditions when the logic synthesis is performed, and performing the simulation verification again after the logic synthesis is completed;
s4, layout planning, wherein the macro cell module for placing the chip determines the placing positions of various functional circuits on the whole, and planning and setting are required according to the regulations when the placing positions are carried out;
s5, wiring the clock independently, wherein the clock signal plays a global command role in the chip and is connected to each register unit in a symmetrical mode, and the delay difference is minimum; ordinary signal wiring, wiring various standard cells;
s6, layout physical verification, comprising the following steps:
s61, comparing and verifying the layout and the gate-level circuit diagram after logic synthesis;
s62, checking a design rule, and checking that the connection distance and the connection width need to meet the process requirements;
s63, checking electrical rules, and checking electrical rule violation of short circuit and open circuit lamps;
and S7, outputting data, and after the layout design is finished, delivering the output file to a manufacturer to produce a mask plate.
Preferably, in the step S5, the cells and the input and output are connected by metal wires according to the circuit logic relationship, and the chip area is ensured to be minimum.
Preferably, the layout and wiring need to use an LEF file and a TLF file, and the layout verification uses a unit layout data file and a layout verification command file.
(III) advantageous effects
The invention provides a design method of a semiconductor chip layout. The method has the following beneficial effects:
the design method of the semiconductor chip layout can effectively provide the required performance requirements and can improve the yield through more accurate design rules.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example (b):
the embodiment of the invention provides a design method of a semiconductor chip layout, which comprises the following design steps:
s1, chip specification formulation, according to the design requirements proposed by the customer, and including the requirements of the chip in terms of specific functions and performance, making a design scheme and a specific implementation architecture, and dividing the module functions;
s2, coding, namely, describing and implementing the module functions in the form of codes by using a Hardware Description Language (HDL);
s3, verifying, performing simulation verification to check the correctness of the coded design, performing logic synthesis after the simulation verification passes, translating the HDL code realized by the design into a gate-level netlist through the logic synthesis, setting constraint conditions when the logic synthesis is performed, and performing the simulation verification again after the logic synthesis is completed;
s4, layout planning, wherein the macro cell module for placing the chip determines the placing positions of various functional circuits on the whole, and planning and setting are required according to the regulations when the placing positions are carried out;
s5, wiring the clock independently, wherein the clock signal plays a global command role in the chip and is connected to each register unit in a symmetrical mode, and the delay difference is minimum; ordinary signal wiring, wiring various standard cells;
s6, layout physical verification, comprising the following steps:
s61, comparing and verifying the layout and the gate-level circuit diagram after logic synthesis;
s62, checking a design rule, and checking that the connection distance and the connection width need to meet the process requirements;
s63, checking electrical rules, and checking electrical rule violation of short circuit and open circuit lamps;
and S7, outputting data, and after the layout design is finished, delivering the output file to a manufacturer to produce a mask plate.
In step S5, the cells and the input/output cells are connected by metal wires according to the circuit logic relationship, and the chip area is ensured to be minimum.
The layout and wiring need to use an LEF file and a TLF file, and the layout verification uses a unit layout data file and a layout verification command file.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (3)
1. A design method of a semiconductor chip layout is characterized in that: comprises the following design steps:
s1, chip specification formulation, according to the design requirements proposed by the customer, and including the requirements of the chip in terms of specific functions and performance, making a design scheme and a specific implementation architecture, and dividing the module functions;
s2, coding, namely, describing and implementing the module functions in the form of codes by using a Hardware Description Language (HDL);
s3, verifying, performing simulation verification to check the correctness of the coded design, performing logic synthesis after the simulation verification passes, translating the HDL code realized by the design into a gate-level netlist through the logic synthesis, setting constraint conditions when the logic synthesis is performed, and performing the simulation verification again after the logic synthesis is completed;
s4, layout planning, wherein the macro cell module for placing the chip determines the placing positions of various functional circuits on the whole, and planning and setting are required according to the regulations when the placing positions are carried out;
s5, wiring the clock independently, wherein the clock signal plays a global command role in the chip and is connected to each register unit in a symmetrical mode, and the delay difference is minimum; ordinary signal wiring, wiring various standard cells;
s6, layout physical verification, comprising the following steps:
s61, comparing and verifying the layout and the gate-level circuit diagram after logic synthesis;
s62, checking a design rule, and checking that the connection distance and the connection width need to meet the process requirements;
s63, checking electrical rules, and checking electrical rule violation of short circuit and open circuit lamps;
and S7, outputting data, and after the layout design is finished, delivering the output file to a manufacturer to produce a mask plate.
2. The method for designing a semiconductor chip layout according to claim 1, characterized in that: in the step S5, the cells and the input/output cells are connected by metal wires according to the circuit logic relationship, and the chip area is ensured to be the minimum.
3. The method for designing a semiconductor chip layout according to claim 1, characterized in that: the layout and wiring need to use an LEF file and a TLF file, and the layout verification uses a unit layout data file and a layout verification command file.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111287966.4A CN114048700A (en) | 2021-11-02 | 2021-11-02 | Design method of semiconductor chip layout |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111287966.4A CN114048700A (en) | 2021-11-02 | 2021-11-02 | Design method of semiconductor chip layout |
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| Publication Number | Publication Date |
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| CN114048700A true CN114048700A (en) | 2022-02-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202111287966.4A Withdrawn CN114048700A (en) | 2021-11-02 | 2021-11-02 | Design method of semiconductor chip layout |
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| CN (1) | CN114048700A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114818560A (en) * | 2022-03-07 | 2022-07-29 | 江苏汤谷智能科技有限公司 | Chip development verification system platform based on simulation technology |
| CN115455892A (en) * | 2022-09-20 | 2022-12-09 | 珠海妙存科技有限公司 | Layout design method of module with low-voltage tube under advanced process |
-
2021
- 2021-11-02 CN CN202111287966.4A patent/CN114048700A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114818560A (en) * | 2022-03-07 | 2022-07-29 | 江苏汤谷智能科技有限公司 | Chip development verification system platform based on simulation technology |
| CN114818560B (en) * | 2022-03-07 | 2024-02-13 | 江苏汤谷智能科技有限公司 | Chip development verification system platform based on simulation technology |
| CN115455892A (en) * | 2022-09-20 | 2022-12-09 | 珠海妙存科技有限公司 | Layout design method of module with low-voltage tube under advanced process |
| CN115455892B (en) * | 2022-09-20 | 2023-06-13 | 珠海妙存科技有限公司 | Layout design method for low-voltage tube-containing module |
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Application publication date: 20220215 |