CN114046896A - Temperature sampling circuit of multiple cascade mode - Google Patents
Temperature sampling circuit of multiple cascade mode Download PDFInfo
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- CN114046896A CN114046896A CN202210035304.6A CN202210035304A CN114046896A CN 114046896 A CN114046896 A CN 114046896A CN 202210035304 A CN202210035304 A CN 202210035304A CN 114046896 A CN114046896 A CN 114046896A
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- G01—MEASURING; TESTING
- G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
- G01K7/00—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements
- G01K7/16—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements
- G01K7/22—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements the element being a non-linear resistance, e.g. thermistor
- G01K7/24—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements the element being a non-linear resistance, e.g. thermistor in a specially-adapted circuit, e.g. bridge circuit
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Abstract
The invention provides a temperature sampling circuit in a multi-cascade mode, wherein each slave single board is directly or indirectly connected to an input pin of a master single board; wherein, at least two slave single boards are connected with an input pin of the master single board after being cascaded; each first thermosensitive unit in the slave single board is connected to an input pin corresponding to the first MCU; the output end of the first MCU is used as the output end of the slave single board; in the main veneer: the input pin of the second MCU is used as the input pin of the main single board, the output end of the second MCU is connected with the input end of the isolation optocoupler, and the output end of the isolation optocoupler is used as the output end of the main single board; therefore, the main single board and the slave single board need to adopt the MCU with fewer pins, and the cost is reduced; meanwhile, only one output line is arranged for each slave single board, so that the problem that more connectors and wire harnesses are needed when the number of the slave single boards is more than 2 is solved; meanwhile, the structure is small in size, convenient to wire and beneficial to expansion.
Description
Technical Field
The invention belongs to the technical field of temperature sampling, and particularly relates to a temperature sampling circuit in a multi-cascade mode.
Background
With the development of the fields of wind power generation, photovoltaic power generation, energy storage and the like, a plurality of single-machine high-power converters are produced, three-level multi-parallel power units are continuously developed, the Temperature of NTC (Negative Temperature CoeffiCient) needing to be sampled is increased, the existing scheme generally selects MCU (micro controller Unit) which only performs over-Temperature protection or uses more pin resources to sample NTC Temperature, but the positions of the NTC of the modules are distributed on different slave single plates, and the extension of multi-channel sampling is not facilitated.
The prior art generally adopts the structure shown in fig. 1, but the prior art needs more pin resource controllers and is high in price; when the number of the slave single boards is more than 2, more connectors and wire harnesses are needed; meanwhile, the structure is large in size, inconvenient in wiring and not beneficial to expansion.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a multi-cascade temperature sampling circuit, which is used to reduce the cost by using MCUs with fewer pins in a master board and a slave board.
The application discloses temperature sampling circuit of many cascade ways includes: a plurality of slave single boards and a master single board;
each slave single board is directly or indirectly connected to an input pin of the master single board; wherein, at least two slave single boards are connected with an input pin of the master single board after being cascaded;
the slave veneer comprises: at least two first temperature sensing units and a first microcontroller MCU; each first thermosensitive unit is connected to an input pin corresponding to the first MCU; the output end of the first MCU is used as the output end of the slave single board;
the main veneer includes: the second MCU and the isolation optocoupler are arranged; and the input pin of the second MCU is used as the input pin of the main single board, the output end of the second MCU is connected with the input end of the isolation optocoupler, and the output end of the isolation optocoupler is used as the output end of the main single board.
Optionally, in the temperature sampling circuit in the multiple cascade mode, each slave board is connected to one input pin of the master board after being cascaded.
Optionally, in the temperature sampling circuit in the multiple cascade mode, each slave board is cascaded according to a principle that a position of the slave board is close to the slave board.
Optionally, in the temperature sampling circuit of the multiple cascade system, the first thermosensitive unit includes: at least one resistor and at least one thermistor;
and after being connected in series with the thermistors, the resistors are arranged between a power supply and the ground.
Optionally, in the multi-cascade temperature sampling circuit, the number of the resistors is 1, and the number of the thermistors is 1;
and a connection point between the thermistor and the resistor serves as an output end of the first thermosensitive unit.
Optionally, in the temperature sampling circuit in the multiple cascade mode, one end of the resistor is connected to the power supply, and the other end of the resistor is connected to one end of the thermistor; the other end of the thermistor is grounded.
Optionally, in the temperature sampling circuit in the multiple cascade mode, one end of the resistor is grounded, and the other end of the resistor is connected to one end of the thermistor; the other end of the thermistor is connected with the power supply.
Optionally, in the temperature sampling circuit in the multiple cascade mode, the other input pin of the second MCU is further connected to at least two second thermal sensitive units.
Optionally, in the temperature sampling circuit in the multiple cascade connection mode, each thermosensitive unit corresponds to an input pin of a corresponding MCU one to one.
Optionally, in the temperature sampling circuit in the multiple cascade mode, one of the temperature data collected from the single board is a path of sampled temperature data;
and each slave veneer is sequentially transmitted to the next stage according to the corresponding connection relation until the last stage of transmission finishes all temperatures.
As can be seen from the above technical solutions, the present invention provides a temperature sampling circuit in a multiple cascade mode, wherein: each slave single board is directly or indirectly connected to an input pin of the master single board; wherein, at least two slave single boards are connected with an input pin of the master single board after being cascaded; the slave veneer comprises: at least two first temperature sensing units and a first microcontroller MCU; each first thermosensitive unit is connected to a corresponding pin of the first MCU; the output end of the first MCU is used as the output end of the slave single board; the main veneer includes: the second MCU and the isolation optocoupler are arranged; an input pin of the second MCU is used as an input pin of the main single board, an output end of the second MCU is connected with an input end of the isolation optocoupler, and an output end of the isolation optocoupler is used as an output end of the main single board; therefore, the main single board and the slave single board need to adopt the MCU with fewer pins, and the cost is reduced; meanwhile, only one output line is arranged for each slave single board, so that the problem that more connectors and wire harnesses are needed when the number of the slave single boards is more than 2 is solved; meanwhile, the structure is small in size, convenient to wire and beneficial to expansion.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of a temperature sampling circuit in a multi-cascade manner according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another temperature sampling circuit in a multi-cascade manner according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another temperature sampling circuit in a multi-cascade manner according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of another temperature sampling circuit in a multi-cascade manner according to an embodiment of the present invention;
fig. 5 is a timing diagram illustrating sampling in another temperature sampling circuit in a multiple cascade mode according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In this application, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The technical terms used in the present application are to be interpreted as:
NTC Temperature (Negative Temperature CoeffiCient); refers to the phenomenon and materials of thermistors with negative temperature coefficients, with the resistance decreasing exponentially with temperature rise. The material is a semiconductor ceramic which is prepared by fully mixing, molding, sintering and other processes of two or more than two metal oxides of manganese, copper, silicon, cobalt, iron, nickel, zinc and the like, and can be prepared into a thermistor with a Negative Temperature Coefficient (NTC). The resistivity and material constant of the material vary with the material composition ratio, sintering atmosphere, sintering temperature and structural state. Non-oxide NTC thermistor materials typified by silicon carbide, tin selenide, tantalum nitride, and the like have also been developed.
MCU: (Microcontroller Unit, Microcontroller); the system is also called a Single Chip Microcomputer (Microcomputer) or a Single Chip Microcomputer, and is characterized in that the frequency and specification of a Central Processing Unit (CPU) are properly reduced, and peripheral interfaces such as a memory (memory), a counter (Timer), a USB, an a/D conversion, a UART, a PLC, a DMA and the like, even an LCD driving circuit are integrated on a Single Chip to form a Chip-level computer, so that different combination control is performed for different application occasions. Such as mobile phones, PC peripherals, remote controls, automotive electronics, industrial stepper motors, robotic arm controls, etc., can see the silhouette of the MCU.
IGBT: (Insulated Gate Bipolar Transistor); the composite full-control voltage-driven power semiconductor device is a composite full-control voltage-driven power semiconductor device consisting of a BJT (bipolar junction transistor) and an MOS (insulated gate field effect transistor), and has the advantages of both high input impedance of the MOSFET and low conduction voltage drop of the GTR. The GTR saturation voltage is reduced, the current carrying density is high, but the driving current is large; the MOSFET has small driving power, high switching speed, large conduction voltage drop and small current carrying density. The IGBT integrates the advantages of the two devices, and has small driving power and reduced saturation voltage. The method is very suitable for being applied to the fields of current transformation systems with direct-current voltage of 600V or more, such as alternating-current motors, frequency converters, switching power supplies, lighting circuits, traction transmission and the like.
The IGBT module is a modularized semiconductor product formed by bridge packaging of an IGBT (insulated gate bipolar transistor chip) and an FWD (diode chip) through a specific circuit; the packaged IGBT module is directly applied to equipment such as a frequency converter, a UPS (uninterrupted power supply) and the like; the IGBT module has the characteristics of energy conservation, convenience in installation and maintenance, stable heat dissipation and the like; most of the current market products are such modular products, generally, the IGBT is also referred to as IGBT module; with the promotion of concepts of energy conservation, environmental protection and the like, the products are more and more seen in the market.
The embodiment of the application provides a temperature sampling circuit in a multi-cascade mode, which is used for solving the problems that the structure shown in figure 1 is adopted in the prior art, but more pin resource controllers are needed, and the price is high; when the number of the slave single boards is more than 2, more connectors and wire harnesses are needed; meanwhile, the structure is large in size, inconvenient in wiring and not beneficial to expansion.
Referring to fig. 1, the multi-cascade temperature sampling circuit includes: a plurality of slave single boards and a master single board.
Each slave single board is directly or indirectly connected to an input pin of the master single board. Wherein, at least two slave single boards are connected with one input pin of the master single board after being cascaded.
That is, there is at least two slave boards sharing the input pin of one master board. The sharing mode is that one end after the cascade connection is used as a total output end.
The connection relationship between the slave boards may be the structure shown in fig. 1 or the structure shown in fig. 2, which is not described herein again, and is determined according to the actual situation, and is within the protection scope of the present application.
It should be noted that there may be multiple sets of cascades; that is, the first group: at least two slave single boards are connected with one input pin of the master single board after being cascaded; second group: there is another at least two slave single boards connected with another input pin of the master single board after being cascaded.
The other numbers are not described in detail here, and are within the scope of the present application depending on the actual situation.
The slave veneer comprises: at least two first temperature sensing units and a first microcontroller MCU; each first thermosensitive unit is connected to an input pin corresponding to the first MCU; and the output end of the first MCU is used as the output end of the slave single board.
Specifically, the output end of a first thermosensitive unit is connected with a first input pin of a first MCU; and the output end of the other first thermosensitive unit is connected with the second input pin of the first MCU.
It should be noted that, for the sake of distinction, the slave board is divided into a first slave board and other second slave boards. If other second slave single boards are connected to the main single board through the first slave single board; the first MCU in the first master single board is also provided with a pin connected with the corresponding second slave single board.
That is to say, the number of the specific pins in the MCU may be determined according to actual situations, and is not described herein any more, and is within the protection scope of the present application.
It should be noted that each MCU may have the same type, or certainly may have different types, and the type of each MCU is not specifically limited herein, and is within the protection scope of the present application.
The main veneer includes: the second MCU and the isolation optocoupler are arranged; and the input pin of the second MCU is used as the input pin of the main single board, the output end of the second MCU is connected with the input end of the isolation optocoupler, and the output end of the isolation optocoupler is used as the output end of the main single board.
It should be noted that the second MCU also has a plurality of input pins, and each input pin of the second MCU can be used as an input pin of the main board.
It should be noted that, an input pin of the second MCU has a direct connection relationship with an output terminal of a slave board only.
If two slave single boards are connected with one input pin of the master single board after being cascaded. Specifically, the output end of the first slave single board is connected with one end of the input end of the second slave single board; the output end of the second slave single board is connected with one input pin of the second MCU.
The output pin of the second MCU in the main single board inputs signals to the isolation optocoupler, the input side of the isolation optocoupler is a light emitting diode (namely, the input end on the left side), the output side of the isolation optocoupler is a phototriode (namely, the output end on the right side), and the phototriode converts optical signals into electric signals and outputs the electric signals to the control panel.
It should be noted that, the topology of the high-power converter system is changed from two levels to three levels, the number of the IGBT modules is increased to three times of the original number, NTC resistance sampling inside a plurality of modules is realized, the module junction temperature can be monitored more accurately, and the system reliability is improved.
In this embodiment, each slave board is directly or indirectly connected to an input pin of the master board; wherein, at least two slave single boards are connected with an input pin of the master single board after being cascaded; the slave veneer comprises: at least two first temperature sensing units and a first microcontroller MCU; each first thermosensitive unit is connected to a corresponding pin of the first MCU; the output end of the first MCU is used as the output end of the slave single board; the main veneer includes: the second MCU and the isolation optocoupler are arranged; an input pin of the second MCU is used as an input pin of the main single board, an output end of the second MCU is connected with an input end of the isolation optocoupler, and an output end of the isolation optocoupler is used as an output end of the main single board; therefore, the main single board and the slave single board need to adopt the MCU with fewer pins, and the cost is reduced; meanwhile, only one output line is arranged for each slave single board, so that the problem that more connectors and wire harnesses are needed when the number of the slave single boards is more than 2 is solved; meanwhile, the structure is small in size, convenient to wire and beneficial to expansion.
In practical application, as shown in fig. 1, each slave board is connected to one input pin of the master board after being cascaded.
Specifically, if the number of slave boards is N, the output terminal Tx of the first slave board is connected to the input pin Rx of the second slave board; the output terminal Tx of the second slave single board is connected to the input pin Rx of the third slave single board; by analogy, the output terminal Tx of the nth-1 slave board is connected with the input pin Rx of the nth slave board; the output terminal Tx of the nth slave board is connected to an input pin Rx of the master board.
It should be noted that fig. 4 shows 1 slave board as an example, and the number of slave boards is a structural schematic diagram of other numbers, which is not described herein any more, and is only required depending on actual situations, and is within the protection scope of the present application.
In this embodiment, the MCU is disposed on different boards, and samples the NTC temperature value in the board, so that only one signal line is needed to output all NTC sampling signals.
In practical application, each slave single board is cascaded according to the position and the principle of proximity.
It should be noted that, the use of the proximity principle can be used to save the material of the connection line, if the proximity principle is not used, the use of the connection line may reach the first length, and if the proximity principle is used, the use of the connection line reaches the second length, and the first length is greater than the second length.
The specific connection relationship of each veneer is not described herein any more, and it is only necessary to ensure that the final connecting line material is minimum, all within the protection scope of the present application.
In practical applications, the first thermosensitive unit includes: at least one resistor and at least one thermistor.
And after being connected in series with the thermistors, the resistors are arranged between a power supply and the ground.
As shown in fig. 3 and 4, VDD is the power supply; NTC 1, NTC 2, NTC n1, NTC n2, NTC m1, and NTC m2 are all thermistors.
Specifically, the resistors, that is, the common resistors, may be arranged adjacently, and the thermistors may be arranged adjacently.
Certainly, the manner of interval arrangement is not excluded, and the description is omitted here, which is determined according to the actual situation and is within the protection scope of the present application.
In practical application, the number of the resistors is 1, and the number of the thermistors is 1.
Of course, the situation that the number of the resistors is other numbers is not excluded, and the description is omitted here, and the resistors are within the protection scope of the present application depending on the actual situation.
The situation that the number of the thermistors is other numbers is not excluded, and the thermistors are not repeated in detail herein, and are within the protection scope of the present application depending on the actual situation.
And a connection point between the thermistor and the resistor serves as an output end of the first thermosensitive unit.
That is, the voltage at the connection point between the thermistor and the resistor can reflect the current ambient temperature condition of the single board.
The arrangement positions of the thermistor and the resistor are not particularly limited, and may be determined as the case may be, and are within the scope of the application.
Two setting positions are explained below:
(1) one end of the resistor is connected with the power supply, and the other end of the resistor is connected with one end of the thermistor; the other end of the thermistor is grounded.
Note that a connection point between the thermistor and the resistor serves as an output terminal of the first thermosensitive unit.
That is, the voltage at the connection point between the thermistor and the resistor can reflect the current ambient temperature condition of the single board.
(2) One end of the resistor is grounded, and the other end of the resistor is connected with one end of the thermistor; the other end of the thermistor is connected with the power supply.
Note that a connection point between the thermistor and the resistor serves as an output terminal of the first thermosensitive unit.
That is, the voltage at the connection point between the thermistor and the resistor can reflect the current ambient temperature condition of the single board.
It should be noted that, when the number of the resistors and the thermistors is other numbers, the specific arrangement positions thereof are similar to the two manners illustrated above, and are not described herein any more, and all of them are within the protection scope of the present application depending on the actual situation.
The thermistor can be an NTC resistor or a PCT resistor; the drawings show the NCT resistor as an example, and when the thermistor is a PCT resistor, the descriptions are similar to the above descriptions, and are not repeated here, and all are within the protection scope of the present application depending on the actual situation.
In practical application, as shown in fig. 2, at least two second thermal units are connected to the other input pins of the second MCU.
Specifically, the output end of a second thermosensitive unit is connected with one input end of a second MCU; and the output end of the other second thermosensitive unit is connected with the other input end of the second MCU.
In practical applications, the second thermosensitive unit includes: at least one resistor and at least one thermistor.
And after being connected with the thermistor in series, the resistors are arranged between a power supply and the ground.
Specifically, the resistors, that is, the common resistors, may be arranged adjacently, and the thermistors may be arranged adjacently.
Certainly, the manner of interval arrangement is not excluded, and the description is omitted here, which is determined according to the actual situation and is within the protection scope of the present application.
In practical application, the number of the resistors is 1, and the number of the thermistors is 1.
Of course, the situation that the number of the resistors is other numbers is not excluded, and the description is omitted here, and the resistors are within the protection scope of the present application depending on the actual situation.
The situation that the number of the thermistors is other numbers is not excluded, and the thermistors are not repeated in detail herein, and are within the protection scope of the present application depending on the actual situation.
And a connection point between the thermistor and the resistor serves as an output end of the second thermosensitive unit.
That is, the voltage at the connection point between the thermistor and the resistor can reflect the current ambient temperature condition of the single board.
The arrangement positions of the thermistor and the resistor are not particularly limited, and may be determined as the case may be, and are within the scope of the application.
Two setting positions are explained below:
(1) one end of the resistor is connected with the power supply, and the other end of the resistor is connected with the thermistor; the other end of the thermistor is grounded.
Note that a connection point between the thermistor and the resistor serves as an output terminal of the second thermosensitive unit.
That is, the voltage at the connection point between the thermistor and the resistor can reflect the current ambient temperature condition of the single board.
(2) One end of the resistor is grounded, and the other end of the resistor is connected with the thermistor; the other end of the thermistor is connected with the power supply.
Note that a connection point between the thermistor and the resistor serves as an output terminal of the second thermosensitive unit.
That is, the voltage at the connection point between the thermistor and the resistor can reflect the current ambient temperature condition of the single board.
It should be noted that, when the number of the resistors and the thermistors is other numbers, the specific arrangement positions thereof are similar to the two manners illustrated above, and are not described herein any more, and all of them are within the protection scope of the present application depending on the actual situation.
The thermistor can be an NTC resistor or a PCT resistor; the drawings show the NCT resistor as an example, and when the thermistor is a PCT resistor, the descriptions are similar to the above descriptions, and are not repeated here, and all are within the protection scope of the present application depending on the actual situation.
Each thermosensitive unit is in one-to-one correspondence with the input pins of the corresponding MCU.
In practical application, one of the temperature data collected from the single board is a path of sampling temperature data;
and each slave veneer is sequentially transmitted to the next stage according to the corresponding connection relation until the last stage of transmission finishes all temperatures.
It should be noted that, as shown in fig. 5, the signal outgoing timing sequence starts with the output of the temperature signal at the beginning, and as shown in fig. 2, a single board 1 samples NTC 1 and NTC 2 as the first path of sampling temperature data, and all sampling temperatures on the single board are transmitted in sequence; and the next stage of sampling temperature data is continuously transmitted to the next stage by following the previous stage until the last stage of transmission finishes all temperatures.
As shown in fig. 5, "ID: n2 "indicates the nth stage, way 2, and so on. The details are not repeated here and are within the scope of the present application.
Features described in the embodiments in the present specification may be replaced with or combined with each other, and the same and similar portions among the embodiments may be referred to each other, and each embodiment is described with emphasis on differences from other embodiments. In particular, the system or system embodiments are substantially similar to the method embodiments and therefore are described in a relatively simple manner, and reference may be made to some of the descriptions of the method embodiments for related points. The above-described system and system embodiments are only illustrative, wherein the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A temperature sampling circuit of a multi-cascade mode is characterized by comprising: a plurality of slave single boards and a master single board;
each slave single board is directly or indirectly connected to an input pin of the master single board; wherein, at least two slave single boards are connected with an input pin of the master single board after being cascaded;
the slave veneer comprises: at least two first temperature sensing units and a first microcontroller MCU; each first thermosensitive unit is connected to an input pin corresponding to the first MCU; the output end of the first MCU is used as the output end of the slave single board;
the main veneer includes: the second MCU and the isolation optocoupler are arranged; and the input pin of the second MCU is used as the input pin of the main single board, the output end of the second MCU is connected with the input end of the isolation optocoupler, and the output end of the isolation optocoupler is used as the output end of the main single board.
2. The multi-cascade temperature sampling circuit according to claim 1, wherein each of the slave boards is connected to one input pin of the master board after being cascaded.
3. The multi-cascade temperature sampling circuit according to claim 2, wherein each slave board is cascaded according to its position and proximity.
4. The multi-cascade temperature sampling circuit according to claim 2, wherein the first temperature sensing unit includes: at least one resistor and at least one thermistor;
and after being connected in series with the thermistors, the resistors are arranged between a power supply and the ground.
5. The multi-cascade temperature sampling circuit according to claim 4, wherein the number of the resistors is 1, and the number of the thermistors is 1;
and a connection point between the thermistor and the resistor serves as an output end of the first thermosensitive unit.
6. The multi-cascade temperature sampling circuit according to claim 5, wherein one end of the resistor is connected to the power supply, and the other end of the resistor is connected to one end of the thermistor; the other end of the thermistor is grounded.
7. The multi-cascade temperature sampling circuit according to claim 5, wherein one end of the resistor is grounded, and the other end of the resistor is connected to one end of the thermistor; the other end of the thermistor is connected with the power supply.
8. The multi-cascade temperature sampling circuit according to claim 1, wherein at least two second thermal cells are connected to the other input pins of the second MCU.
9. The multiple cascade mode temperature sampling circuit of any one of claims 1 to 8, wherein each temperature sensing unit is in one-to-one correspondence with an input pin of a corresponding MCU.
10. The multiple cascade mode temperature sampling circuit according to any one of claims 1 to 8, wherein one of the temperature data collected from the single board is a path of sampled temperature data;
and each slave veneer is sequentially transmitted to the next stage according to the corresponding connection relation until the last stage of transmission finishes all temperatures.
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| CN202210035304.6A CN114046896A (en) | 2022-01-13 | 2022-01-13 | Temperature sampling circuit of multiple cascade mode |
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Citations (9)
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