CN114038023A - Fingerprint identification device and fingerprint identification method - Google Patents

Abstract

The embodiment of the disclosure discloses a fingerprint identification device and a fingerprint identification method, wherein an acquisition unit and a comparison unit are arranged on a liner, a storage capacitor of a first column of acquisition units is configured to be a reference capacitor with a fixed capacitance value, and storage capacitors of the other column of acquisition units are configured to be acquisition capacitors with a variable capacitance value when a finger presses; therefore, the comparison unit can output a first comparison level when the capacitance value of the electrically connected acquisition capacitor is the same as that of the reference capacitor, and output a second comparison level when the capacitance value of the electrically connected acquisition capacitor is larger than that of the reference capacitor. Therefore, the binary numerical value of the fingerprint can be directly output through a hardware circuit, so that the binary image of the fingerprint can be directly obtained through the binary numerical value, and the power consumption of fingerprint detection is reduced.

Description

Fingerprint identification device and fingerprint identification method

Technical Field

The present disclosure relates to the field of fingerprint detection technologies, and in particular, to a fingerprint identification apparatus and a fingerprint identification method.

Background

With the rapid development of technology, mobile products with biometric identification function gradually come into the lives of people. The fingerprint is a characteristic which is unique and unique to the human body and distinguishable from other people, and is composed of a series of valleys and ridges on the surface of the skin at the finger tip, the composition details of which usually include the branches of the ridges, the ends of the ridges, the arches, the tent-like arches, the left-handed, right-handed, spiral, or double-handed details, which determine the unique characteristics of the fingerprint and therefore have received much attention.

Disclosure of Invention

The fingerprint identification device and the fingerprint identification method are used for reducing the calculation amount of fingerprint detection.

The disclosed embodiment provides a fingerprint identification device, including:

a substrate base plate;

the plurality of acquisition units are arranged on the substrate in an array manner; wherein, the collection unit includes: a storage capacitor; the storage capacitors of the first column acquisition units are configured as reference capacitors with fixed capacitance values, and the storage capacitors of the rest of the column acquisition units are configured as acquisition capacitors with variable capacitance values when pressed by fingers;

a plurality of comparison units on the substrate base plate; one comparison unit is electrically connected with the first electrode plate of the storage capacitor in one row of acquisition units; and the comparison unit is configured to: and outputting a first comparison level when the capacitance value of the electrically connected acquisition capacitor is the same as the capacitance value of the reference capacitor, and outputting a second comparison level when the capacitance value of the connected acquisition capacitor is larger than the capacitance value of the reference capacitor.

In some examples, the acquisition unit further comprises: a first control circuit and a second control circuit;

the first control circuit is configured to switch on and off a first reference voltage terminal and a second electrode plate of the storage capacitor in response to a signal of a first control terminal;

the second control circuit is configured to turn on and off a second reference voltage terminal with a second electrode plate of the storage capacitor in response to a signal of a second control terminal.

In some examples, the first control circuit includes: a first transistor;

the gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the first reference voltage terminal, and the second electrode of the first transistor is electrically connected to the second electrode plate of the storage capacitor.

In some examples, the second control circuit includes: a second transistor;

the grid electrode of the second transistor is electrically connected with the second control end, the first electrode of the second transistor is electrically connected with the second reference voltage end, and the second electrode of the second transistor is electrically connected with the second electrode plate of the storage capacitor.

In some examples, the fingerprint recognition device further includes:

a plurality of first control lines; one first control line is electrically connected with the first control ends corresponding to the first control circuits of the acquisition units in one row;

a plurality of second control lines; one second control line is electrically connected with second control ends corresponding to second control circuits of one row of the acquisition units;

a plurality of collection lines; and the first electrode plates of the storage capacitors in one row of acquisition units are electrically connected with the corresponding comparison unit through one acquisition line.

In some examples, the comparison unit includes; a comparator and a control switch;

the control end of the control switch is electrically connected with the acquisition control end, the first end of the control switch is electrically connected with the reference voltage end, and the second end of the control switch is electrically connected with the negative phase input end of the comparator;

a non-inverting input terminal of the comparator is electrically connected to the reference voltage terminal, and an output terminal of the comparator is configured to output the first comparison level and the second comparison level.

In some examples, the fingerprint recognition device further includes: a data processing unit;

the data processing unit is electrically connected with the plurality of comparison units respectively; the data processing unit is configured to receive the first comparison level and the second comparison level output by the comparison unit, generate a binary image according to the received first comparison level and second comparison level, and perform fingerprint recognition according to the generated binary image.

The embodiment of the present disclosure further provides a fingerprint identification method of a fingerprint identification apparatus, including:

the output capacitance value of the acquisition capacitor connected with the same comparison unit is controlled in a time-sharing manner, and the output capacitance value of the reference capacitor connected with the same comparison unit is controlled when the capacitance value of the acquisition capacitor is output; and a first comparison level is output when the capacitance value of the acquisition capacitor electrically connected with the same comparison unit is the same as the capacitance value of the reference capacitor; when the capacitance value of the acquisition capacitor connected with the same comparison unit is larger than that of the reference capacitor, outputting a second comparison level;

generating a binary image according to the first comparison level and the second comparison level;

and performing fingerprint identification according to the generated binary image.

In some examples, the time-sharing control is performed on an output capacitance value of a collecting capacitor connected with the same comparison unit, and when the output capacitance value of the collecting capacitor is larger than the output capacitance value of a reference capacitor connected with the same comparison unit, the output capacitance value of the reference capacitor connected with the same comparison unit is controlled; the method comprises the following steps:

dividing one frame of acquisition time into a plurality of acquisition stages; wherein, a row of acquisition units with the acquisition capacitor corresponds to an acquisition stage; the acquisition stage comprises a first sub-acquisition stage and a second sub-acquisition stage;

in the first sub-acquisition stage, loading a signal of a first level to an acquisition control end of a control switch in each comparison unit, loading a signal of a first level to a first control line connected with the first row of acquisition units, loading a signal of a second level to a second control line connected with the first row of acquisition units, loading a signal of a first level to a first control line electrically connected with the acquisition unit corresponding to the acquisition stage, and loading a signal of a second level to a second control line electrically connected with the acquisition unit corresponding to the acquisition stage;

in the second sub-acquisition stage, a signal of a second level is loaded to an acquisition control end of a control switch in each comparison unit, a signal of a second level is loaded to a first control line connected to the first row of acquisition units, a signal of a first level is loaded to a second control line connected to the first row of acquisition units, a signal of a second level is loaded to a first control line electrically connected to the acquisition unit corresponding to the acquisition stage, and a signal of a second level is loaded to a second control line electrically connected to the acquisition unit corresponding to the acquisition stage.

In some examples, the fingerprinting from the generated binary image includes:

and according to the generated binary image, sequentially performing feature extraction and feature comparison to determine the information of the valleys and ridges of the fingerprint.

The beneficial effects of the disclosed embodiment are as follows:

the fingerprint identification device and the fingerprint identification method provided by the disclosure are characterized in that the acquisition units and the comparison units are arranged on the liner, the storage capacitors of the acquisition units in the first column are configured to be reference capacitors with fixed capacitance values, and the storage capacitors of the acquisition units in the other columns are configured to be acquisition capacitors with variable capacitance values when a finger presses; therefore, the comparison unit can output a first comparison level when the capacitance value of the electrically connected acquisition capacitor is the same as that of the reference capacitor, and output a second comparison level when the capacitance value of the electrically connected acquisition capacitor is larger than that of the reference capacitor. Therefore, the binary numerical value of the fingerprint can be directly output through a hardware circuit, so that the binary image of the fingerprint can be directly obtained through the binary numerical value, and the power consumption of fingerprint detection is reduced. And the flow of fingerprint identification can be more concise, and a binary image can be generated without additionally setting a large amount of programming codes, so that the situations of excessive image processing and insufficient image processing can be avoided, and the accuracy of fingerprint detection is improved.

Drawings

FIG. 1 is a schematic diagram of a fingerprint identification device according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a specific structure of a fingerprint identification device according to an embodiment of the present disclosure;

FIG. 3 is a flow chart of a fingerprint identification method in an embodiment of the present disclosure;

fig. 4 is a signal timing diagram in an embodiment of the disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. And the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the sizes and shapes of the various figures in the drawings are not to scale, but are merely intended to illustrate the present disclosure. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

Fingerprint identification technology is the most common identity authentication mode in modern society, and the social value of the technology is very high. The capacitive fingerprint identification technology is one of the mainstream fingerprint identification technologies at present. When a finger touches the capacitive fingerprint identification device, the finger can be used as a polar plate of the capacitor, and because the distances between the upper valley and the ridge of the finger and the substrate of the storage capacitor in the capacitive fingerprint identification device are unequal, the capacitance values of the storage capacitor in the capacitive fingerprint identification device are also different. In general, in fingerprint recognition, a grayscale image of a fingerprint is acquired by a hardware device such as a capacitive fingerprint recognition device, and then a binary image of the fingerprint image is obtained by performing image binarization processing after performing image segmentation, image enhancement, and other processing on the grayscale image. And then, according to the obtained binary image, performing feature extraction and feature comparison to complete the fingerprint identification process. However, the processing procedures such as image segmentation and image enhancement on the grayscale image need to be performed in a software platform, which not only needs a large amount of programming codes to perform calculation and verification, but also is very easy to cause the situations of image over-processing and image under-processing, so that the situations of fingerprint non-recognition and fingerprint false recognition occur.

The fingerprint identification apparatus provided in the embodiment of the present disclosure, as shown in fig. 1, may include:

a base substrate 100;

a plurality of collection units 110 arranged in an array on the substrate base plate 100; wherein, the collection unit 110 includes: a storage capacitor; also, the storage capacitance of the first column acquisition unit 110 is configured as a reference capacitance having a fixed capacitance value, and the storage capacitances of the remaining column acquisition units 110 are configured as acquisition capacitances that change the capacitance value when pressed by a finger;

a plurality of comparison units 120 on the substrate base plate 100; one comparing unit 120 is electrically connected to the first electrode plate of the storage capacitor in one row of the collecting units 110; and, the comparing unit 120 is configured to: and outputting a first comparison level when the capacitance value of the electrically connected acquisition capacitor is the same as the capacitance value of the reference capacitor, and outputting a second comparison level when the capacitance value of the connected acquisition capacitor is larger than the capacitance value of the reference capacitor.

The fingerprint identification device provided by the embodiment of the disclosure is characterized in that the acquisition units and the comparison unit are arranged on the liner, the storage capacitors of the acquisition units in the first column are configured to be reference capacitors with fixed capacitance values, and the storage capacitors of the acquisition units in the other columns are configured to be acquisition capacitors with variable capacitance values when a finger presses; therefore, the comparison unit can output a first comparison level when the capacitance value of the electrically connected acquisition capacitor is the same as that of the reference capacitor, and output a second comparison level when the capacitance value of the electrically connected acquisition capacitor is larger than that of the reference capacitor. Therefore, the binary numerical value of the fingerprint can be directly output through a hardware circuit, so that the binary image of the fingerprint can be directly obtained through the binary numerical value, and the power consumption of fingerprint detection is reduced. And the flow of fingerprint identification can be more concise, and a binary image can be generated without additionally setting a large amount of programming codes, so that the situations of excessive image processing and insufficient image processing can be avoided, and the accuracy of fingerprint detection is improved.

It should be noted that, in the embodiment of the present disclosure, a column may be a practical column, and a row may be a practical row. Alternatively, the columns in the embodiments of the present disclosure may be actual rows, and the rows may be actual columns, which is not limited herein.

Illustratively, as shown in fig. 1, the storage capacitance of the first column acquisition unit 110 is configured as a reference capacitance having a fixed capacitance value. Namely, the storage capacitors C11, C21, and C31 are reference capacitors.

Illustratively, as shown in fig. 1, the storage capacitances of the remaining column acquisition units 110, except for the first column acquisition unit 110, are configured as acquisition capacitances that change capacitance values when pressed by a finger. That is, the storage capacitors C12, C22 and C32 in the second column are collecting capacitors, and the storage capacitors C13, C23 and C33 in the third column are collecting capacitors.

It should be noted that the capacitance value of each reference capacitor may be the same. The capacitance value of the reference capacitor may be determined when the fingerprint recognition device is manufactured, and the capacitance value of the reference capacitor may not be changed by the influence of the finger when the finger touches the fingerprint recognition device. For example, when the fingerprint identification device is manufactured, the shielding layer is arranged on the side, facing the finger, of the reference capacitor, so that the capacitance value of the reference capacitor is prevented from being influenced by the finger. Alternatively, other preparation means may be adopted so that the capacitance value of the reference capacitor does not change under the influence of the finger. The same as above means the same within an error tolerance.

It should be noted that, when a finger touches the fingerprint identification device, the capacitance of the collecting capacitor may be changed under the influence of the finger.

In the embodiment of the present disclosure, as shown in fig. 1, the fingerprint identification device further includes: a data processing unit 130; wherein, the data processing unit 130 is electrically connected to the plurality of comparing units 120 respectively; the data processing unit 130 is configured to receive the first and second comparison levels output by the comparison unit 120, and generate a binary image according to the received first and second comparison levels, and perform fingerprint recognition according to the generated binary image. For example, after feature extraction and feature comparison are sequentially performed according to the generated binary image, information of valleys and ridges of the fingerprint can be determined to complete fingerprint identification.

In this disclosure, as shown in fig. 1, the collecting unit 110 may further include: a first control circuit 111 and a second control circuit 112; wherein the first control circuit 111 is configured to turn on and off the first reference voltage terminal VR1 with the second electrode plate of the storage capacitor in response to a signal of the first control terminal VM 1. The second control circuit 112 is configured to turn on and off the second reference voltage terminal VR2 with the second electrode plate of the storage capacitor in response to a signal of the second control terminal VM 2.

In the embodiment of the present disclosure, as shown in fig. 2, the first control circuit 111 includes: a first transistor; the gate of the first transistor is electrically connected to the first control terminal VM1, the first pole of the first transistor is electrically connected to the first reference voltage terminal VR1, and the second pole of the first transistor is electrically connected to the second electrode plate of the storage capacitor.

In the embodiment of the present disclosure, as shown in fig. 2, the second control circuit 112 includes: a second transistor; the gate of the second transistor is electrically connected to the second control terminal VM2, the first pole of the second transistor is electrically connected to the second reference voltage terminal VR2, and the second pole of the second transistor is electrically connected to the second electrode plate of the storage capacitor.

In the embodiments of the present disclosure, in order to reduce the manufacturing process, as shown in fig. 2, the first transistor and the second transistor may be N-type transistors. The N-type transistor is turned on by a high level and turned off by a low level.

In the embodiments of the present disclosure, in order to reduce the manufacturing process, the first transistor and the second transistor may also be P-type transistors. The P-type transistor is turned off by a high level and turned on by a low level.

In the embodiment of the present disclosure, the first Transistor and the second Transistor may be Thin Film Transistors (TFTs) or Metal Oxide semiconductor field effect transistors (MOS), and are not limited herein. In a specific implementation, the first pole of the transistors may be a source and the second pole may be a drain, or the first pole may be a drain and the second pole may be a source, which are not specifically distinguished herein.

In the embodiment of the present disclosure, as shown in fig. 2, the comparing unit 120 may include; a comparator and a control switch; the control end of the control switch is electrically connected with the acquisition control end, the first end of the control switch is electrically connected with the reference voltage end VG, and the second end of the control switch is electrically connected with the negative phase input end of the comparator. The non-inverting input terminal of the comparator is electrically connected to the reference voltage terminal VG, and the output terminal of the comparator is configured to output a first comparison level and a second comparison level.

Illustratively, when the voltage of the positive phase input terminal and the voltage of the negative phase input terminal of the comparator are equal, the comparator outputs "0" as the first comparison level. When the voltage of the negative phase input terminal of the comparator is greater than the voltage of the positive phase input terminal, the comparator outputs "1" as a second comparison level.

In the embodiment of the present disclosure, as shown in fig. 1 and fig. 2, the fingerprint identification device may further include: a plurality of first control lines; one of the first control lines is electrically connected to the first control terminal VM1 corresponding to the first control circuit 111 of one column of the acquisition units 110. Illustratively, one first control line is electrically connected to the gates of the first transistors of a column of acquisition units 110.

In the embodiment of the present disclosure, as shown in fig. 1 and fig. 2, the fingerprint identification device may further include: a plurality of second control lines; one of the second control lines is electrically connected to the second control terminal VM2 corresponding to the second control circuit 112 of one column of the acquisition units 110. Illustratively, a second control line is electrically connected to the gates of the second transistors of a column of acquisition units 110.

In the embodiment of the present disclosure, as shown in fig. 1 and fig. 2, the fingerprint identification device may further include: a plurality of collection lines; the first electrode plates of the storage capacitors in one row of the acquisition units 110 are electrically connected to the corresponding comparison unit 120 through one acquisition line. Illustratively, the first electrode plate of the storage capacitor in one row of the acquisition units 110 is electrically connected to the negative input terminal of the comparator in the corresponding comparison unit 120 through one acquisition line.

Exemplarily, as shown in fig. 2, only a3 × 3 array of acquisition units 110 is taken as an example. In practical applications, the number of the acquisition units 110 may be determined according to requirements of practical applications, and is not limited herein.

The first column and first row acquisition unit 110 includes: a storage capacitor C11, a first transistor MA11, and a second transistor MB 11. The first column and second row acquisition unit 110 has: a storage capacitor C21, a first transistor MA21, and a second transistor MB 21. The first column and third row acquisition unit 110 has: a storage capacitor C31, a first transistor MA31, and a second transistor MB 31.

The second column first row acquisition unit 110 has: a storage capacitor C12, a first transistor MA12, and a second transistor MB 12. The second column and second row acquisition unit 110 has: a storage capacitor C22, a first transistor MA22, and a second transistor MB 22. The second column and third row acquisition units 110 have: a storage capacitor C32, a first transistor MA32, and a second transistor MB 32.

The third column, first row acquisition unit 110 has: a storage capacitor C13, a first transistor MA13, and a second transistor MB 13. The third column and second row acquisition unit 110 has: a storage capacitor C23, a first transistor MA23, and a second transistor MB 23. Third column the third row acquisition unit 110 has: a storage capacitor C33, a first transistor MA33, and a second transistor MB 33.

The gate of the first transistor MA11, the gate of the first transistor MA21, and the gate of the first transistor MA31 are electrically connected to the first control line CA-1. The gate of the second transistor MB11, the gate of the second transistor MB21, and the gate of the second transistor MB31 are electrically connected to a second control line CB-1. The gate of the first transistor MA12, the gate of the first transistor MA22, and the gate of the first transistor MA32 are electrically connected to the first control line CA-2. The gate of the second transistor MB12, the gate of the second transistor MB22, and the gate of the second transistor MB32 are electrically connected to a second control line CB-2. The gate of the first transistor MA13, the gate of the first transistor MA23, and the gate of the first transistor MA33 are electrically connected to a first control line CA-3. The gate of the second transistor MB13, the gate of the second transistor MB23, and the gate of the second transistor MB33 are electrically connected to a second control line CB-3.

The first electrode plate of the storage capacitor C11, the first electrode plate of the storage capacitor C12, and the first electrode plate of the storage capacitor C13 are electrically connected to the inverting input terminal of the comparator VC1 via the collection line CC-1. The first electrode plate of the storage capacitor C21, the first electrode plate of the storage capacitor C22 and the first electrode plate of the storage capacitor C23 are electrically connected with the inverting input terminal of the comparator VC2 through a collecting line CC-2. The first electrode plate of the storage capacitor C31, the first electrode plate of the storage capacitor C32 and the first electrode plate of the storage capacitor C33 are electrically connected with the inverting input terminal of the comparator VC3 through a collecting line CC-3.

The inverting input terminal of the comparator VC1 is electrically connected to the reference voltage terminal VG through the control switch K1, and the control terminal of the control switch K1 is electrically connected to the acquisition control terminal VS 1. The inverting input terminal of the comparator VC2 is electrically connected to the reference voltage terminal VG through the control switch K2, and the control terminal of the control switch K2 is electrically connected to the acquisition control terminal VS 2. The inverting input terminal of the comparator VC3 is electrically connected to the reference voltage terminal VG through the control switch K3, and the control terminal of the control switch K3 is electrically connected to the acquisition control terminal VS 3. For example, the acquisition control terminal VS1, the acquisition control terminal VS2 and the acquisition control terminal VS3 may be independent signal terminals. Alternatively, the acquisition control terminal VS1, the acquisition control terminal VS2 and the acquisition control terminal VS3 may be the same signal terminal, which is not limited herein.

Illustratively, the voltage VR1 of the first reference voltage terminal VR1 may be a fixed voltage. For example, the voltage VR2 of the second reference voltage terminal VR2 may be a ground voltage of 0V. Of course, in practical applications, the voltage VR1 of the first reference voltage terminal VR1 may be determined according to requirements of practical applications, and is not limited herein.

Illustratively, the voltage VR2 of the second reference voltage terminal VR2 may be a fixed voltage, for example, the voltage VR2 of the second reference voltage terminal VR2 may be a ground voltage of 0V. Of course, in practical applications, the voltage VR2 of the second reference voltage terminal VR2 may be determined according to requirements of practical applications, and is not limited herein.

For example, the voltage vcom of the reference voltage terminal VG may be a fixed voltage, and of course, in practical applications, the voltage VG of the reference voltage terminal VG may be determined according to the requirements of practical applications, and is not limited herein.

The embodiment of the present disclosure further provides a fingerprint identification method of a fingerprint identification apparatus, as shown in fig. 3, the method may include the following steps:

s01, controlling the output capacitance value of the acquisition capacitor connected with the same comparison unit in a time-sharing manner, and controlling the output capacitance value of the reference capacitor connected with the same comparison unit when the output capacitance value of the acquisition capacitor is acquired; moreover, a first comparison level is output when the capacitance value of the acquisition capacitor electrically connected with the same comparison unit is the same as the capacitance value of the reference capacitor; outputting a second comparison level when the capacitance value of the acquisition capacitor connected with the same comparison unit is larger than that of the reference capacitor;

s02, generating a binary image according to the first comparison level and the second comparison level;

and S03, performing fingerprint identification according to the generated binary image.

In this embodiment of the present disclosure, performing fingerprint identification according to the generated binary image may include: and according to the generated binary image, sequentially performing feature extraction and feature comparison to determine the information of the valleys and ridges of the fingerprint.

In the embodiment of the present disclosure, the output capacitance values of the collection capacitors connected to the same comparison unit 120 are controlled in a time-sharing manner, and when the output capacitance values of the collection capacitors are collected, the output capacitance values of the reference capacitors connected to the same comparison unit 120 are controlled; the method comprises the following steps:

dividing one frame of acquisition time into a plurality of acquisition stages; wherein, a row of acquisition units 110 with acquisition capacitance corresponds to an acquisition phase; the acquisition stage comprises a first sub-acquisition stage and a second sub-acquisition stage;

in the first sub-acquisition stage, a signal of a first level is loaded to an acquisition control end of a control switch in each comparison unit 120, a signal of the first level is loaded to a first control line connected to the first row of acquisition units 110, a signal of a second level is loaded to a second control line connected to the first row of acquisition units 110, a signal of the first level is loaded to a first control line electrically connected to the acquisition unit 110 corresponding to the acquisition stage, and a signal of the second level is loaded to a second control line electrically connected to the acquisition unit 110 corresponding to the acquisition stage;

in the second sub-acquisition stage, a signal of the second level is loaded to the acquisition control end of the control switch in each comparison unit 120, a signal of the second level is loaded to the first control line connected to the first row of acquisition units 110, a signal of the first level is loaded to the second control line connected to the first row of acquisition units 110, a signal of the second level is loaded to the first control line electrically connected to the acquisition unit 110 corresponding to the acquisition stage, and a signal of the second level is loaded to the second control line electrically connected to the acquisition unit 110 corresponding to the acquisition stage.

In the embodiment of the present disclosure, the first level may be a high level, and the second level may be a low level. Alternatively, the first level may be a low level, and the second level may be a high level, which is not limited herein.

The operation of the fingerprint identification device provided by the embodiment of the present disclosure is described below with reference to the signal timing diagram shown in fig. 4, taking the structure of the fingerprint identification device shown in fig. 2 and vr2 being 0V as an example. It should be noted that, in the present embodiment, the disclosure is better explained, but the disclosure is not limited thereto.

As shown in fig. 4, the one-frame acquisition time F0 is divided into 2 acquisition phases T10 and T20. Wherein, the acquisition phase T10 may include: a first sub-acquisition phase T11 and a second sub-acquisition phase T12. The acquisition phase T20 may include: a first sub-acquisition phase T21 and a second sub-acquisition phase T22. The acquisition phase T10 corresponds to the second row of acquisition units 110, and the acquisition phase T20 corresponds to the third row of acquisition units 110.

Furthermore, VS1 represents the signal loaded by the acquisition control terminal VS1, VS2 represents the signal loaded by the acquisition control terminal VS2, and VS3 represents the signal loaded by the acquisition control terminal VS 3. CA-1 represents a signal transmitted on the first control line CA-1, CA-2 represents a signal transmitted on the first control line CA-2, and CA-3 represents a signal transmitted on the first control line CA-3. CB-1 represents the signal transmitted on the second control line CB-1, CB-2 represents the signal transmitted on the second control line CB-2, and CB-3 represents the signal transmitted on the second control line CB-3.

In the first sub-acquisition stage T11, vs1 controls the control switch K1 to be closed, and the voltage on the acquisition line CC-1 is the voltage vcom of the reference voltage terminal VG. The signal cb-1 may control the second transistor MB11 to turn off. The signal ca-1 may control the first transistor MA11 to be turned on to provide the voltage VR1 of the first reference voltage terminal VR1 to the second electrode plate of the storage capacitor C11. Also, the signal ca-2 may control the first transistor MA12 to turn off. The signal cb-2 may control the second transistor MB12 to be turned on to supply the 0V voltage of the second reference voltage terminal VR2 to the second electrode plate of the storage capacitor C12. And, the signal ca-3 may control the first transistor MA13 to turn off. The signal cb-3 may control the second transistor MB13 to turn off. Thus, the amount of charge Q1-1 on the collection line CC-1 satisfies the formula: q1-1 ═ c11 (vcom-vr1) + c12 ═ vcom. Where C11 represents the capacitance of the storage capacitor C11, and C12 represents the capacitance of the storage capacitor C12.

And vs2 controls control switch K2 to close, so that the voltage on collection line CC-2 is the voltage vcom of reference voltage terminal VG. The signal cb-1 may control the second transistor MB21 to turn off. The signal ca-1 may control the first transistor MA21 to be turned on to provide the voltage VR1 of the first reference voltage terminal VR1 to the second electrode plate of the storage capacitor C21. Also, the signal ca-2 may control the first transistor MA22 to turn off. The signal cb-2 may control the second transistor MB22 to be turned on to supply the 0V voltage of the second reference voltage terminal VR2 to the second electrode plate of the storage capacitor C22. And, the signal ca-3 may control the first transistor MA23 to turn off. The signal cb-3 may control the second transistor MB23 to turn off. Therefore, the amount of charge Q1-2 on the collection line CC-2 satisfies the formula: q1-2 ═ c21 (vcom-vr1) + c22 ═ vcom. Where C21 represents the capacitance of the storage capacitor C21, and C22 represents the capacitance of the storage capacitor C22.

And vs3 controls the control switch K3 to be closed, so that the voltage on the collection line CC-3 is the voltage vcom of the reference voltage end VG. The signal cb-1 may control the second transistor MB31 to turn off. The signal ca-1 may control the first transistor MA31 to be turned on to provide the voltage VR1 of the first reference voltage terminal VR1 to the second electrode plate of the storage capacitor C31. Also, the signal ca-2 may control the first transistor MA32 to turn off. The signal cb-2 may control the second transistor MB32 to be turned on to supply the 0V voltage of the second reference voltage terminal VR2 to the second electrode plate of the storage capacitor C32. And, the signal ca-3 may control the first transistor MA33 to turn off. The signal cb-3 may control the second transistor MB33 to turn off. Therefore, the amount of charge Q1-3 on the collection line CC-3 satisfies the formula: q1-3 ═ c31 (vcom-vr1) + c32 ═ vcom. Where C31 represents the capacitance of the storage capacitor C31, and C32 represents the capacitance of the storage capacitor C32.

In the second sub-acquisition phase T12, vs1 controls the control switch K1 to be turned off, and the acquisition line CC-1 is disconnected from the reference voltage terminal VG. The signal ca-1 may control the first transistor MA11 to turn off. The signal cb-1 may control the second transistor MB11 to be turned on to supply the 0V voltage of the second reference voltage terminal VR2 to the second electrode plate of the storage capacitor C11. And, the signal cb-2 may control the second transistor MB12 to turn off. The signal ca-2 may control the first transistor MA12 to be turned on to provide the voltage VR1 of the first reference voltage terminal VR1 to the second electrode plate of the storage capacitor C12. And, the signal ca-3 may control the first transistor MA13 to turn off. The signal cb-3 may control the second transistor MB13 to turn off. Thus, the amount of charge Q2-1 on the collection line CC-1 satisfies the formula: q2-1 ═ c12 (v1-vr1) + c11 ═ v 1. Where C11 represents the capacitance of the storage capacitor C11, C12 represents the capacitance of the storage capacitor C12, and v1 represents the voltage on the collection line CC-1. According to the principle of charge conservation, the amount of charge on the collection line CC-1 does not change during the first sub-collection phase T11 and the second sub-collection phase T12, and therefore Q2-1 is Q1-1. Then v1 satisfies the formula:

therefore, the voltage difference v1-vcom across the comparator VC1 is

If c12 is equal to c11, the comparator VC1 outputs "0" as the first comparison level. If, c12>c11, the comparator VC1 outputs "1" as the second comparison level.

And vs2 controls the control switch K2 to be turned off, so that the collecting line CC-2 and the reference voltage end are connectedVG turns off. The signal ca-1 may control the first transistor MA21 to turn off. The signal cb-1 may control the second transistor MB21 to be turned on to supply the 0V voltage of the second reference voltage terminal VR2 to the second electrode plate of the storage capacitor C21. And, the signal cb-2 may control the second transistor MB22 to turn off. The signal ca-2 may control the first transistor MA22 to be turned on to provide the voltage VR1 of the first reference voltage terminal VR1 to the second electrode plate of the storage capacitor C22. And, the signal ca-3 may control the first transistor MA23 to turn off. The signal cb-3 may control the second transistor MB23 to turn off. Therefore, the amount of charge Q2-2 on the collection line CC-2 satisfies the formula: q2-2 ═ c22 (v2-vr1) + c21 ═ v 2. Where C21 represents the capacitance of the storage capacitor C21, C22 represents the capacitance of the storage capacitor C22, and v2 represents the voltage on the collection line CC-2. According to the principle of charge conservation, the amount of charge on the collection line CC-2 is unchanged in the first sub-collection phase T11 and the second sub-collection phase T12, and thus Q2-2 is Q1-2. Then v2 satisfies the formula:

therefore, the voltage difference v2-vcom across the comparator VC2 is

If c22 is equal to c21, the comparator VC2 outputs "0" as the first comparison level. If, c22>c21, the comparator VC2 outputs "1" as the second comparison level.

And vs3 controls the control switch K3 to be disconnected, and the collection line CC-3 is disconnected with the reference voltage end VG. The signal ca-1 may control the first transistor MA31 to turn off. The signal cb-1 may control the second transistor MB31 to be turned on to supply the 0V voltage of the second reference voltage terminal VR2 to the second electrode plate of the storage capacitor C31. And, the signal cb-2 may control the second transistor MB32 to turn off. The signal ca-2 may control the first transistor MA32 to be turned on to provide the voltage VR1 of the first reference voltage terminal VR1 to the second electrode plate of the storage capacitor C32. And, the signal ca-3 may control the first transistor MA33 to turn off. The signal cb-3 may control the second transistor MB33 to turn off. Therefore, the amount of charge Q3-2 on the collection line CC-3 satisfies the formula: q3-2 ═ c32 (v3-vr1) + c31 ═ v 3. It is composed ofWhere C31 represents the capacitance of the storage capacitor C31, C32 represents the capacitance of the storage capacitor C32, and v3 represents the voltage on the collection line CC-3. According to the principle of charge conservation, the amount of charge on the collection line CC-3 is unchanged in the first sub-collection phase T11 and the second sub-collection phase T12, and thus Q2-3 is Q1-3. Then v3 satisfies the formula:

therefore, the voltage difference v3-vcom across the comparator VC3 is

If c32 is equal to c31, the comparator VC3 outputs "0" as the first comparison level. If, c32>c31, the comparator VC3 outputs "1" as the second comparison level.

In the first sub-acquisition stage T21, vs1 controls the control switch K1 to be closed, and the voltage on the acquisition line CC-1 is the voltage vcom of the reference voltage terminal VG. The signal cb-1 may control the second transistor MB11 to turn off. The signal ca-1 may control the first transistor MA11 to be turned on to provide the voltage VR1 of the first reference voltage terminal VR1 to the second electrode plate of the storage capacitor C11. Also, the signal ca-2 may control the first transistor MA12 to turn off. The signal cb-2 may control the second transistor MB12 to turn off. And, the signal ca-3 may control the first transistor MA13 to turn off. The signal cb-3 may control the second transistor MB13 to be turned on to supply the 0V voltage of the second reference voltage terminal VR2 to the second electrode plate of the storage capacitor C13. Thus, the amount of charge Q1-1' on the collection line CC-1 satisfies the formula: q1-1' ═ c11 (vcom-vr1) + c13 vcom. Wherein C13 represents the capacitance value of the storage capacitor C13.

And vs2 controls control switch K2 to close, so that the voltage on collection line CC-2 is the voltage vcom of reference voltage terminal VG. The signal cb-1 may control the second transistor MB21 to turn off. The signal ca-1 may control the first transistor MA21 to be turned on to provide the voltage VR1 of the first reference voltage terminal VR1 to the second electrode plate of the storage capacitor C21. Also, the signal ca-2 may control the first transistor MA22 to turn off. The signal cb-2 may control the second transistor MB22 to turn off. And, the signal ca-3 may control the first transistor MA23 to turn off. The signal cb-3 may control the second transistor MB23 to be turned on to supply the 0V voltage of the second reference voltage terminal VR2 to the second electrode plate of the storage capacitor C23. Thus, the amount of charge Q2-1' on the collection line CC-2 satisfies the formula: q2-1' ═ c11 (vcom-vr1) + c23 vcom. Wherein C23 represents the capacitance value of the storage capacitor C13.

And vs3 controls the control switch K3 to be closed, so that the voltage on the collection line CC-3 is the voltage vcom of the reference voltage end VG. The signal cb-1 may control the second transistor MB31 to turn off. The signal ca-1 may control the first transistor MA31 to be turned on to provide the voltage VR1 of the first reference voltage terminal VR1 to the second electrode plate of the storage capacitor C31. Also, the signal ca-2 may control the first transistor MA32 to turn off. The signal cb-2 may control the second transistor MB32 to turn off. And, the signal ca-3 may control the first transistor MA33 to turn off. The signal cb-3 may control the second transistor MB33 to be turned on to supply the 0V voltage of the second reference voltage terminal VR2 to the second electrode plate of the storage capacitor C33. Thus, the amount of charge Q3-1' on the collection line CC-3 satisfies the formula: q3-1' ═ c11 (vcom-vr1) + c33 vcom. Wherein C33 represents the capacitance value of the storage capacitor C33.

In the second sub-acquisition phase T22, vs1 controls the control switch K1 to be turned off, and the acquisition line CC-1 is disconnected from the reference voltage terminal VG. The signal ca-1 may control the first transistor MA11 to turn off. The signal cb-1 may control the second transistor MB11 to be turned on to supply the 0V voltage of the second reference voltage terminal VR2 to the second electrode plate of the storage capacitor C11. And, the signal cb-2 may control the second transistor MB12 to turn off. The signal ca-2 may control the first transistor MA12 to turn off. And, the signal cb-3 may control the second transistor MB13 to turn off. The signal ca-3 may control the first transistor MA13 to turn on to provide the voltage VR1 of the first reference voltage terminal VR1 to the second electrode plate of the storage capacitor C13. Thus, the amount of charge Q2-1' on the collection line CC-1 satisfies the formula: q2-1 ' ═ c13 (v1 ' -vr1) + c11 × v1 '. Where C13 represents the capacitance value of the storage capacitor C13 and v 1' represents the voltage on the collection line CC-1. According to the principle of charge conservation, the amount of charge on the collection line CC-1 is unchanged during the first sub-collection phase T21 and the second sub-collection phase T22, and thus, Q2-1 'is Q1-1'. V 1'Satisfies the formula:

therefore, the voltage difference v 1' -vcom across the comparator VC1 is

If c13 is equal to c11, the comparator VC1 outputs "0" as the first comparison level. If, c13>c11, the comparator VC1 outputs "1" as the second comparison level.

And vs2 controls the control switch K2 to be disconnected, and the collection line CC-2 is disconnected with the reference voltage end VG. The signal ca-1 may control the first transistor MA21 to turn off. The signal cb-1 may control the second transistor MB21 to be turned on to supply the 0V voltage of the second reference voltage terminal VR2 to the second electrode plate of the storage capacitor C21. And, the signal cb-2 may control the second transistor MB22 to turn off. The signal ca-2 may control the first transistor MA22 to turn off. And, the signal cb-3 may control the second transistor MB23 to turn off. The signal ca-3 may control the first transistor MA23 to turn on to provide the voltage VR1 of the first reference voltage terminal VR1 to the second electrode plate of the storage capacitor C23. Thus, the amount of charge Q2-2' on the collection line CC-2 satisfies the formula: q2-2 ' ═ c23 (v2 ' -vr1) + c21 × v2 '. Where C23 represents the capacitance value of the storage capacitor C23 and v 2' represents the voltage on the collection line CC-2. According to the principle of charge conservation, the amount of charge on the collection line CC-2 is not changed in the first sub-collection phase T21 and the second sub-collection phase T22, and thus, Q2-2 'is Q1-2'. Then v 2' satisfies the formula:

therefore, the voltage difference v 2' -vcom across the comparator VC2 is

If c23 is equal to c21, the comparator VC2 outputs "0" as the first comparison level. If, c23>c21, the comparator VC2 outputs "1" as the second comparison level.

And vs3 controls the control switch K3 to be disconnected, and the collection line CC-3 is disconnected with the reference voltage end VG.The signal ca-1 may control the first transistor MA31 to turn off. The signal cb-1 may control the second transistor MB31 to be turned on to supply the 0V voltage of the second reference voltage terminal VR2 to the second electrode plate of the storage capacitor C31. And, the signal cb-2 may control the second transistor MB32 to turn off. The signal ca-2 may control the first transistor MA32 to turn off. And, the signal cb-3 may control the second transistor MB33 to turn off. The signal ca-3 may control the first transistor MA33 to turn on to provide the voltage VR1 of the first reference voltage terminal VR1 to the second electrode plate of the storage capacitor C33. Therefore, the charge amount Q3-2' on the collection line CC-3 satisfies the formula: q3-2 ' ═ c33 (v3 ' -vr1) + c31 × v3 '. Where C33 represents the capacitance value of the storage capacitor C33 and v 3' represents the voltage on the collection line CC-3. According to the principle of charge conservation, the amount of charge on the collection line CC-3 is not changed in the first sub-collection phase T21 and the second sub-collection phase T22, and thus, Q3-2 'is Q3-2'. Then v 3' satisfies the formula:

therefore, the voltage difference v 3' -vcom across the comparator VC3 is

If c33 is equal to c31, the comparator VC3 outputs "0" as the first comparison level. If, c33>c31, the comparator VC3 outputs "1" as the second comparison level.

For example, in the second sub-acquisition phase T12, the output terminal VO1 of the comparator VC1 outputs "0", the output terminal VO2 of the comparator VC2 outputs "1", and the output terminal VO3 of the comparator VC3 outputs "1". The data processing unit 130 may receive that the output terminal VO1 of the comparator VC1 outputs "0", the output terminal VO2 of the comparator VC2 outputs "1", and the output terminal VO3 of the comparator VC3 outputs "1".

And in the second sub-acquisition stage T22, the output terminal VO1 of the comparator VC1 outputs "1", the output terminal VO2 of the comparator VC2 outputs "0", and the output terminal VO3 of the comparator VC3 outputs "1". The data processing unit 130 may receive that the output terminal VO1 of the comparator VC1 outputs "1", the output terminal VO2 of the comparator VC2 outputs "0", and the output terminal VO3 of the comparator VC3 outputs "1".

Thereafter, the data processing unit 130 may generate a binary image from these received "0" and "1". Therefore, after feature extraction and feature comparison are sequentially carried out according to the generated binary image, the information of the valleys and ridges of the fingerprint is determined so as to complete fingerprint identification.

In the embodiment of the present disclosure, the fingerprint identification device may be combined with the display panel, so that the display panel may implement fingerprint identification.

In the embodiment of the disclosure, the fingerprint identification device can also directly and independently perform fingerprint identification. For example, the fingerprint identification device may be a fingerprint punched card machine, a fingerprint lock, or the like.

The fingerprint identification device and the fingerprint identification method provided by the disclosure are characterized in that the acquisition units and the comparison units are arranged on the liner, the storage capacitors of the acquisition units in the first column are configured to be reference capacitors with fixed capacitance values, and the storage capacitors of the acquisition units in the other columns are configured to be acquisition capacitors with variable capacitance values when a finger presses; therefore, the comparison unit can output a first comparison level when the capacitance value of the electrically connected acquisition capacitor is the same as that of the reference capacitor, and output a second comparison level when the capacitance value of the electrically connected acquisition capacitor is larger than that of the reference capacitor. Therefore, the binary numerical value of the fingerprint can be directly output through a hardware circuit, so that the binary image of the fingerprint can be directly obtained through the binary numerical value, and the power consumption of fingerprint detection is reduced. And the flow of fingerprint identification can be more concise, and a binary image can be generated without additionally setting a large amount of programming codes, so that the situations of excessive image processing and insufficient image processing can be avoided, and the accuracy of fingerprint detection is improved.

It will be apparent to those skilled in the art that various changes and modifications can be made in the present disclosure without departing from the spirit and scope of the disclosure. Thus, if such modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such modifications and variations as well.

Claims (10)

1. A fingerprint recognition device, comprising:

a substrate base plate;

the plurality of acquisition units are arranged on the substrate in an array manner; wherein, the collection unit includes: a storage capacitor; the storage capacitors of the first column acquisition units are configured as reference capacitors with fixed capacitance values, and the storage capacitors of the rest of the column acquisition units are configured as acquisition capacitors with variable capacitance values when pressed by fingers;

a plurality of comparison units on the substrate base plate; one comparison unit is electrically connected with the first electrode plate of the storage capacitor in one row of acquisition units; and the comparison unit is configured to: and outputting a first comparison level when the capacitance value of the electrically connected acquisition capacitor is the same as the capacitance value of the reference capacitor, and outputting a second comparison level when the capacitance value of the connected acquisition capacitor is larger than the capacitance value of the reference capacitor.

2. The fingerprint recognition device of claim 1, wherein the acquisition unit further comprises: a first control circuit and a second control circuit;

the first control circuit is configured to switch on and off a first reference voltage terminal and a second electrode plate of the storage capacitor in response to a signal of a first control terminal;

the second control circuit is configured to turn on and off a second reference voltage terminal with a second electrode plate of the storage capacitor in response to a signal of a second control terminal.

3. The fingerprint recognition device of claim 2, wherein the first control circuit comprises: a first transistor;

the gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the first reference voltage terminal, and the second electrode of the first transistor is electrically connected to the second electrode plate of the storage capacitor.

4. The fingerprint recognition device of claim 2, wherein the second control circuit comprises: a second transistor;

the grid electrode of the second transistor is electrically connected with the second control end, the first electrode of the second transistor is electrically connected with the second reference voltage end, and the second electrode of the second transistor is electrically connected with the second electrode plate of the storage capacitor.

5. The fingerprint recognition device of claim 2, wherein the fingerprint recognition device further comprises:

a plurality of first control lines; one first control line is electrically connected with the first control ends corresponding to the first control circuits of the acquisition units in one row;

a plurality of second control lines; one second control line is electrically connected with second control ends corresponding to second control circuits of one row of the acquisition units;

a plurality of collection lines; and the first electrode plates of the storage capacitors in one row of acquisition units are electrically connected with the corresponding comparison unit through one acquisition line.

6. The fingerprint recognition apparatus according to any one of claims 1-5, wherein said comparison unit comprises; a comparator and a control switch;

the control end of the control switch is electrically connected with the acquisition control end, the first end of the control switch is electrically connected with the reference voltage end, and the second end of the control switch is electrically connected with the negative phase input end of the comparator;

a non-inverting input terminal of the comparator is electrically connected to the reference voltage terminal, and an output terminal of the comparator is configured to output the first comparison level and the second comparison level.

7. The fingerprint recognition device of claim 6, wherein said fingerprint recognition device further comprises: a data processing unit;

the data processing unit is electrically connected with the plurality of comparison units respectively; the data processing unit is configured to receive the first comparison level and the second comparison level output by the comparison unit, generate a binary image according to the received first comparison level and second comparison level, and perform fingerprint recognition according to the generated binary image.

8. A fingerprint recognition method of a fingerprint recognition device according to any one of claims 1 to 7, comprising:

the output capacitance value of the acquisition capacitor connected with the same comparison unit is controlled in a time-sharing manner, and the output capacitance value of the reference capacitor connected with the same comparison unit is controlled when the capacitance value of the acquisition capacitor is output; and a first comparison level is output when the capacitance value of the acquisition capacitor electrically connected with the same comparison unit is the same as the capacitance value of the reference capacitor; when the capacitance value of the acquisition capacitor connected with the same comparison unit is larger than that of the reference capacitor, outputting a second comparison level;

generating a binary image according to the first comparison level and the second comparison level;

and performing fingerprint identification according to the generated binary image.

9. The fingerprint identification method of the fingerprint identification device according to claim 8, wherein the time-sharing control is performed on the output capacitance value of the collecting capacitor connected with the same comparing unit, and when the output capacitance value of the collecting capacitor is obtained, the time-sharing control is performed on the output capacitance value of the reference capacitor connected with the same comparing unit; the method comprises the following steps:

dividing one frame of acquisition time into a plurality of acquisition stages; wherein, a row of acquisition units with the acquisition capacitor corresponds to an acquisition stage; the acquisition stage comprises a first sub-acquisition stage and a second sub-acquisition stage;

in the first sub-acquisition stage, loading a signal of a first level to an acquisition control end of a control switch in each comparison unit, loading a signal of a first level to a first control line connected with the first row of acquisition units, loading a signal of a second level to a second control line connected with the first row of acquisition units, loading a signal of a first level to a first control line electrically connected with the acquisition unit corresponding to the acquisition stage, and loading a signal of a second level to a second control line electrically connected with the acquisition unit corresponding to the acquisition stage;

in the second sub-acquisition stage, a signal of a second level is loaded to an acquisition control end of a control switch in each comparison unit, a signal of a second level is loaded to a first control line connected to the first row of acquisition units, a signal of a first level is loaded to a second control line connected to the first row of acquisition units, a signal of a second level is loaded to a first control line electrically connected to the acquisition unit corresponding to the acquisition stage, and a signal of a second level is loaded to a second control line electrically connected to the acquisition unit corresponding to the acquisition stage.

10. The fingerprint recognition method of the fingerprint recognition device according to claim 8, wherein the fingerprint recognition based on the generated binary image comprises:

and according to the generated binary image, sequentially performing feature extraction and feature comparison to determine the information of the valleys and ridges of the fingerprint.

Images