CN114035641B - Band gap reference circuit with high performance - Google Patents

Band gap reference circuit with high performance Download PDF

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Publication number
CN114035641B
CN114035641B CN202111296272.7A CN202111296272A CN114035641B CN 114035641 B CN114035641 B CN 114035641B CN 202111296272 A CN202111296272 A CN 202111296272A CN 114035641 B CN114035641 B CN 114035641B
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transistor
resistor
circuit
terminal
circuit module
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CN114035641A (en
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李娅妮
张佐已
皇甫自宽
朱樟明
杨银堂
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Chongqing Institute Of Integrated Circuit Innovation Xi'an University Of Electronic Science And Technology
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Chongqing Institute Of Integrated Circuit Innovation Xi'an University Of Electronic Science And Technology
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a band gap reference circuit with high performance, which comprises: the self-bias current source circuit comprises a band gap core circuit, a multistage operational amplifier closed-loop circuit, a base current compensation circuit, a Trim circuit and a self-bias current source circuit; the self-bias current source circuit is used for outputting bias current according to starting current so as to control the multistage operational amplifier closed-loop circuit to enter a working state; the multistage operational amplifier closed-loop circuit is used for controlling the band gap core circuit to generate reference voltage; the base current compensation circuit is used for outputting compensation current to the band gap core circuit; the base current compensation circuit and the Trim circuit are used for adjusting the reference voltage to be equal to a target voltage so as to obtain a final voltage. The invention can ensure the stability of the circuit in the environments of process, voltage, temperature change and the like.

Description

Band gap reference circuit with high performance
Technical Field
The invention belongs to the field of integrated circuits, and particularly relates to a band gap reference circuit with high performance.
Background
In analog integrated circuit designs, bandgap references are widely used in hybrid integrated circuits as a primary circuit structure to provide a stable dc voltage independent of supply voltage and temperature variations.
An operational amplifier is generally used in the conventional bandgap reference voltage source (see fig. 1), however, due to the low voltage trend of CMOS (Complementary Metal Oxide Semiconductor ) technology, the typical value of the intrinsic gain of the transistor is about 20-30dB in the deep submicron process, which results in the performance degradation of the operational amplifier, failing to meet the requirements of the bandgap reference circuit for the gain, bandwidth, etc., and reducing the PSRR (Power Supply Rejection Rati, power supply rejection ratio) and stability of the bandgap reference circuit. Resulting in poor loading of the bandgap reference circuit, low PSRR and large loss of bandgap reference source.
Fig. 1 provides a circuit diagram of a conventional bandgap reference circuit. In the circuit shown in fig. 1, the operational amplifier is generally a 2-stage operational amplifier, while the power consumption and the complexity of the circuit design of the bandgap reference circuit are greatly reduced, the circuit performance cannot reach the circuit design index, and meanwhile, if the structural design of the operational amplifier is unreasonable, the nonideal factors such as offset and the like of the operational amplifier cannot be well eliminated and suppressed, so that the stability and the accuracy of the bandgap reference are seriously affected, and even the function of the bandgap reference circuit may be lost.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a bandgap reference circuit having high performance. The technical problems to be solved by the invention are realized by the following technical scheme:
a bandgap reference circuit having high performance, the circuit comprising: the self-bias current source circuit comprises a band gap core circuit, a multistage operational amplifier closed-loop circuit, a base current compensation circuit, a Trim circuit and a self-bias current source circuit; the self-bias current source circuit is used for outputting bias current according to starting current so as to control the multistage operational amplifier closed-loop circuit to enter a working state; the multistage operational amplifier closed-loop circuit is used for controlling the band gap core circuit to generate reference voltage; the base current compensation circuit is used for outputting compensation current to the band gap core circuit; the base current compensation circuit and the Trim circuit are used for adjusting the reference voltage to be equal to a target voltage so as to obtain a final voltage.
In one embodiment of the present invention, the bandgap core circuit includes: transistor Q10, transistor Q12, transistor Q13, transistor Q14, and transistor MP12, resistor R13, resistor R14, resistor R15, resistor R16, resistor R17, resistor R18, resistor R19, and resistor R34; wherein, the transistors Q10, Q12, Q13 and Q14 are PNP bipolar transistors; an emitter of the transistor Q12 is connected with an emitter of the transistor Q13 and a drain terminal of the transistor MP 12; the base electrode of the transistor Q12 is connected with one end of a resistor R15; the collector of the transistor Q12 is connected with one end of the resistor R16, the base of the transistor Q16 and the collector of the transistor Q19; the base of the transistor Q13 is connected with the base of the transistor Q14 and the emitter of the transistor Q14; the collector of the transistor Q13 is connected with the collector of the transistor Q14, the base of the transistor Q15, the collector of the transistor Q20 and one end of the resistor R17; the other end of the resistor R16 is connected with the other end of the resistor R17 and one end of the resistor R18; the other end of the resistor R18 is connected with the ground; the gate terminal of the transistor MP12 is connected with the drain terminal of the transistor MN7, the drain terminal of the transistor MP11, the drain terminal of the transistor MP16 and the gate terminal of the transistor MP 16; the source end of the transistor MP12 is connected with one end of a resistor R19; the other end of the resistor R19 is connected with a power supply VDD; the collector of the transistor Q10 is connected with the collector of the transistor Q11, the base of the transistor Q11, the input terminal REFS of the first circuit module, one end of the capacitor C7, the gate terminal of the transistor MN16, the drain terminal of the transistor MN15, the drain terminal of the transistor MP21, the drain terminal of the transistor MP22, the body terminal of the transistor MP22, and one end of the capacitor C3; the base electrode of the transistor Q10 is connected with the output end of the second circuit module; the emitter of the transistor Q10 is connected to the input of the third circuit module.
In one embodiment of the present invention, the multi-stage op-amp closed loop circuit includes: transistor Q15, transistor Q16, transistor Q17, transistor Q18, transistor Q19, transistor Q20, transistor Q21, transistor Q11, transistor MP17, transistor MP18, transistor MP21, transistor MP22, transistor MP19, transistor MN12, transistor MN13, transistor MN14, and transistor MN15, resistor R12, resistor R24, resistor R23, resistor R22, resistor R20, resistor R21, resistor R25, resistor R26, resistor R27, resistor R28, resistor R29, resistor R30, resistor R31, and resistor R32, capacitor C2, capacitor C3, capacitor C4, capacitor C5, first circuit block, second circuit block; the transistors Q15, Q16, Q19 and Q20 are PNP transistors, the transistors Q11, Q17, Q18 and Q21 are NPN transistors Q15, the collector of the transistor Q20, the collector of the transistor Q14 and the collector of the transistor Q13, and one end of the resistor R17 are connected; the base of the transistor Q16 is connected with the collector of the transistor Q12 and one end of the resistor R16; the emitter of the transistor Q15, the emitter of the transistor Q16 and the drain terminal of the transistor MP14 are connected; the collector of the transistor Q16, the collector of the transistor Q17, the base of the transistor Q21, and the drain of the transistor MN9 are connected with one end of the capacitor C2 and one end of the resistor R20; the collector of the transistor Q15, the collector of the transistor Q18, the base of the transistor Q17 and the drain of the transistor MN8 are connected with the other end of the resistor R20; the gate end of the transistor MP14 is connected with the gate end of the transistor MP8, the gate end of the transistor MP6, the gate end of the transistor MP3, the gate end of the transistor MP2, the gate end of the transistor MP15 and the drain end of the transistor MP 8; the source terminal of the transistor MP14 is connected with one end of a resistor R21; the other end of the resistor R21 is connected with a power supply VDD; the emitter of the transistor Q18, the emitter of the transistor Q17 and the source of the transistor MN8 are connected with ground; the emitter of the transistor Q21 and the source of the transistor MN9 are connected with the ground VSS; the collector of the transistor Q21, the drain of the transistor MP15, and the gate of the transistor MN14 are connected with one end of the resistor R29, the capacitor C5, and the drain of the transistor MN 10; the other end of the resistor R29 is connected with the other end of the capacitor C2; the source end of the transistor MP15 is connected with one end of a resistor R25; the other end of the resistor R25 is connected with a power supply VDD; the gate terminal of the transistor MP16, the drain terminal of the transistor MP16, the gate terminal of the transistor MP17, the gate terminal of the transistor MP18, the drain terminal of the transistor MP19, and the drain terminal of the transistor MP11 are connected with the drain terminal of the MN 7; the source end of MP16 is connected with one end of resistor R26; the other end of the resistor R26 is connected with a power supply VDD; the source end of MP17 is connected with one end of a resistor R27; the other end of the resistor R27 is connected with a power supply VSS; the drain terminal of the transistor MP16 is connected with the drain terminal of the transistor MN12, the gate terminal of the transistor MN13 and the drain terminal of the transistor MN 11; the source terminal of the transistor MN12 is connected to one terminal of the resistor R30; the other end of the resistor R30 is connected with the ground VSS; the source terminal of the transistor MN13 is connected to one terminal of the resistor R31; the other end of the resistor R31 is connected with the ground VSS; the drain terminal of the transistor MN13 is connected with the source terminal of the transistor MN14 and the body terminal of the transistor MN 14; the drain terminal of the transistor MN14 is connected to the drain terminal of the transistor MP22, the gate terminal of the transistor MP21, the drain terminal of the transistor MP18, the other end of the capacitor C3, and one end of the capacitor C4; the source end of MP18 is connected with one end of resistor R28; the other end of the resistor R28 is connected with a power supply VSS, and the other end of the capacitor C4 is connected with one end of the resistor R32; the other end of the resistor R32 is connected with a power supply VDD; the source end of the transistor MP21 is connected with a power supply VDD; the drain terminal of the transistor MP21 is connected with the source terminal of the transistor MP22, the body terminal of the transistor MP22, the drain terminal of the transistor MN15, the gate terminal of the transistor MN16, one end of the capacitor C3 and one end of the capacitor C7; the source terminal of the transistor MN15 is connected to the ground VSS; the other end of the capacitor C7 is connected to ground VSS.
The invention has the beneficial effects that:
the invention can improve the load performance and stability of the band gap reference circuit through the multistage operational amplifier closed-loop circuit, and has higher power supply voltage rejection ratio (PSRR, power Supply Rejection Ratio). In addition, the invention can reduce reference voltage offset through the Trim circuit and improve the accuracy and the qualitability of the circuit.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic diagram of a conventional bandgap reference circuit;
FIG. 2 is a schematic diagram of a bandgap reference circuit according to an embodiment of the present invention;
FIG. 3 (a) is a schematic diagram of a bandgap reference circuit according to an embodiment of the invention;
FIG. 3 (b) is a schematic diagram of a first circuit module according to an embodiment of the present invention;
FIG. 3 (c) is a schematic diagram of a second circuit module according to an embodiment of the present invention;
fig. 3 (d) is a schematic diagram of a third circuit module according to an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Example 1
Referring to fig. 2, fig. 2 is a schematic diagram of a bandgap reference circuit according to an embodiment of the invention,
the circuit comprises: the self-bias current source circuit comprises a band gap core circuit, a multistage operational amplifier closed-loop circuit, a base current compensation circuit, a Trim circuit and a self-bias current source circuit.
The self-bias current source circuit is used for outputting bias current according to starting current so as to control the multistage operational amplifier closed-loop circuit to enter a working state.
The self-bias current source circuit can start the band gap self-bias circuit after the band gap starting current flows in, and provides bias current for the multistage operational amplifier closed-loop circuit.
The multistage operational amplifier closed loop circuit is used for controlling the band gap core circuit to generate reference voltage.
The multistage operational amplifier closed-loop circuit can control and improve the stability of the band-gap reference circuit and improve the load capacity of the band-gap reference circuit.
The base current compensation circuit is used for outputting compensation current to the band gap core circuit.
The base current compensation circuit can also be called as a band gap core PNP transistor base current compensation circuit, and can perform current compensation when the base current and the emitter current are different due to different numbers of band gap core transistors m in the band gap core circuit, so that band gap reference voltages can still be kept normal under different process angles.
The base current compensation circuit and the Trim circuit are used for adjusting the reference voltage to be equal to a target voltage so as to obtain a final voltage.
The Trim circuit can eliminate errors between the obtained reference voltage and the target voltage generated by the band gap reference circuit under different process conditions through the 7-bit digital Trim code.
The working process of the band gap reference circuit provided by the invention is as follows: the circuit is electrified, starting current firstly flows into the self-bias current source circuit to generate bias current for the multi-stage operational amplifier closed-loop circuit, the band gap core circuit generates reference voltage, and meanwhile, under the combined action of the multi-stage operational amplifier closed-loop circuit, the base current compensation circuit and the Trim circuit, the malignant influence of non-ideal factors such as power supply voltage fluctuation, device mismatch and the like on the circuit is restrained, the stability of the circuit is improved, and the function realization of the circuit is ensured.
See fig. 3 (a), 3 (b), 3 (c), 3 (d).
The transistor MN is an NMOS transistor, and the transistor MP is a PMOS transistor.
Optionally, the bandgap core circuit includes:
transistor Q10, transistor Q12, transistor Q13, transistor Q14, and transistor MP12, resistor R13, resistor R14, resistor R15, resistor R16, resistor R17, resistor R18, resistor R19, and resistor R34.
The transistors Q10, Q12, Q13, and Q14 are PNP bipolar transistors.
The emitter of the transistor Q12 is connected to the emitter of the transistor Q13 and the drain of the transistor MP 12.
The base of transistor Q12 is connected to one end of resistor R15.
The collector of the transistor Q12 is connected to one end of the resistor R16, the base of the transistor Q16, and the collector of the transistor Q19.
The base of the transistor Q13 is connected to the base of the transistor Q14 and the emitter of the transistor Q14.
The collector of transistor Q13 is connected to the collector of transistor Q14, the base of transistor Q15, the collector of transistor Q20, and one end of resistor R17.
The other end of the resistor R16 is connected to the other end of the resistor R17 and one end of the resistor R18.
The other end of resistor R18 is connected to ground.
The gate terminal of the transistor MP12 is connected to the drain terminal of the transistor MN7, the drain terminal of the transistor MP11, the drain terminal of the transistor MP16, and the gate terminal of the transistor MP 16.
The source terminal of transistor MP12 is connected to one terminal of resistor R19.
The other end of the resistor R19 is connected to the power supply VDD.
The collector of the transistor Q10 is connected to the collector of the transistor Q11, the base of the transistor Q11, the input terminal REFS of the first circuit block, one terminal of the capacitor C7, the gate terminal of the transistor MN16, the drain terminal of the transistor MN15, the drain terminal of the transistor MP21, the drain terminal of the transistor MP22, the body terminal of the transistor MP22, and one terminal of the capacitor C3.
The base of the transistor Q10 is connected to the output of the second circuit block.
The emitter of the transistor Q10 is connected to the input of the third circuit module.
Referring to fig. 3 (a), the present invention can increase the gain and stability of the operational amplifier and increase the loading of the bandgap reference voltage source when increasing the order of the operational amplifier. The method comprises the following steps:
in the case of temporarily disregarding device mismatch, the characteristic of virtual short circuit of input node in closed loop is used in multistage operational amplifier to equalize the potential of node A and node B, and thus the voltage across resistor R16 is equalized with the voltage across resistor R17, when the resistance of resistor R16 and resistor R17 are identical, the collector current flowing through transistor Q12 is equalized with the collector current of transistor Q13, thereby obtaining a voltage difference DeltaV BE A PTAT current is shown, which is passed through a resistor to obtain a positive temperature coefficient voltage, which is equal to the base-emitter voltage V of transistor Q10 having a negative temperature coefficient BE10 After summation, the target voltage V is obtained REF 。
In addition, the base current of the transistor Q12 and the base current of the transistor Q13 are compensated through the transistor Q3 and the transistor Q4 by the base current compensation circuit of the band gap core transistor, so that the accuracy of band gap output voltage is improved.
Optionally, the multi-stage operational amplifier closed loop circuit includes:
transistor Q15, transistor Q16, transistor Q17, transistor Q18, transistor Q19, transistor Q20, transistor Q21, transistor Q11, transistor MP17, transistor MP18, transistor MP21, transistor MP22, transistor MP19, transistor MN12, transistor MN13, transistor MN14, and transistor MN15, resistor R12, resistor R24, resistor R23, resistor R22, resistor R20, resistor R21, resistor R25, resistor R26, resistor R27, resistor R28, resistor R29, resistor R30, resistor R31, and resistor R32, capacitor C2, capacitor C3, capacitor C4, capacitor C5, first circuit block, second circuit block.
The transistors Q15, Q16, Q19, and Q20 are PNP transistors, and the transistors Q11, Q17, Q18, and Q21 are NPN transistors.
The base of transistor Q15, the collector of transistor Q20, the collector of transistor Q14 are connected to the collector of transistor Q13, one terminal of resistor R17.
The base of transistor Q16 is connected to the collector of transistor Q12 and to one end of resistor R16.
The emitter of the transistor Q15, the emitter of the transistor Q16, and the drain of the transistor MP14 are connected.
The collector of the transistor Q16, the collector of the transistor Q17, the base of the transistor Q21, and the drain of the transistor MN9 are connected to one end of the capacitor C2 and one end of the resistor R20.
The collector of the transistor Q15, the collector of the transistor Q18, the base of the transistor Q17, and the drain of the transistor MN8 are connected to the other end of the resistor R20.
The gate terminal of the transistor MP14 is connected to the gate terminal of the transistor MP8, the gate terminal of the transistor MP6, the gate terminal of the transistor MP3, the gate terminal of the transistor MP2, the gate terminal of the transistor MP15, and the drain terminal of the transistor MP 8.
The source terminal of the transistor MP14 is connected to one terminal of the resistor R21.
The other end of the resistor R21 is connected to the power supply VDD.
The emitter of transistor Q18, the emitter of transistor Q17, and the source of transistor MN8 are connected to ground.
The emitter of the transistor Q21 and the source of the transistor MN9 are connected to the ground VSS.
The collector of the transistor Q21, the drain of the transistor MP15, and the gate of the transistor MN14 are connected to one end of the resistor R29, the capacitor C5, and the drain of the transistor MN 10.
The other end of the resistor R29 is connected to the other end of the capacitor C2.
The source terminal of transistor MP15 is connected to one terminal of resistor R25.
The other end of the resistor R25 is connected to the power supply VDD.
The gate terminal of the transistor MP16, the drain terminal of the transistor MP16, the gate terminal of the transistor MP17, the gate terminal of the transistor MP18, the drain terminal of the transistor MP19, the drain terminal of the transistor MP11 are connected to the drain terminal of the transistor MN 7.
The source terminal of transistor MP16 is connected to one terminal of resistor R26.
The other end of the resistor R26 is connected to the power supply VDD.
The source terminal of transistor MP17 is connected to one terminal of resistor R27.
The other end of the resistor R27 is connected to the power supply VSS.
The drain terminal of the transistor MP16 is connected to the drain terminal of the transistor MN12, the gate terminal of the transistor MN13, and the drain terminal of the transistor MN 11.
The source terminal of the transistor MN12 is connected to one terminal of the resistor R30.
The other end of resistor R30 is connected to ground VSS.
The source terminal of the transistor MN13 is connected to one terminal of the resistor R31.
The other end of the resistor R31 is connected to ground VSS.
The drain terminal of the transistor MN13 is connected to the source terminal of the transistor MN14 and the body terminal of the transistor MN 14.
The drain terminal of the transistor MN14 is connected to the drain terminal of the transistor MP22, the gate terminal of the transistor MP21, the drain terminal of the transistor MP18, the other terminal of the capacitor C3, and one terminal of the capacitor C4.
The source terminal of MP18 is connected to one terminal of resistor R28.
The other end of resistor R28 is connected to power supply VSS.
The other end of the capacitor C4 is connected to one end of the resistor R32.
The other end of the resistor R32 is connected to the power supply VDD.
The source terminal of the transistor MP21 is connected to the power supply VDD.
The drain terminal of the transistor MP21 is connected to the source terminal of the transistor MP22, the body terminal of the transistor MP22, the drain terminal of the transistor MN15, the gate terminal of the transistor MN16, one terminal of the capacitor C3, and one terminal of the capacitor C7.
The source of transistor MN15 is connected to ground VSS.
The other end of the capacitor C7 is connected to ground VSS.
In the multistage operational amplifier closed loop circuit shown in fig. 3 (a), the transistors Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q11, MP17, MP18, MP21, MP22, MP19, MN12, MN13, MN14, MN15, R12, R24, R23, R22, R20, R21, R25, R26, R27, R28, R29, R30, R31, R32, C2, C3, C4, C5, ref_div, bgsw_4to1, trim constitute a multistage operational amplifier closed loop circuit, which is useful for suppressing power supply disturbance and improving power supply voltage suppression ratio. The circuit structure has the following specific principle of stabilizing voltage bias and inhibiting power supply fluctuation:
when the power supply is disturbed, the power supply equivalent to the multistage operational amplifier is jumped, and at the moment, the gate-source voltages of the transistors MP14, MP15, MP16, MP17 and MP18 are slightly changed, but the gains are very small, so that the drain currents of the transistors MP14, MP15, MP16, MP17 and MP18 are very small in change at low frequency, the influence on the multistage operational amplifier closed-loop circuit is very low and almost negligible, and the PSRR of the product can reach 120dB at low frequency.
The negative feedback structure also has a suppressing effect on device mismatch. If VA > VB, the current flowing through the transistor Q15 will rise, and the current flowing through the transistor Q16 will also rise due to the mirror effect of the transistor Q17 and the current mirror formed by the transistor Q18, i.e. the base emitter voltage of Q2 will rise, while the emitter voltage of Q2 will remain unchanged due to the connection with the emitter of Q15, so the base voltage VB of Q2 will be raised, reducing the gap from VA.
For improving the loadability, the gain and stability of the multi-stage operational amplifier closed-loop circuit are particularly good, the gain of the first-stage amplifier is reduced through the resistor R20, the capacitor C2 and the resistor R29 carry out Miller compensation on the output of the first-stage amplifier circuit and the output of the second-stage amplifier circuit, so that the gain of the multi-stage operational amplifier closed-loop circuit is stable under the condition of very high, and the phase margin full process angle is more than 50 deg.
Optionally, the input terminal VDD of the first circuit module is connected to a power supply VDD.
The input REFS of the first circuit block is connected to the gate terminal of the transistor MN 16.
The input terminal VSS of the first circuit module is connected to ground VSS.
The output VBG0 of the first circuit module is connected to the input i0 of the second circuit module.
The output VBG1 of the first circuit module is connected to the input i1 of the second circuit module.
The output VBG2 of the first circuit module is connected to the input i2 of the second circuit module.
The output VBG3 of the first circuit module is connected to the input i3 of the second circuit module.
In the first circuit module:
the input REFS of the first circuit module is connected to one end of a resistor R34.
The other end of the resistor R34 is connected with one end of the resistor R35 and the output end VBG 0.
The other end of the resistor R35 is connected with one end of the resistor R36 and the output end VBG 1.
The other end of the resistor R36 is connected with one end of the resistor R37 and the output end VBG 2.
The other end of the resistor R37 is connected with one end of the resistor R38 and the output end VBG 3.
The other end of resistor R38 is connected to input terminal VSS.
The input S1 of the second circuit module is connected to the first control signal input.
The first control signal input is represented as: digital code BGC <1>.
The input terminal S0 of the second circuit module is connected to the second control signal input terminal.
The second control signal inputs digital code BGC <0>.
The input terminal VDD of the second circuit block is connected to the power supply VDD.
The input terminal VSS of the second circuit module is connected to ground VSS.
The output OUT of the second circuit block is connected to the base of the transistor Q10.
Optionally, the Trim circuit includes: and a third circuit module.
The third circuit module input terminal TR <6:0> is connected with the digital signal Trim code <6:0 >.
The input terminal VDD of the third circuit block is connected to the power supply VDD.
The input IN of the third circuit module is connected to the emitter of the transistor Q10.
The input BOT of the third circuit module is connected to one end of a resistor R34.
The input terminal VSS of the third circuit module is connected to ground VSS.
The output OUT of the third circuit block is connected to the base of the ground transistor Q13.
The third circuit module includes: transistor MN17, transistor MN18, transistor MN19, transistor MN20, transistor MN21, transistor MN22, transistor MN23, and transistor MN24, resistor R39, resistor R40, resistor R41, resistor R42, resistor R43, resistor R44, resistor R45, resistor R46, resistor R47, resistor R48, resistor R49, resistor R50, resistor R51, resistor R52, resistor R53, resistor R54, and resistor R55.
Referring to fig. 3 (d), for the offset generated at different process angles, the Trim is controlled by the digital signal Trim code <6:0>, the switching tube in the Trim circuit module is controlled, the Trim circuit overall presents a resistance state to the outside, the resistance value is related to the assignment of the digital signal Trim code <6:0>, and the voltage of a positive temperature coefficient can be adjusted by adjusting the digital signal Trim code <6:0>, so that the zero temperature coefficient voltage controlled by the digital signal Trim code <6:0> is generated at the base electrode of the transistor Q10. Under the condition of the full process angle, the output voltage of the band gap reference circuit can be effectively controlled to be 1.25V, and 6Sigma is only 1.5mV under the condition of the full process angle, so that the accuracy of the circuit is greatly improved.
Optionally, the base current compensation circuit includes: transistors MP1, Q2, Q3, and Q4, and resistors R1, R2, and R3.
The gate terminal of the transistor MP1 is connected to the gate terminal of the transistor MN1 and the signal ENI.
Optionally, the self-bias current source circuit includes:
transistor Q5, transistor Q6, transistor Q7, transistor Q8, transistor Q9, transistor MP2, transistor MP3, transistor MP4, transistor MP5, transistor MP6, transistor MP9, transistor MN1, transistor MN2, transistor MN3, transistor MN4, transistor MN5, transistor MN6, and transistor MN7, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, resistor R11, and capacitor C1.
The transistors Q6, Q7, Q8, and Q9 are NPN transistors, and the transistor Q5 is a PNP transistor.
Referring to fig. 3 (a), when a circuit start-up current flows in, a PTAT voltage is generated between the emitter of the transistor Q6 and the emitter of the transistor Q7 to act on the resistor R6 to generate a PTAT current, and then the current resistor provides current bias for the subsequent multi-stage op-amp closed-loop circuit, and the resistor has better matching performance with respect to the MOSFET, so the current resistor performs current matching in a manner of improving the equivalent output resistance by adopting the common gate. The self-bias current source circuit starts the band gap self-bias circuit after the band gap starting current flows in to provide bias current for the multistage operational amplifier closed-loop circuit.
In conclusion, the invention has the beneficial effects that:
(one) has better load characteristics
In the bandgap reference circuit, in view of the fact that the conventional bandgap reference circuit utilizes a low-order operational amplifier to improve the stability of the bandgap reference circuit, and the low-order multistage operational amplifier closed-loop circuit has limited contribution in improving the stability of the bandgap reference circuit, the present invention changes the multistage operational amplifier technology to improve the stability of the bandgap reference circuit and improve the loadability, for example, when the output voltage of the bandgap reference is 1.25V, the current of mA magnitude can be achieved.
(II) higher power supply voltage rejection ratio (PSRR) and stability
In the band gap reference circuit of the present invention, a negative feedback control loop is formed by the transistor Q1, the transistor Q2, the transistor MP1, the transistor MP2, the transistor MP3, the transistor MN1, and the transistor MN2, and a bias signal is generated. The transistors MP1, MP2 and MP3 form a current mirror, which is formed by connecting 3, 1 and 4 unit transistors in parallel, and under the same voltage bias condition, the current ratio of the transistors MP1, MP2 and MP3 will be 3:1:4, the current flowing through the transistor Q1 is the sum of the currents of the transistors MP1 and MP2, and the current flowing through the transistor Q2 is the current flowing through the transistor MP3, and the base currents of the transistors Q1 and Q2 are ignored because of the small base currents of the transistors Q1 and Q2, so that the currents I4 and I5 are equal. In addition, the transistors MP1, MP2, MP3, MN1, MN2 together form a cascode current mirror, which is advantageous to suppress fluctuations in the supply voltage by means of a negative feedback mechanism once the supply voltage changes or there is an offset voltage, thereby increasing the supply voltage suppression ratio. That is, the bandgap reference circuit of the present invention has a higher power supply voltage rejection ratio (PSRR) and stability using a negative feedback loop control technique.
(III) have smaller offset voltage
Compared with the traditional band-gap reference voltage source, the band-gap reference voltage source circuit adopts the digital Trim code to control Trim modules to eliminate errors between the regulated reference voltage and the target voltage generated by the band-gap reference circuit under different process conditions, and the band-gap core transistor base electrode current compensation circuit ensures that the band-gap reference voltage is kept consistent under different process angles by compensating the current to the base electrodes of the band-gap core transistor Q12 and the transistor Q13, thereby reducing reference voltage imbalance. For example, under the condition of a full process angle, the output voltage of the band gap reference circuit can be effectively controlled to be 1.25V, and 6Sigma is only 1.5mV under the condition of the full process angle, so that the accuracy of the circuit is greatly improved.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (6)

1. A bandgap reference circuit having high performance, said circuit comprising:
the self-bias current source circuit comprises a band gap core circuit, a multistage operational amplifier closed-loop circuit, a base current compensation circuit, a Trim circuit and a self-bias current source circuit; wherein,,
the self-bias current source circuit is used for outputting bias current according to starting current so as to control the multistage operational amplifier closed-loop circuit to enter a working state;
the multistage operational amplifier closed-loop circuit is used for controlling the band gap core circuit to generate reference voltage;
the base current compensation circuit is used for outputting compensation current to the band gap core circuit;
the base current compensation circuit and the Trim circuit are used for adjusting the reference voltage to be equal to a target voltage so as to obtain a final voltage;
the bandgap core circuit includes:
transistor Q10, transistor Q12, transistor Q13, transistor Q14, and transistor MP12, resistor R13, resistor R14, resistor R15, resistor R16, resistor R17, resistor R18, resistor R19, and resistor R34; wherein,,
the transistors Q10, Q12, Q13 and Q14 are PNP bipolar transistors;
an emitter of the transistor Q12 is connected with an emitter of the transistor Q13 and a drain terminal of the transistor MP 12;
the base electrode of the transistor Q12 is connected with one end of a resistor R15;
the collector of the transistor Q12 is connected with one end of the resistor R16, the base of the transistor Q16 and the collector of the transistor Q19;
the base of the transistor Q13 is connected with the base of the transistor Q14 and the emitter of the transistor Q14;
the collector of the transistor Q13 is connected with the collector of the transistor Q14, the base of the transistor Q15, the collector of the transistor Q20 and one end of the resistor R17;
the other end of the resistor R16 is connected with the other end of the resistor R17 and one end of the resistor R18;
the other end of the resistor R18 is connected with the ground;
the gate terminal of the transistor MP12 is connected with the drain terminal of the transistor MN7, the drain terminal of the transistor MP11, the drain terminal of the transistor MP16 and the gate terminal of the transistor MP 16;
the source end of the transistor MP12 is connected with one end of a resistor R19;
the other end of the resistor R19 is connected with a power supply VDD;
the collector of the transistor Q10 is connected with the collector of the transistor Q11, the base of the transistor Q11, the input terminal REFS of the first circuit module, one end of the capacitor C7, the gate terminal of the transistor MN16, the drain terminal of the transistor MN15, the drain terminal of the transistor MP21, the drain terminal of the transistor MP22, the body terminal of the transistor MP22, and one end of the capacitor C3;
the base electrode of the transistor Q10 is connected with the output end of the second circuit module;
the emitter of the transistor Q10 is connected to the input of the third circuit module.
2. The bandgap reference circuit with high performance according to claim 1, wherein said multi-stage op-amp closed loop circuit comprises:
transistor Q15, transistor Q16, transistor Q17, transistor Q18, transistor Q19, transistor Q20, transistor Q21, transistor Q11, transistor MP17, transistor MP18, transistor MP21, transistor MP22, transistor MP19, transistor MN12, transistor MN13, transistor MN14, and transistor MN15, resistor R12, resistor R24, resistor R23, resistor R22, resistor R20, resistor R21, resistor R25, resistor R26, resistor R27, resistor R28, resistor R29, resistor R30, resistor R31, and resistor R32, capacitor C2, capacitor C3, capacitor C4, capacitor C5, first circuit block, second circuit block; wherein,,
the transistors Q15, Q16, Q19 and Q20 are PNP transistors, and the transistors Q11, Q17, Q18 and Q21 are NPN transistors;
the base electrode of the transistor Q15, the collector electrode of the transistor Q20 and the collector electrode of the transistor Q14 are connected with the collector electrode of the transistor Q13 and one end of the resistor R17;
the base of the transistor Q16 is connected with the collector of the transistor Q12 and one end of the resistor R16;
the emitter of the transistor Q15, the emitter of the transistor Q16 and the drain terminal of the transistor MP14 are connected;
the collector of the transistor Q16, the collector of the transistor Q17, the base of the transistor Q21, and the drain of the transistor MN9 are connected with one end of the capacitor C2 and one end of the resistor R20;
the collector of the transistor Q15, the collector of the transistor Q18, the base of the transistor Q17 and the drain of the transistor MN8 are connected with the other end of the resistor R20;
the gate end of the transistor MP14 is connected with the gate end of the transistor MP8, the gate end of the transistor MP6, the gate end of the transistor MP3, the gate end of the transistor MP2, the gate end of the transistor MP15 and the drain end of the transistor MP 8;
the source terminal of the transistor MP14 is connected with one end of a resistor R21;
the other end of the resistor R21 is connected with a power supply VDD;
the emitter of the transistor Q18, the emitter of the transistor Q17 and the source of the transistor MN8 are connected with ground;
the emitter of the transistor Q21 and the source of the transistor MN9 are connected with the ground VSS;
the collector of the transistor Q21, the drain of the transistor MP15, and the gate of the transistor MN14 are connected with one end of the resistor R29, the capacitor C5, and the drain of the transistor MN 10;
the other end of the resistor R29 is connected with the other end of the capacitor C2;
the source end of the transistor MP15 is connected with one end of a resistor R25;
the other end of the resistor R25 is connected with a power supply VDD;
the gate terminal of the transistor MP16, the drain terminal of the transistor MP16, the gate terminal of the transistor MP17, the gate terminal of the transistor MP18, the drain terminal of the transistor MP19, the drain terminal of the transistor MP11 are connected to the drain terminal of the transistor MN 7;
the source terminal of the transistor MP16 is connected with one end of a resistor R26;
the other end of the resistor R26 is connected with a power supply VDD;
the source terminal of the transistor MP17 is connected to one terminal of the resistor R27;
the other end of the resistor R27 is connected with a power supply VDD;
the drain terminal of the transistor MP17 is connected with the drain terminal of the transistor MN12, the gate terminal of the transistor MN13 and the drain terminal of the transistor MN 11;
the source terminal of the transistor MN12 is connected to one terminal of the resistor R30;
the other end of the resistor R30 is connected with the ground VSS;
the source terminal of the transistor MN13 is connected to one terminal of the resistor R31;
the other end of the resistor R31 is connected with the ground VSS;
the drain terminal of the transistor MN13 is connected with the source terminal of the transistor MN14 and the body terminal of the transistor MN 14;
the drain terminal of the transistor MN14 is connected to the drain terminal of the transistor MP22, the gate terminal of the transistor MP21, the drain terminal of the transistor MP18, the other end of the capacitor C3, and one end of the capacitor C4;
the source terminal of transistor MP18 is connected to one terminal of resistor R28;
the other end of the resistor R28 is connected with a power supply VDD;
the other end of the capacitor C4 is connected with one end of the resistor R32;
the other end of the resistor R32 is connected with a power supply VDD;
the source end of the transistor MP21 is connected with a power supply VDD;
the drain terminal of the transistor MP21 is connected with the source terminal of the transistor MP22, the body terminal of the transistor MP22, the drain terminal of the transistor MN15, the gate terminal of the transistor MN16, one end of the capacitor C3 and one end of the capacitor C7;
the source terminal of the transistor MN15 is connected to the ground VSS;
the other end of the capacitor C7 is connected to ground VSS.
3. The bandgap reference circuit with high performance according to claim 2, wherein the input terminal VDD of said first circuit block is connected to a power supply VDD;
the input terminal REFS of the first circuit block is connected to the gate terminal of the transistor MN 16;
the input end VSS of the first circuit module is connected with ground VSS;
the output end VBG0 of the first circuit module is connected with the input end i0 of the second circuit module;
the output end VBG1 of the first circuit module is connected with the input end i1 of the second circuit module;
the output end VBG2 of the first circuit module is connected with the input end i2 of the second circuit module;
the output end VBG3 of the first circuit module is connected with the input end i3 of the second circuit module;
in the first circuit module:
the input end REFS of the first circuit module is connected with one end of a resistor R34;
the other end of the resistor R34 is connected with one end of the resistor R35 and the output end VBG 0;
the other end of the resistor R35 is connected with one end of the resistor R36 and the output end VBG 1;
the other end of the resistor R36 is connected with one end of the resistor R37 and the output end VBG 2;
the other end of the resistor R37 is connected with one end of the resistor R38 and the output end VBG 3;
the other end of the resistor R38 is connected with the input end VSS;
the input end S1 of the second circuit module is connected with the input end of the first control signal;
the input end S0 of the second circuit module is connected with the second control signal input end;
the input end VDD of the second circuit module is connected with a power supply VDD;
the input end VSS of the second circuit module is connected with ground VSS;
the output OUT of the second circuit block is connected to the base of the transistor Q10.
4. The bandgap reference circuit with high performance according to claim 1, wherein said Trim circuit comprises: a third circuit module; wherein,,
the input end TR <6:0> of the third circuit module is connected with the digital signal Trim code <6:0 >;
the input end VDD of the third circuit module is connected with a power supply VDD;
the input IN of the third circuit module is connected with the emitter of the transistor Q10;
the input end BOT of the third circuit module is connected with one end of a resistor R34;
the input end VSS of the third circuit module is connected with ground VSS;
the output end OUT of the third circuit module is connected with the base electrode of the transistor Q13;
the third circuit module includes: transistor MN17, transistor MN18, transistor MN19, transistor MN20, transistor MN21, transistor MN22, transistor MN23, and transistor MN24, resistor R39, resistor R40, resistor R41, resistor R42, resistor R43, resistor R44, resistor R45, resistor R46, resistor R47, resistor R48, resistor R49, resistor R50, resistor R51, resistor R52, resistor R53, resistor R54, and resistor R55.
5. The bandgap reference circuit with high performance according to claim 1, wherein said base current compensation circuit comprises:
transistors MP1, Q2, Q3, and Q4, and resistors R1, R2, and R3;
the gate terminal of the transistor MP1 is connected to the gate terminal of the transistor MN1 and the signal ENI.
6. The bandgap reference circuit with high performance according to claim 1, wherein said self-biasing current source circuit comprises:
transistor Q5, transistor Q6, transistor Q7, transistor Q8, transistor Q9, transistor MP2, transistor MP3, transistor MP4, transistor MP5, transistor MP6, transistor MP9, transistor MN1, transistor MN2, transistor MN3, transistor MN4, transistor MN5, transistor MN6, and transistor MN7, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, resistor R11, and capacitor C1; wherein,,
the transistors Q6, Q7, Q8, and Q9 are NPN transistors, and the transistor Q5 is a PNP transistor.
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