CN114023745A - Semiconductor structure, preparation method thereof and three-dimensional memory - Google Patents

Semiconductor structure, preparation method thereof and three-dimensional memory Download PDF

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CN114023745A
CN114023745A CN202111274063.2A CN202111274063A CN114023745A CN 114023745 A CN114023745 A CN 114023745A CN 202111274063 A CN202111274063 A CN 202111274063A CN 114023745 A CN114023745 A CN 114023745A
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step structure
photoetching
stacked
etching
steps
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高建峰
刘卫兵
李俊杰
周娜
项金娟
杨涛
李俊峰
罗军
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention discloses a semiconductor structure, a preparation method thereof and a three-dimensional memory, relates to the technical field of three-dimensional memory devices, and provides a technical scheme of a step structure which can reduce photoetching times and has better step side wall appearance. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; sequentially forming N stacked structures which are stacked on the substrate; photoetching and etching the N stacked structures for m times in sequence to obtain a target step structure with N steps; and N is greater than m, and the N and the m meet a preset relation. The semiconductor structure is prepared according to the preparation method of the semiconductor structure. A three-dimensional memory includes the semiconductor structure.

Description

Semiconductor structure, preparation method thereof and three-dimensional memory
Technical Field
The invention relates to the technical field of three-dimensional memory devices, in particular to a semiconductor structure, a preparation method thereof and a three-dimensional memory.
Background
In recent years, Flash Memory (Flash Memory) memories have been developed particularly rapidly. In order to further improve the Bit Density (Bit Density) of the flash memory and simultaneously reduce the Bit Cost (Bit Cost), the three-dimensional flash memory (3D NAND) technology has been rapidly developed. At the same time, substantially the same integration requirements exist for other three-dimensional memory devices.
In the conventional three-dimensional structure, a step region needs to be formed at the periphery of the stacked structure for subsequently etching a contact hole to connect out the gate line. In the step forming process, the photoresist is used as a mask layer, and after the photoresist is transversely etched, the stacked structure is etched. Because the number of the steps is large, in order to reduce the number of times of photoetching and reduce the cost, a photoresist transverse Trim process is mostly adopted, a plurality of steps can be formed under the condition of one-time photoetching, but the photoresist layer can be etched longitudinally while being etched transversely, and the photoresist layer is consumed, so that a thicker photoresist layer needs to be formed, otherwise, the problems that the photoresist layer is consumed too much and the steps are damaged can occur. And when the lateral etching is carried out, the unsmooth side wall is easily generated, which can cause that the roughness of the side wall of the formed step is higher when the photoresist mask pattern is transferred to the lower layer film, and further the accuracy of the step size is influenced.
Disclosure of Invention
The invention aims to provide a semiconductor structure, a preparation method thereof and a three-dimensional memory, and aims to provide a technical scheme of a step structure which can reduce the photoetching times and has better step side wall appearance.
In a first aspect, the present invention provides a method for fabricating a semiconductor structure, comprising the steps of: providing a substrate; sequentially forming N stacked structures which are stacked on a substrate; photoetching and etching the N stacked structures for m times in sequence to obtain a target step structure with N steps; and N is greater than m, and the N and the m meet a preset relation.
Compared with the prior art, the preparation method of the semiconductor structure provided by the invention sequentially carries out photoetching and etching on the N stacked structures for m times to obtain the target step structure with N steps. Therefore, each step in the target step structure is formed by a direct photoetching and etching method, and compared with the prior art, the method has the advantages that the unsmooth side wall is easily generated by adopting the photoresist transverse Trim process, so that the roughness of the side wall of the formed step is higher when the photoresist mask pattern is transferred to a lower layer film, and the accuracy of the step size is further influenced.
Furthermore, the number of steps in the target step structure is greater than the number of times of photoetching, so that the number of times of photoetching can be reduced.
Preferably, the preset relationship is as follows:
N＝2m-1。
preferably, each of the stacked structures includes a first sacrificial layer and a first insulating layer stacked from bottom to top;
or, each stacked structure comprises a first metal layer and a first insulating layer which are stacked from bottom to top.
Preferably, each step in the target step structure is formed by one or more times of photolithography and etching of the corresponding stacked structure.
Preferably, each step at least comprises a second sacrificial layer, and the second sacrificial layer is formed by the first sacrificial layer in the corresponding stacked structure through one or more times of photoetching and etching;
or, each step at least comprises a second metal layer in the corresponding stacked structure, and the second metal layer is formed by the first metal layer in the corresponding stacked structure through one or more times of photoetching and etching.
Preferably, when each of the steps includes at least the second sacrificial layer in the corresponding stack structure, the method for manufacturing a semiconductor structure further includes:
removing the second sacrificial layer in the target step structure;
and forming a third metal layer in the area where the second sacrificial layer is located to obtain a new target step structure.
Preferably, the step of sequentially performing m photolithography and etching on the N stacked structures to obtain a target step structure having N steps includes:
forming first photoetching patterns on the N stacking structures, removing top insulating layers of preset areas of the N stacking structures by taking the first photoetching patterns as masks, and exposing sacrificial layers or metal layers below the top insulating layers of the N stacking structures to obtain first step structures; wherein the preset region corresponds to a region where the target step structure is located;
forming a second photoetching pattern on the first step structure, and etching the first step structure according to the direction from bottom to top by taking the second photoetching pattern as a mask to obtain a second step structure;
forming a third photoetching pattern on the second step structure, and etching the second step structure according to the direction from bottom to top by taking the third photoetching pattern as a mask to obtain a third step structure; the number of steps in the third step structure is 2 times that in the second step structure;
forming a p +1 th photoetching pattern on the p-th step structure, and etching the p-th step structure by taking the p +1 th photoetching pattern as a mask according to the direction from bottom to top to obtain a p +1 th step structure; the number of steps in the p +1 th step structure is 2 times that in the p-th step structure;
until an mth photoetching pattern is formed on the mth-1 step structure, etching the mth-1 step structure according to the direction from bottom to top by taking the mth photoetching pattern as a mask to obtain the target step structure; wherein the number of steps in the target step structure is 2 times the number of steps in the m-1 th step structure; wherein p +1 is less than or equal to m-1.
Preferably, the p +1 th photolithography pattern is formed on a target region of each step of the p-th step structure; wherein, the target area is a partial area where the step is connected with the previous step.
In a second aspect, the invention also provides a semiconductor structure prepared according to the preparation method of the semiconductor structure.
In a third aspect, the present invention also provides a three-dimensional memory, including the above semiconductor structure.
Compared with the prior art, the beneficial effects of the second aspect and the third aspect of the present invention are the same as the beneficial effects of the semiconductor structure provided by the first aspect, and are not described herein again.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic structural diagram of a substrate according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of N stacked structures according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention;
fig. 4-11 are schematic structural diagrams of various stages of a method for fabricating a semiconductor structure according to an embodiment of the invention.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In recent years, Flash Memory (Flash Memory) memories have been developed particularly rapidly. In order to further improve the Bit Density (Bit Density) of the flash memory and simultaneously reduce the Bit Cost (Bit Cost), the three-dimensional flash memory (3D NAND) technology has been rapidly developed. At the same time, substantially the same integration requirements exist for other three-dimensional memory devices.
In the conventional three-dimensional structure, a step region needs to be formed at the periphery of the stacked structure for subsequently etching a contact hole to connect out the gate line. In the step forming process, the photoresist is used as a mask layer, and after the photoresist is transversely etched, the stacked structure is etched. Because the number of the steps is large, in order to reduce the number of times of photoetching and reduce the cost, a photoresist transverse Trim process is mostly adopted, a plurality of steps can be formed under the condition of one-time photoetching, but the photoresist layer can be etched longitudinally while being etched transversely, and the photoresist layer is consumed, so that a thicker photoresist layer needs to be formed, otherwise, the problems that the photoresist layer is consumed too much and the steps are damaged can occur. And when the lateral etching is carried out, the unsmooth side wall is easily generated, which can cause that the roughness of the side wall of the formed step is higher when the photoresist mask pattern is transferred to the lower layer film, and further the accuracy of the step size is influenced.
Based on this, in a first aspect, an embodiment of the present invention discloses a method for manufacturing a semiconductor structure, including the following steps:
referring to fig. 1, a substrate 10 is provided.
In order to reduce the manufacturing cost of the semiconductor structure, the substrate 10 may be a semiconductor substrate such as a silicon substrate or a silicon germanium substrate. The substrate 10 may be an SOI (Silicon-On-Insulator) substrate without considering cost, which is not particularly limited in the embodiment of the present invention.
Referring to fig. 2, N stacked structures 20 are sequentially formed on the substrate 10 in a stacked arrangement.
Each stack structure 20 includes a first sacrificial layer and a first insulating layer stacked from bottom to top. Alternatively, each of the stacked structures includes a first metal layer and a first insulating layer stacked from bottom to top. Referring to fig. 2, 201 may be a first sacrificial layer or a first metal layer. 202 is a first insulating layer.
The first metal layer may be a word line metal layer. The word line metal layer is used for forming steps in the follow-up process, then the steps are etched to form etching contact holes, and the contact holes are used for leading out control electrode word lines so as to achieve the function of a three-dimensional memory device.
Referring to fig. 3, performing lithography and etching on the N stacked structures m times in sequence to obtain a target step structure 30 having N steps; and N is greater than m, and the N and the m meet a preset relation.
Referring to fig. 3, it can be seen that each of the steps includes at least a second sacrificial layer formed by one or more of photolithography and etching from the first sacrificial layer in the corresponding stack structure. Each step further includes a second insulating layer, which may be formed by performing photolithography etching on the first insulating layer in the lower stacked structure adjacent to the stacked structure.
Or, each step at least comprises a second metal layer in the corresponding stacked structure, and the second metal layer is formed by the first metal layer in the corresponding stacked structure through one or more times of photoetching and etching. Each step further includes a second insulating layer, which may be formed by performing photolithography etching on the first insulating layer in the lower stacked structure adjacent to the stacked structure.
Further, when each step includes at least the second sacrificial layer in the corresponding stacked structure, the method for manufacturing the semiconductor structure further includes:
removing the second sacrificial layer in the target step structure; in the semiconductor structure, the thickness of the second sacrificial layer is very small, so that, in practice, the second sacrificial layer in the target step structure can be removed by a dry etching method.
And forming a third metal layer in the area where the second sacrificial layer is located to obtain a new target step structure. It will be appreciated that this new target step structure is the final desired step structure.
In a preferred embodiment, the preset relationship satisfied by N and m may be N-2m-1。
It can be seen that, when the number of steps in the target step structure is 8, the embodiment of the present invention needs to perform 4 steps of photolithography and etching. By analogy, the embodiment of the invention can form a step structure with 16 steps by 5 times of photoetching; 6 times of photoetching can form a step structure with 32 steps; 7 times of photoetching can form a step structure with 64 steps; the 8 times of photoetching can form a step structure with 128 steps; the step structure with 256 steps can be formed by 9 times of photoetching, the photoetching times are greatly reduced, the preparation process is simplified, and particularly for the step structure with more step layers, the preparation method of the semiconductor structure provided by the embodiment of the invention can show more excellent simplified process effect.
The following describes in detail a method for manufacturing a semiconductor structure according to an embodiment of the present invention, taking a target step structure with 8 steps as an example:
referring to fig. 4, a first photolithography pattern 401 is formed on the N stacked structures. Wherein the process of forming the first photolithography pattern may include: first photoresist is formed on the N stacked structures, and a first photo-etching pattern 401 is obtained after the first photoresist is exposed, developed, and the like. The first lithography pattern is required to expose a region of the N stacked structures where a target step structure is to be subsequently formed.
Referring to fig. 5, the top insulating layers of the preset regions of the N stacked structures are removed by using the first lithography pattern as a mask to expose the sacrificial layers or the metal layers under the top insulating layers of the N stacked structures, and then the first lithography pattern is removed to obtain the first step structure 501. And the preset area corresponds to the area where the target step structure is located.
Referring to fig. 6, a second photolithography pattern 402 is formed on the first step structure 501. The process of forming the second lithography pattern 402 may include: a second photoresist is formed on the first step structure 501, and the second photoresist is exposed and developed to obtain a second lithography pattern 402. The second lithography pattern 402 is required to expose the region of the first step structure where the step is required to be formed by the lithography etching.
Referring to fig. 7, the second lithography pattern 402 is used as a mask, the first step structure is etched from bottom to top, and then the second lithography pattern 402 is removed to obtain a second step structure 502. And the number of the step layers in the second step structure is 2.
Referring to fig. 8, a third photolithography pattern 403 is formed on the second step structure 502. The process of forming the third lithography pattern 403 may include: a third photoresist is formed on the second step structure 502, and the third photoresist is exposed and developed to obtain a third photoresist pattern 403. The third lithography pattern 403 is required to expose the region of the second step structure 502 where the step is required to be formed by the lithography etching.
Referring to fig. 9, the third lithography pattern 403 is used as a mask, the second step structure is etched from bottom to top, and then the third lithography pattern 403 is removed to obtain a third step structure 503; wherein, the number of steps in the third step structure 503 is 2 times that in the second step structure. It can be seen that the number of step layers in the third step structure 503 is 4.
Referring to fig. 10, a fourth photolithography pattern 404 is formed on the third step structure 503. The process of forming the fourth lithography pattern 404 may include: a fourth photoresist is formed on the third step structure 503, and the fourth photoresist is exposed and developed to obtain a fourth photo-etching pattern 404. The fourth lithography pattern 404 is required to expose the region of the third step structure 503 where the step is required to be formed by the lithography etching.
Referring to fig. 11, the fourth lithography pattern 404 is used as a mask, the third step structure is etched in a bottom-up direction, and then the fourth lithography pattern 404 is removed to obtain a fourth step structure 504; the number of steps in the fourth step structure 504 is 2 times of the number of steps in the third step structure. It can be seen that the number of step layers in the fourth step structure is 8.
So far, the target step structure with 8 steps is obtained through four times of photoetching and etching.
It will be appreciated that in practice, when a relatively large number of lithography passes is required to obtain a desired number of steps in the target step structure, the intermediate steps may be performed as follows:
forming a p +1 th photolithographic pattern on the p-th step structure, wherein the process of forming the p +1 th photolithographic pattern may include: and forming a P +1 th photoresist on the P-th step structure, and carrying out operations such as exposure, development and the like on the P +1 th photoresist to obtain a P +1 th photoetching pattern. The p +1 th photoetching pattern needs to expose the region of the p-th step structure where the step needs to be formed in the photoetching.
Etching the p-th step structure by taking the p + 1-th photoetching pattern as a mask according to the direction from bottom to top, and then removing the p + 1-th photoetching pattern to obtain a p + 1-th step structure; wherein, the number of steps in the p +1 th step structure is 2 times of the number of steps in the p-th step structure.
Then, carrying out photoetching etching on the step structure according to the mode until an mth photoetching pattern is formed on the (m-1) th step structure, and etching the (m-1) th step structure according to the direction from bottom to top by taking the mth photoetching pattern as a mask to obtain the target step structure; and the number of steps in the target step structure is 2 times of the number of steps in the m-1 step structure, and at the moment, the target step structure of the required layer step is obtained. Wherein p +1 is less than or equal to m-1.
Notably, in the manufacturing process of the semiconductor structure, a p +1 th photolithography pattern is formed on a target region of each step of the p-th step structure; wherein, the target area is a partial area where the step is connected with the previous step. At this time, it can be ensured that the step structure extending downward can be formed after the corresponding insulating layer is removed to expose the metal layer or the sacrificial layer, that is, based on this, the height of the middle step of the target step structure formed later can be higher than the step of the next layer and lower than the step of the previous layer, so as to ensure the preparation of the step structure.
Based on this, the method for manufacturing a semiconductor structure provided by the embodiment of the invention sequentially performs lithography and etching on the N stacked structures m times to obtain a target step structure having N steps. Therefore, each step in the target step structure is formed by direct photoetching and etching, and compared with the prior art, the method has the advantages that the process of adopting the photoresist transverse Trim is easy to generate unsmooth side walls, so that the roughness of the side walls of the formed steps is higher when the photoresist mask pattern is transmitted to a lower layer film downwards, and the accuracy of the dimension of the steps is further influenced.
Furthermore, the number of steps in the target step structure is greater than the number of times of photoetching, so that the number of times of photoetching can be reduced.
In a second aspect, the embodiment of the invention also discloses a semiconductor structure, which is prepared according to the preparation method of the semiconductor structure in the first aspect.
The beneficial effects of the semiconductor structure in the embodiment of the present invention are the same as those of the semiconductor structure in the first aspect, and are not described herein again.
In a third aspect, an embodiment of the invention further discloses a three-dimensional memory, which includes the semiconductor structure provided in the second aspect.
The beneficial effects of the three-dimensional memory in the embodiment of the present invention are the same as those of the semiconductor structure in the second aspect, and are not described herein again.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (10)

1. A method for manufacturing a semiconductor structure, the method comprising:
providing a substrate;
sequentially forming N stacked structures which are stacked on the substrate;
photoetching and etching the N stacked structures for m times in sequence to obtain a target step structure with N steps; and N is greater than m, and the N and the m meet a preset relation.
2. The method of claim 1, wherein the predetermined relationship is:
N＝2m-1。
3. the method for manufacturing a semiconductor structure according to claim 1, wherein each of the stacked structures includes a first sacrificial layer and a first insulating layer which are stacked from bottom to top;
or, each stacked structure comprises a first metal layer and a first insulating layer which are stacked from bottom to top.
4. The method of claim 3, wherein each step in the target step structure is formed from at least the corresponding stacked structure by one or more of photolithography and etching.
5. The method for manufacturing a semiconductor structure according to claim 3, wherein each step comprises at least a second sacrificial layer formed by one or more times of photolithography and etching on the first sacrificial layer in the corresponding stacked structure;
or, each step at least comprises a second metal layer in the corresponding stacked structure, and the second metal layer is formed by the first metal layer in the corresponding stacked structure through one or more times of photoetching and etching.
6. The method of claim 5, wherein when each of the steps includes at least the second sacrificial layer in the corresponding stack structure, the method further comprises:
removing the second sacrificial layer in the target step structure;
and forming a third metal layer in the area where the second sacrificial layer is located to obtain a new target step structure.
7. The method for preparing a semiconductor structure according to any one of claims 1 to 6, wherein the step of sequentially performing the lithography and etching on the N stacked structures m times to obtain a target step structure having N steps comprises:
forming first photoetching patterns on the N stacking structures, removing top insulating layers of preset areas of the N stacking structures by taking the first photoetching patterns as masks, and exposing sacrificial layers or metal layers below the top insulating layers of the N stacking structures to obtain first step structures; wherein the preset region corresponds to a region where the target step structure is located;
forming a second photoetching pattern on the first step structure, and etching the first step structure according to the direction from bottom to top by taking the second photoetching pattern as a mask to obtain a second step structure;
forming a third photoetching pattern on the second step structure, and etching the second step structure according to the direction from bottom to top by taking the third photoetching pattern as a mask to obtain a third step structure; the number of steps in the third step structure is 2 times that in the second step structure;
forming a p +1 th photoetching pattern on a p-th step structure, and etching the p-th step structure by taking the p +1 th photoetching pattern as a mask according to the direction from bottom to top to obtain a p +1 th step structure; the number of steps in the p +1 th step structure is 2 times that in the p-th step structure;
until an mth photoetching pattern is formed on the mth-1 step structure, etching the mth-1 step structure according to the direction from bottom to top by taking the mth photoetching pattern as a mask to obtain the target step structure; wherein the number of steps in the target step structure is 2 times the number of steps in the m-1 th step structure;
wherein p +1 is less than or equal to m-1.
8. The method for fabricating a semiconductor structure according to claim 7, wherein the p +1 th photolithography pattern is formed on a target region of each step of the p-th step structure; wherein, the target area is a partial area where the step is connected with the previous step.
9. A semiconductor structure prepared according to the method of any one of claims 1 to 8.
10. A three-dimensional memory comprising the semiconductor structure of claim 9.
CN202111274063.2A 2021-10-29 2021-10-29 Semiconductor structure, preparation method thereof and three-dimensional memory Pending CN114023745A (en)

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