CN114023688A

CN114023688A - Method for improving uniformity of step height in process

Info

Publication number: CN114023688A
Application number: CN202111226639.8A
Authority: CN
Inventors: 李博文; 王昌锋; 马雁飞
Original assignee: Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Current assignee: Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority date: 2021-10-21
Filing date: 2021-10-21
Publication date: 2022-02-08

Abstract

The invention provides a method for improving the step height uniformity in the process, wherein STI trenches are arranged between active regions; a first SiN layer is formed on the active region; filling oxide in the STI trench, wherein the oxide covers the first SiN layer on the active region; annealing the oxide-filled STI trench; the first chemical mechanical polishing is used for flattening the oxide on the STI trench; forming a second SiN layer on the planarized oxide; carrying out second chemical mechanical polishing on the second SiN layer to flatten the surface of the second SiN layer; etching the second SiN layer and the oxide until the upper surface of the first SiN layer is exposed; keeping the height of the oxide consistent with that of the upper surface of the first SiN layer; and selecting an etching condition that the etching ratio of the oxide to the first SiN layer is greater than 1, and etching the oxide to make the heights of the first SiN layers on the plurality of active regions consistent. The invention improves the inconsistency of the step heights between different graph structures by STI twice CMP processes so as to improve the window of the later process and improve the performance of the device.

Description

Method for improving uniformity of step height in process

Technical Field

The invention relates to the technical field of semiconductors, in particular to a method for improving the uniformity of step height in a process.

Background

The Step Height (Step Height) uniformity formed by different structures in the prior art is mainly adjusted by STI planarization (CMP), and the Step heights of different Pattern structures (Pattern loading) are different due to the CMP process characteristics, so that the phenomenon of Height inconsistency is generated when polycrystalline silicon falls on active regions and STI regions of different Pattern structures in the subsequent process, and the electrical result of a device is influenced.

Therefore, a new method is needed to solve the above problems.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for improving uniformity of step height in a process, which is used to solve the problem of affecting device performance due to the difference of step heights of different pattern structures in the prior art.

To achieve the above and other related objects, the present invention provides a method for improving step height uniformity in a process, comprising:

providing a wafer, wherein a plurality of active regions are arranged on the wafer, and STI (shallow trench isolation) grooves are arranged between the active regions; a first SiN layer is formed on the active region; filling the STI trench with an oxide, and the oxide covering over the first SiN layer on the active region; then annealing the STI trench filled with the oxide;

step two, carrying out first chemical mechanical polishing to planarize the oxide on the STI trench;

step three, forming a second SiN layer on the planarized oxide;

fourthly, carrying out second chemical mechanical polishing on the second SiN layer to flatten the surface of the second SiN layer;

fifthly, etching the second SiN layer and the oxide until the upper surface of the first SiN layer is exposed; and keeping the oxide and the upper surface of the first SiN layer in consistent height;

and sixthly, selecting an etching condition that the etching ratio of the oxide to the first SiN layer is larger than 1, and etching the oxide to enable the heights of the first SiN layers on the plurality of active regions to be consistent.

Preferably, in the first step, before the oxide is filled in the STI trench, a thin oxide layer is formed on the STI trench and the active region; the thin oxide layer on the active region is located below the first SiN layer.

Preferably, the method for etching the second SiN layer and the oxide in the fifth step is dry etching.

Preferably, in the dry etching in the fifth step, an etching ratio of the second SiN layer to the oxide is close to 1: 1.

Preferably, the etching in the sixth step is dry etching.

As described above, the method for improving the uniformity of the step height in the process of the present invention has the following beneficial effects: the invention improves the inconsistency of the step heights between different graph structures by STI twice CMP processes so as to improve the window of the later process and improve the performance of the device.

Drawings

FIG. 1 is a schematic structural diagram of an STI trench disposed between a plurality of active regions according to the present invention;

FIG. 2 is a schematic structural diagram of an oxide after a first CMP process in accordance with the present invention;

FIG. 3 is a schematic diagram illustrating a second SiN layer on an oxide layer according to the present invention;

FIG. 4 is a schematic view of a second SiN layer after a second CMP in accordance with the present invention;

FIG. 5 is a schematic diagram illustrating a structure of the present invention after etching a second SiN layer and an oxide to expose an upper surface of the first SiN layer;

FIG. 6 is a schematic diagram illustrating a structure of the present invention for etching oxide and first SiN layers to make the heights of the first SiN layers on multiple active regions consistent;

FIG. 7 is a flow chart of a method for improving step height uniformity in a process according to the present invention.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 7. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

The invention provides a method for improving uniformity of step height in a process, as shown in fig. 7, fig. 7 is a flow chart of the method for improving uniformity of step height in a process, the method at least comprises the following steps:

providing a wafer, wherein a plurality of active regions are arranged on the wafer, and STI (shallow trench isolation) grooves are arranged between the active regions; a first SiN layer is formed on the active region; filling the STI trench with an oxide, and the oxide covering over the first SiN layer on the active region; then annealing the STI trench filled with the oxide; as shown in fig. 1, fig. 1 is a schematic structural diagram of a wafer having a plurality of active regions 01 and STI trenches 03 between the active regions 01 in the first step, where the STI trenches are formed between the active regions 01; a first SiN layer 04 is formed on the active region 01; filling the STI trench with an oxide 02, wherein the oxide 02 covers the first SiN layer 04 on the active region 01; then annealing (Anneal) the STI trench 03 filled with the oxide 02;

further, in the first step of this embodiment, before the STI trench 03 is filled with the oxide 02, a thin oxide layer 05 is formed on the STI trench 03 and the active region 01; the thin oxide layer 05 on the active region is located below the first SiN layer 04.

Step two, carrying out first chemical mechanical polishing to planarize the oxide on the STI trench; as shown in fig. 2, fig. 2 is a schematic structural view of the oxide after the first chemical mechanical polishing in the present invention. In the second step, a first Chemical Mechanical Polishing (CMP) is performed to planarize the oxide 02 on the STI trench, and the planarization in the second step is the planarization that is the largest possible.

Step three, forming a second SiN layer on the planarized oxide; as shown in fig. 3, fig. 3 is a schematic structural diagram of the present invention after forming a second SiN layer on an oxide, and in this step, the second SiN layer 06 is formed on the planarized oxide 02.

Fourthly, carrying out second chemical mechanical polishing on the second SiN layer to flatten the surface of the second SiN layer; as shown in fig. 4, fig. 4 is a schematic structural view of the second SiN layer after the second chemical mechanical polishing, in the fourth step, the second SiN layer 06 is subjected to the second chemical mechanical polishing to planarize the surface thereof, and the planarization in the fourth step refers to the planarization with the greatest possible degree.

Fifthly, etching the second SiN layer and the oxide until the upper surface of the first SiN layer is exposed; and keeping the oxide and the upper surface of the first SiN layer in consistent height; as shown in fig. 5, fig. 5 is a schematic structural view illustrating the second SiN layer and the oxide layer etched until the upper surface of the first SiN layer is exposed. Etching the second SiN layer and the oxide 02 until the upper surface of the first SiN layer 04 is exposed; and the oxide 02 is kept in conformity with the height of the upper surface of the first SiN layer 04.

Further, in the present invention, in the fifth step of this embodiment, a method for etching the second SiN layer and the oxide is dry etching.

Further, in the dry etching in step five of this embodiment, the etching ratio of the second SiN layer to the oxide is close to 1: 1.

And sixthly, selecting an etching condition that the etching ratio of the oxide to the first SiN layer is larger than 1, and etching the oxide to enable the heights of the first SiN layers on the plurality of active regions to be consistent. As shown in FIG. 6, FIG. 6 is a schematic structural view illustrating the oxide and first SiN layers etched according to the present invention to make the heights of the first SiN layers on the plurality of active regions consistent.

Further, the etching in step six of this embodiment is dry etching.

In summary, the invention improves the step height inconsistency between different pattern structures by STI twice CMP processes, so as to improve the window of the later process and improve the performance of the device. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A method for improving uniformity of step height in a process, comprising:

step three, forming a second SiN layer on the planarized oxide;

2. The method of claim 1, wherein the step height uniformity in the process is further characterized by: firstly, before the STI trench is filled with the oxide, a thin oxide layer is formed on the STI trench and the active region; the thin oxide layer on the active region is located below the first SiN layer.

3. The method of claim 1, wherein the step height uniformity in the process is further characterized by: and fifthly, the method for etching the second SiN layer and the oxide is dry etching.

4. The method of claim 3, wherein the step height uniformity is further characterized by: in the dry etching in the fifth step, the etching ratio of the second SiN layer to the oxide is close to 1: 1.

5. The method of claim 1, wherein the step height uniformity in the process is further characterized by: and the etching in the sixth step is dry etching.