CN114023277A

CN114023277A - Chip on film, GOA driving method and display device

Info

Publication number: CN114023277A
Application number: CN202111225015.4A
Authority: CN
Inventors: 田婷; 石爽; 许梦兴; 王珍; 杜育锋; 舒兴军; 杨胜伟; 高宗丽; 安娜; 杨瑞锋; 李志�
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Priority date: 2021-10-19
Filing date: 2021-10-19
Publication date: 2022-02-08
Anticipated expiration: 2041-10-19
Also published as: CN114023277B

Abstract

The application discloses a chip on film, a GOA driving method and a display device, which comprise a plurality of pins arranged in an array, wherein each pin comprises a signal terminal and a redundant terminal, and a plurality of pins arranged adjacently form a first pin area, wherein the signal terminal in the first pin area is a double-pin signal, and the adjacent pins in the double-pin signal correspond to the same signal; the two sides of the first pin area are the redundant terminals respectively. According to the chip on film provided by the embodiment of the application, the arrangement mode of the pins is optimized, the metal corrosion of the binding region is reduced, and the voltage difference between the pins and the duration time of the high voltage difference are reduced; the time sequence of the driving signal is optimized, so that the optimization effect is further improved, and the defects caused by metal corrosion are avoided; the problem of abnormal display of a high-frequency product under high temperature and high humidity reliability is solved under the condition of not influencing the charging rate, and the reliability of the product is improved.

Description

Chip on film, GOA driving method and display device

Technical Field

The present disclosure relates generally to the field of display technologies, and in particular, to a chip on film, a GOA driving method, and a display device.

Background

In recent years, the market occupation rate of high refresh rate mobile phone products is gradually increasing in order to pursue more stable pictures, smoother dynamic picture performance and better game experience. However, a high frame rate means that the display time per frame is reduced, the charging time of pixels is reduced with the resolution being unchanged, and there may be a problem that the charging time is insufficient at a high frame rate. In order to solve the problem of insufficient charging of pixels, the driving voltage of a product is increased at present, and the charging speed of pixels is increased.

However, when the driving voltage is increased, metal Ni ions in ACF conductive adhesive in a Bonding pin with a COF Bonding position at a high potential are easy to generate electrochemical corrosion Ni-2e ═ Ni ^2+ in a high-temperature and high-humidity (85 ℃, 85% R.H.) environment, so that Ni plating is lost, and due to the fact that the area of the COF Bonding pin is small, the width of the current commonly-used pin is 12 micrometers, the gap is 18 micrometers, the length is only 0.4mm, the number of conductive particles is limited, and the product is failed under the action of a long time.

Disclosure of Invention

In view of the above-mentioned defects or shortcomings in the prior art, it is desirable to provide a chip on film, a GOA driving method and a display device, which can effectively solve the problem of product failure caused by metal corrosion at the Bonding position when the PPI is high.

In a first aspect, the present application provides a chip on film comprising a plurality of pins arranged in an array, the pins comprising signal terminals and redundant terminals, a plurality of adjacently arranged pins forming a first pin field, wherein,

the signal terminals in the first pin area are double-pin signals, and adjacent pins in the double-pin signals correspond to the same signal;

the two sides of the first pin area are the redundant terminals respectively.

Optionally, at least one of two sides of the dual pin signal in the first pin area is the redundant terminal.

Optionally, a high level ratio of each signal terminal in the first pin field is greater than a first threshold, where the high level ratio is a time ratio that a signal is at a high level compared with an adjacent signal in one frame time.

Optionally, the signal terminal of the first pin field comprises one or more of CN, VGH, VCOM.

Optionally, the device further includes a second pin area formed by a plurality of pins arranged adjacently, the redundant terminals are respectively arranged on two sides of the second pin area, a high level ratio of the second pin area is smaller than that of the first pin area, and high level ratios of the signal terminals in the second pin area are all larger than a second threshold.

Optionally, the signal terminal of the second pin field includes one or more of EN _ TOUCH, CNB.

Optionally, the signal line further includes a third pin area formed by a plurality of pins disposed adjacent to each other, the redundant terminal is disposed on at least one side of the third pin area, and a high level ratio of each signal terminal in the third pin area is greater than a third threshold.

Optionally, the signal terminals in the third pin field include one or more of CK, CKB, MUXR.

Optionally, two adjacent pin areas share the same redundant pin at adjacent positions.

Optionally, the redundant terminal is in a high impedance state or a high level state.

In a second aspect, the present application provides a chip on film row driving method, which employs the chip on film as described in any one of the above, the method including:

in the display stage of a frame of image, controlling a first voltage end input by a scanning signal of the current stage of the GOA unit to be a high level signal, a second voltage end input by a scanning signal of the next stage to be a low level signal, and a touch control enabling end input by a touch control signal to be a low level signal;

in the touch control stage of a frame of image, a first voltage end input by a scanning signal of the current stage of the GOA unit is controlled to be a low level signal, a second voltage end input by a scanning signal of the next stage is controlled to be a low level signal, and a touch control enabling end input by the touch control signal is controlled to be a high level signal.

Optionally, the method further comprises:

inserting partial low voltage time sequence in the high-frequency driving time sequence to realize low-frequency driving, specifically comprising:

in a blanking stage of a frame of image, a first voltage end input by a scanning signal of the current stage of the GOA unit is controlled to be a low level signal, a second voltage end input by a scanning signal of the next stage is controlled to be a low level signal, and a touch enable end input by a touch signal is controlled to be a low level signal.

In a third aspect, the present application provides a display device comprising a flip-chip film as described in any of the above.

The technical scheme provided by the embodiment of the application can have the following beneficial effects:

according to the chip on film provided by the embodiment of the application, the arrangement mode of the pins is optimized, the metal corrosion of the binding region is reduced, and the voltage difference between the pins and the duration time of the high voltage difference are reduced; the time sequence of the driving signal is optimized, so that the optimization effect is further improved, and the defects caused by metal corrosion are avoided; the problem of abnormal display of a high-frequency product under high temperature and high humidity reliability is solved under the condition of not influencing the charging rate, and the reliability of the product is improved.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

fig. 1 is a schematic view of a display device provided in an embodiment of the present application;

FIG. 2 is an element map of a binding region provided by an embodiment of the present application;

fig. 3 is a schematic view illustrating a position of a chip on film according to an embodiment of the present application;

FIG. 4 is a schematic diagram of the location of a pin distribution in the prior art;

fig. 5 is a schematic diagram of a location of a pin distribution provided by an embodiment of the present application;

FIG. 6 is a timing diagram corresponding to FIG. 4;

FIG. 7 is a signal timing diagram corresponding to FIG. 5;

FIG. 8 is a timing diagram of a redundancy signal provided by an embodiment of the present application;

fig. 9 is a schematic diagram of a GOA circuit according to an embodiment of the present disclosure;

fig. 10 is a schematic diagram of a GOA cascade according to an embodiment of the present disclosure;

FIG. 11 is another timing diagram of signals provided by an embodiment of the present application;

FIG. 12 is a timing diagram of the comparison signals of FIG. 11.

Detailed Description

The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

The display panel is bonded during preparation, and the display panel is mainly formed by connecting a panel, a Chip On Film (COF), a Flexible Printed Circuit (FPC) and the like together through a golden finger, so that the panel has functions of electrifying, displaying, touching and the like. The COF (Chip on Film) technology usually manufactures a driving circuit on a Chip On Film (COF), and the Chip on Film is directly connected with a display panel to electrically connect the driving circuit and the display panel. The COG technology generally requires an IC (Integrated Circuit) to be bonded On a display panel, and generally uses a COG (Chip On Glass, Chip fixed On a Glass substrate) bonding method to electrically connect the IC and a lead On the Glass substrate. In the examples of the present application, COF is exemplified.

Bonding, also called Bonding or binding, in the Bonding process, a layer of ACF (Anisotropic Conductive Film) is covered on the Bonding structure, then the control circuit board and the display substrate are aligned and vacuum-absorbed, and the connection is realized by the connection ends of the ACF and the display substrate through a butt joint pressure heating mode to achieve a solidification joint.

In the conventional high PPI product, for example, when all signals are pulled high during GOA driving, the TFT is in an on state, and the voltage is VGH voltage, at present, +10V (in the embodiment of the present application, the +10V is exemplarily described and other potentials, such as +9V, may also be included) may be used to ensure the charging rate at high frequency, and when the signals are pulled low, the TFTs are in an off state, and the voltage is VGL voltage, and-8V is used. As the high frequency of 120Hz is needed, the driving voltage VGH of the product is raised from +8V of the original low frequency to +10V, and the turn-off voltage of GOA (Gate Driver on Arra; array substrate row driving technology) still keeps-8V. The high voltage difference of 10V or 18V exists between part of Bonding pins and peripheral pins, the voltage difference lasts for a long time, and poor display of the screen is generated in high-temperature and high-humidity operation.

Through analysis, few Bonding particles are found at a high-voltage pin part of a COF Bonding position, and the phenomenon of Ni coating loss is found in ACF slicing, so that the Bonding resistance is increased finally, IC signals cannot be transmitted to the interior of a panel, and abnormal display is caused. According to the actual product defect, the voltage difference is weighted more heavily in the defect, and then the holding time of the high voltage difference, fig. 1 is the slicing result of the actual defective product, fig. 2 is the element map of the actual defect, and the defect of the Ni plating layer can be clearly seen from fig. 2.

Please refer to fig. 3 in detail, a chip on film includes a plurality of pins arranged in an array, the pins include signal terminals and redundant terminals DUMMY, a plurality of pins arranged adjacently form a first pin area D1, wherein the signal terminals in the first pin area D1 are dual-pin signals 10, and the adjacent pins in the dual-pin signals 10 correspond to the same signal; the two sides of the first pin area D1 are the redundant terminals DUMMY, respectively.

At least one of two sides of the two-pin signal 10 in the first pin field D1 is the redundant terminal DUMMY. It should be noted that, in the embodiment of the present application, the two-pin signal 10 is a group of two adjacent signal pins, and the same input or output signal is provided in one group of the two adjacent signal pins. The two-pin signal 10 may be a power supply terminal, a first power supply terminal VGH, and a second power supply terminal VGL, which adopt two pins in the pins of the existing COF, or may be a signal terminal whose high-level occupation ratio is higher than a first threshold value, which is set as the two-pin signal 10 according to the design principle of the present application.

For example, in the prior art, the first voltage terminal CN of the GOA unit is set to be a single pin, in the embodiment of the present application, the first voltage terminal is set to be a double pin, that is, two adjacent pins serve as signal terminals of the first voltage terminal. By arranging the signal with higher high-level ratio in the prior art in one area, the voltage difference between two adjacent pins and the duration of the high voltage difference can be effectively reduced, and metal corrosion at a binding position is prevented.

In the embodiment of the present application, a high level ratio of each of the signal terminals in the first pin field D1, which is a time ratio of a signal to an adjacent signal at a high level in one frame time, is greater than a first threshold. It should be noted that, in the embodiment of the present application, the high level is a logic high level, and is a comparison between two adjacent signals, the level of the signal is higher than the level of the other signal, and the level of the signal has 2 state quantities, which does not represent that the high level and the low level have specific values throughout the text. That is, the high level ratio is a time ratio in which the level of the signal is higher than the level of the adjacent signal in one frame time.

For example, when the high level time ratio exceeds 70% within one frame time, a signal having a pull-up time greater than 12ms is designed using a double pin with a time period of 60Hz and is disposed within the first pin zone D1. It should be noted that, when the refresh rate is different, different threshold values may be adopted, and in the embodiment of the present application, the threshold values are merely exemplary, and the present application is not limited to the values.

Optionally, the signal terminal of the first pin field D1 includes one or more of CN, VGH, VCOM. It should be noted that the signals of the first pin field D1 in the embodiment of the present application include, but are not limited to, the above three types, and in different device and application scenarios, other signal terminals may also be included, and of course, the three exemplary signal terminals may also not be included.

For example, if the high ratio of the signal terminals CN and VGH of the first pin field D1 both exceed the first threshold, the pin order in the first pin field D1 may be set as DUMMY/CN/VGH/DUMMY. If the pin has a space and cannot insert too many DUMMY signals, the long and high signals can be arranged together, and the arrangement can be preferably set as DUMMY/CN/DUMMY/VGH/DUMMY.

It should be noted that, in the embodiment of the present application, it is preferable to adopt the two-pin signal 10, in the case of adopting the two-pin signal 10, it is considered that the redundant terminals DUMMY are provided on the left and right sides of the two-pin signal 10, and in the case of pin limitation, it is also considered that the two-pin signal is provided only on the two sides of the first pin zone D1.

Fig. 4 shows a partial distribution diagram of a pin in a bonding region in the prior art, and fig. 5 shows a distribution diagram of the pin in the prior art optimized by the technical solution of the present application. FIG. 6 is a driving timing of a portion of signals corresponding to the pin distribution of FIG. 4; fig. 7 is a driving timing of a part of signals corresponding to the pin distribution of fig. 5.

For the first voltage terminal CN, a dual-pin configuration is not adopted in the prior art, as shown in fig. 6, so that in the frame rate Real 120Hz or 60Hz state, the CN signal is always in a pull-up state, the voltage difference between the CN signal and the peripheral signals is 10V, and the retention time reaches 16.67ms with 60Hz as a time period, so that the problem of CN signal abnormality occurs in the reliability test in the prior art. In the embodiment of the present application, a double pin design is used for a signal in a pull-up state for a long time, such as a CN signal, as shown in fig. 5, and a DUMMY signal is added to both sides to ensure a binding state after reliability. The design is in a pass state in the reliability test, and the approval of the client is obtained.

In this embodiment, the device further includes a second pin area D2 formed by a plurality of pins disposed adjacently, the redundant terminals DUMMY are disposed on two sides of the second pin area D2, a high level ratio of the second pin area D2 is smaller than a high level ratio of the first pin area D1, and a high level ratio of each signal terminal in the second pin area D2 is greater than a second threshold.

It should be noted that, in the embodiment of the present application, the pin in the second pin area D2 may be a two-pin signal 10 or a single-pin signal. For example, common voltage terminal VCOM of the two-pin signal 10, EN _ TOUCH of the single-pin signal. One signal or multiple signals may be included in the region, which is not limited in this application. In the area, if a plurality of signals are included, the redundant terminals DUMMY may be provided at both ends of each signal, and in the case where the pin is limited, the redundant terminals DUMMY may be provided only at both ends of the area.

Illustratively, the second threshold is that the high time fraction exceeds 40% in one frame time, and a signal with a pull-up time of more than 7ms requires a double-sided addition of DUMMY signal design, such as EN _ TOUCH signal, with a time period of 60 Hz.

In the prior art, both sides of the EN _ TOUCH signal are valid signals, as shown in fig. 5, one side is the CLK signal and one side is the MUXR signal, the voltage difference between the CLK signal and the signals on the two sides of the periphery is always kept at 18V, and the holding time of the signal at the high voltage difference reaches 7.75ms (the frame time of the frame rate of 60Hz is taken as the total time), so that the reject rate of the EN _ TOUCH signal reaches 21.9% at the frame rate.

According to the embodiment of the application, the DUMMY signal is added on both sides of the EN _ TOUCH signal, the DUMMY signal is set to be in a high-impedance state, the voltage difference between the signal and the peripheral signal is reduced, and the signal passes through both the client and the factory in the reliability test, so that the approval of the client is obtained.

Optionally, the signal terminal of the second pin field D2 includes one or more of EN _ TOUCH, CNB. It should be noted that the signals of the second pin field D2 in the embodiment of the present application include, but are not limited to, the above, and in different device and application scenarios, other signal terminals may also be included, and of course, the various exemplary signal terminals may also not be included.

In the embodiment of the present application, the module further includes a third pin area D3 formed by a plurality of pins disposed adjacently, the redundant terminal DUMMY is disposed on at least one side of the third pin area D3, and a high-level ratio of each signal terminal in the third pin area D3 is greater than a third threshold.

Illustratively, the third threshold is that the high-level time accounts for more than 24% in one frame time, and signals with 60Hz pull-down time longer than 4ms require one-sided addition of DUMMY signal designs, such as MUXR signals and the like.

When the frame rate is Real 120Hz or 60Hz, in the prior art, the pressure difference between the MUXR signal and the peripheral signal is 18V, the holding time is 4.17ms, and the holding time is longest in the pressure difference of 18V, so that the problem of the MUXR signal NG exists under the reliability in the mode. According to the embodiment of the application, the DUMMY signal is added on the single side of the MUXR, the problem that the Ni plating layer disappears in the actual reliability is solved, and the authentication of a client is passed.

Optionally, the signal terminals in the third pin field D3 include one or more of CK, CKB, MUXR. It should be noted that the signals of the third pin field D3 in the embodiment of the present application include, but are not limited to, the above, and in different device and application scenarios, other signal terminals may also be included, and of course, the various exemplary signal terminals may also not be included.

Through carrying out the subregion through the difference according to the high level time ratio to the pin of different signals in this application, to the higher signal of high level ratio adopt the setting of double pin and set up redundant terminal DUMMY at the both ends of two pin signal 10, to the signal adoption that the high level ratio is inferior and set up redundant terminal DUMMY at the both ends of subregion respectively, to the signal of lower high level ratio, can adopt and only set up redundant terminal DUMMY in one side.

Based on the inventive concept of the present application, it is possible to make appropriate adjustments according to the limitation of the number of different pins, for example, in the case of limited pins, two adjacent pin areas share the same redundant pin at adjacent positions. By reducing the high level difference between the pins and the duration time of the high level difference, metal corrosion under a high-temperature and high-humidity environment is effectively prevented, the reliability of the product is improved, and the performance of the product is ensured.

It should be noted that, in the embodiment of the present application, the number of each partition in the first pin field D1, the second pin field D2, and the third pin field D3 may be one or more, and the number of redundant pins may be reduced by the adjacent pin fields and pin fields. The number of pins in each pin area is not limited, and the pin area can be optimally set according to the total number of pins. For example, since a plurality of signal terminals are disposed in the second pin area D2, since the high level ratio of each signal terminal is close, the voltage difference between adjacent pins or the duration of the high voltage difference can be reduced to reduce metal corrosion.

For example, the number of redundant terminals DUMMY can be reduced by distributing the plurality of signal terminals originally provided in the second pin area D2 in two areas, and locating the two areas on both sides of the second pin area D2. This is applicable to situations where pin is limited. The above is an exemplary illustration, and the inventive concept of the present application can be implemented by setting different partitions.

In one embodiment of the present application, the redundancy terminal DUMMY is in a high impedance state or a high level state. The high impedance state may be set to pin floating. The pin is suspended, the signal measured voltage is about 0V, and the yield is greatly improved. The method can avoid the phenomenon that the CN signal and the signal pressure difference on the two sides are in a high voltage difference state for a long time when other low-level signals are accessed, and effectively avoids the bad CN. Fig. 8 shows waveforms corresponding to the redundant terminal at low level (DUMMY VGL), high impedance state (DUMMY Hiz), and high level (DUMMY VGH).

In addition, the DUMMY signal may be set to a high level state in which the difference between the signal in a pulled-up state for a long period of time, such as the CN signal, and the DUMMY signal is maintained at 0V, and electrochemical corrosion does not occur. For the signal with high or low state of EN _ TOUCH/MUXR, when the signal is in a pull-down state, the DUMMY signal is high, the signal generating electrochemical corrosion is the DUMMY signal, and the product performance is not influenced because the DUMMY pin is not connected with an effective signal; when the device is in a pull-up state, the difference between the voltage and the DUMMY signal is 0V, and electrochemical corrosion does not exist.

It should be noted that, in the embodiment of the present application, the signals accessed to the redundant terminals DUMMY at different positions may be set to different signals, for example, a high level in the VGH state is accessed at both ends of the CN terminal, and the redundant terminals DUMMY in the high impedance state are set at both sides of the signal with the high or low state, such as EN _ TOUCH/MUXR.

In the embodiment of the present application, the GOA (Gate Driver on Array) technology is a Gate driving circuit technology that is most commonly used in the display panel at present, and the Gate driving circuit is directly integrated on the Array substrate of the display panel through a photolithography process. The preparation method of the GOA in the embodiment of the present application may adopt a scheme in the prior art, and is not described herein again. The GOA circuit may be a specific GOA unit such as 2T1C, 3T1C, 6T1C, 7T1C, 8T1C, and the application is not limited thereto.

Fig. 9 is a schematic circuit diagram of an 11T2C GOA unit of a touch display panel provided in an embodiment of the present application, where the GOA unit has two clock signal terminals CK and CKB, two input signal terminals STV and RESET, and two voltage terminals CN and CNB. The signal CK and the signal CKB are complementary signals, VGL is a dc low level signal, and the first voltage terminal CN and the second voltage terminal CNB are control voltage terminals for implementing positive and negative scanning.

Fig. 10 is a schematic diagram of a GOA circuit formed by cascading a plurality of GOA units shown in fig. 1, where STV of a GOA unit is connected to an output OUT of a GOA unit in a previous stage, and RESET is connected to an output of a GOA unit in a next stage. The GOA circuit can realize positive and negative scanning, specifically, if CN is high level and CNB is low level, the GOA circuit realizes positive scanning, and STV is a signal input end of the positive scanning; if CN is low level and CNB is high level, the GOA circuit implements reverse scanning, and RESET is the signal input end of the reverse scanning.

In this embodiment, the GOA unit further includes a TOUCH enable signal EN _ TOUCH, the nth level GOA unit enters a TOUCH stage after outputting an OUTPUT signal, the display stage enters again after the TOUCH stage is finished, and the N +1 th level GOA unit continues to OUTPUT an OUTPUT _ N +1 signal.

It should be noted that, in the embodiment of the present application, the GOA unit may further include other signal terminals, such as a first INPUT terminal INPUT1, a second INPUT terminal INPUT2, a gate output terminal GOUT, an enable output terminal EOUT, a first signal terminal GCK, a second signal terminal GCB, a third signal terminal ECK, a fourth signal terminal ECB, a first power source terminal VGH, and a second power source terminal VGL. The present application is not repeated herein, and different signal terminals may be selected according to different devices and different application scenarios.

In the display process, a gate scanning signal is output through the GOA circuit, each pixel unit is scanned and accessed row by row (or column by column or in other preset modes), the GOA circuit is used for generating the gate scanning signal of the pixel unit, each GOA unit is used as a shift register to transmit the gate scanning signal to the next GOA unit in sequence, and TFT switches are turned on row by row to complete data signal input of the pixel unit.

The application provides a chip on film line driving method, which adopts the chip on film as described in any one of the above, and the method comprises the following steps: as shown in figure 7 of the drawings,

in a Touch control phase Touch of a frame of image, a first voltage end input by a scanning signal of the current stage of the GOA unit is controlled to be a low level signal, a second voltage end input by a scanning signal of the next stage is controlled to be a low level signal, and a Touch control enable end input by the Touch control signal is controlled to be a high level signal.

In the research of the application, it is found that another important factor of the missing of the Ni plating layer is that the duration of the high voltage difference is long, so that it can be considered to reduce the pull-up time of the high voltage signal so as to reduce the probability of the missing of the Ni plating layer. When the frame rate is Real 120Hz or 60Hz, as shown in fig. 8, compared with fig. 5, the CN/CNB performs pull-down in Touch interval to reduce pull-up time of signal, and in the regression verification, the Timing optimization sequence is used, and all pass the authentication of the client.

The display screen needs to display at different refresh frequencies based on different application scenes of the terminal of the whole machine, for example, a common picture is displayed at a refresh frequency of 60Hz, a game mode is displayed at a refresh frequency of 120Hz or higher, and other application scenes need to be displayed at a refresh frequency of 90Hz or other frequencies.

Optionally, the method further comprises:

and inserting part of low-voltage time sequence in the high-frequency driving time sequence to realize low-frequency driving, and providing a corresponding number of display pulses to corresponding pixel driving circuits for different refreshing frequencies in each display driving period.

In the embodiment of the present application, the blanking period is set after the display period and the touch period are completed for one frame of image, the blanking period is inserted, and the high-frequency waveform during the high-frequency driving is replaced by the blanking period, so that the driving modes in the display period and the touch period are not changed in the high-frequency period and the low-frequency period. The conversion from a high-frequency signal to a low-frequency signal is realized, the blanking stage is inserted in the rear time sequence of one frame of image, the conversion between the high frequency and the low frequency can be effectively and quickly realized, the brightness difference or the screen flashing phenomenon does not exist, only the number of display pulses is changed, the GOA time sequence does not need to be switched, and the change of the writing time of a data signal is not caused.

The method specifically comprises the following steps:

as shown in fig. 11, in the blanking period of one frame of image, the first voltage terminal of the current-stage scanning signal input of the GOA unit is controlled to be a low-level signal, the second voltage terminal of the next-stage scanning signal input is controlled to be a low-level signal, and the touch enable terminal of the touch signal input is controlled to be a low-level signal.

In the present application, a blanking phase is inserted into one frame of image, so as to implement a conversion between a high frequency and a low frequency, for example, a 120Hz high frequency driving is converted into a 60Hz mode through an in-out blanking phase, in this embodiment, in the blanking phase, a signal is adjusted, as shown in fig. 11, compared with fig. 12, CN/CNB is pulled down in a Touch interval, so as to reduce the pull-up time of the signal, in this mode, the pull-up time of the CN signal can be reduced by about 8ms, so as to greatly reduce the speed of the CN signal electrochemical corrosion; the EN _ TOUCH signal is pulled low in the Porch interval, and the pull-up time is reduced by about 7 ms.

In addition, in order to further reduce metal corrosion of the GOA in the bonding area, a mode of reducing a routing load may be further adopted, and by reducing the voltage value of the first power source terminal VGH, the voltage difference between the pin and the pin may also be reduced by reducing the VGH driving voltage under the condition that the charging rate is satisfied.

And correspondingly, the arrangement rule is optimized in the binding area of the FPC by referring to the arrangement mode of pins of the chip on film. This application is not described in detail herein.

The present application also provides a display device comprising the above flip-chip film.

The display device may specifically include at least a liquid crystal display device and an organic light emitting diode display device, for example, the touch display device may be any product or component with a display function, such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.

It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, as used herein, refer to an orientation or positional relationship indicated in the drawings that is solely for the purpose of facilitating the description and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and is therefore not to be construed as limiting the invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

Unless defined otherwise, technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Terms such as "disposed" and the like, as used herein, may refer to one element being directly attached to another element or one element being attached to another element through intervening elements. Features described herein in one embodiment may be applied to another embodiment, either alone or in combination with other features, unless the feature is otherwise inapplicable or otherwise stated in the other embodiment.

The present invention has been described in terms of the above embodiments, but it should be understood that the above embodiments are for purposes of illustration and description only and are not intended to limit the invention to the scope of the described embodiments. It will be appreciated by those skilled in the art that many variations and modifications may be made to the teachings of the invention, which fall within the scope of the invention as claimed.

Claims

1. A chip on film comprises a plurality of pins arranged in an array, and is characterized in that the pins comprise signal terminals and redundant terminals, a plurality of pins arranged adjacently form a first pin area, wherein,

the two sides of the first pin area are the redundant terminals respectively.

2. The COF of claim 1, wherein at least one of two sides of said two-pin signal in said first pin field is said redundant terminal.

3. The chip on film according to claim 1, wherein a high level ratio of each of the signal terminals in the first pin field is greater than a first threshold, and the high level ratio is a time ratio in which a signal is at a high level compared with an adjacent signal in one frame time.

4. The chip on film of claim 1, wherein the signal terminals of the first pin field comprise one or more of CN, VGH, CTSWVCOM.

5. The chip on film of claim 1, further comprising a second pin area formed by a plurality of pins disposed adjacently, wherein the redundant terminals are disposed on two sides of the second pin area, a high level ratio of the second pin area is smaller than that of the first pin area, and a high level ratio of each signal terminal in the second pin area is greater than a second threshold.

6. The chip on film of claim 5, wherein the signal terminals of the second pin field comprise one or more of EN _ TOUCH, CNB.

7. The chip on film according to claim 1, further comprising a third lead area formed by a plurality of leads disposed adjacent to each other, wherein at least one side of the third lead area is disposed with the redundant terminal, and a high-level ratio of each of the signal terminals in the third lead area is greater than a third threshold.

8. The chip on film of claim 7, wherein the signal terminals in the third pin field comprise one or more of CK, CKB, MUXR.

9. The COF of claim 1, wherein two adjacent lead areas share the same redundant lead at adjacent locations.

10. The chip on film of claim 1, wherein the redundant terminal is in a high impedance state or a high level state.

11. A GOA driving method, wherein the chip on film according to any one of claims 1 to 10 is used, the method comprising:

12. The GOA driving method according to claim 11, further comprising:

in a blanking stage of a frame of image, the first voltage end of the GOA unit is controlled to be a low level signal, the second voltage end of the GOA unit is controlled to be a low level signal, and the touch control enabling end of the GOA unit is controlled to be a low level signal.

13. A display device comprising the flip-chip film according to any one of claims 1 to 10.