CN114020344A - Bus resource reservation method, device, equipment and storage medium - Google Patents
Bus resource reservation method, device, equipment and storage medium Download PDFInfo
- Publication number
- CN114020344A CN114020344A CN202210007514.4A CN202210007514A CN114020344A CN 114020344 A CN114020344 A CN 114020344A CN 202210007514 A CN202210007514 A CN 202210007514A CN 114020344 A CN114020344 A CN 114020344A
- Authority
- CN
- China
- Prior art keywords
- bus
- configuration information
- vga
- shared memory
- root port
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000012986 modification Methods 0.000 claims description 23
- 230000004048 modification Effects 0.000 claims description 23
- 238000004590 computer program Methods 0.000 claims description 15
- 241001290266 Sciaenops ocellatus Species 0.000 claims description 6
- 238000013507 mapping Methods 0.000 claims description 3
- 238000007726 management method Methods 0.000 abstract description 24
- 238000013468 resource allocation Methods 0.000 abstract description 14
- 230000000694 effects Effects 0.000 abstract description 3
- 238000004891 communication Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4403—Processor initialisation
Abstract
The application discloses a bus resource reservation method, device, equipment and storage medium. The method comprises the following steps: adding bus configuration information to a VGA shared memory associated with a substrate management controller; the bus configuration information comprises the bus number corresponding to each root port of the CPU; initializing VGA equipment where the VGA shared memory is located in a first stage of a basic input/output system; and at a second stage after the first stage of the basic input and output system, carrying out bus resource configuration on each root port according to the bus configuration information in the VGA shared memory. The bus number configuration can be directly carried out on each root port in the CPU according to the bus configuration information stored in the VGA shared memory when the basic input and output system carries out the first bus resource configuration, so that the bus reservation scheme can be started and taken effect at one time without extra restarting, and the bus resource allocation efficiency is improved.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a method, an apparatus, a device, and a storage medium for reserving bus resources.
Background
In the starting process of a server BIOS, 0-255 total 256 BUS (BUS) resources are allocated to all Root ports (Root ports) of a CPU by Intel, and the resources are allocated to the Root ports according to a default average allocation mode, but in practical application, different devices are connected below each Root Port, and the required BUS resources are greatly different, for example, a NVME disk with 4X 4 bandwidth is connected below the Root Port with a bandwidth X16, so that the Root Port only needs to reserve 4 BUSs to be enough, and an intelligent network card with 1X 16 bandwidth is connected below the Root Port with another bandwidth X16, but the network card may virtualize nearly 100 network ports, and the Root Port needs to reserve 100 BUSs to support the normal operation of the network card. Therefore, the reserved BUS is a very important technology for adjusting the distribution of the CPU Root Port Bus, but in the field of the current server, the adopted method for reserving the BUS is generally adjusted according to the difference of PCIE equipment models connected below the Root ports, and because the action of judging the BUS resources required by taking the equipment by the equipment models needs to pass the stage of CPU BUS resource initialization after PCIE equipment enumeration, the method needs to be restarted once and takes effect in the second starting, and once new equipment or original equipment is connected below another Root Port, BIOS needs to issue a new version for support, so that the maintenance is very inconvenient.
In the prior art, the CPU reserves resources by first acquiring resource information of each PCIE device corresponding to the server, then determining a maximum resource demand of the PCIE device according to the resource information, changing the resource demand reserved by the PCIE bridge into the maximum resource demand, and finally performing resource allocation according to the 32-bit resource type and the maximum resource demand that can be prefetched. However, the resources required to be reserved for the CPU are obtained by reading the PCIE device configuration space, which is performed after the PCIE device enumeration and passes through the stage of CPU resource allocation, so that a restart is required to perform resource allocation according to the maximum resource demand, which causes resource waste and reduces the efficiency of resource allocation; secondly, the method does not support the maximum resource quantity required by the out-of-band CPU, and the method is changed completely according to the type of the PCIE equipment, so that the method has great limitation. Therefore, how to improve the efficiency of reserving bus resources is a problem that needs to be solved.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a method, an apparatus, a device and a medium for reserving bus resources, which can improve the efficiency of bus resource allocation. The specific scheme is as follows:
in a first aspect, the present application discloses a method for reserving bus resources, including:
adding bus configuration information to a VGA shared memory associated with a substrate management controller; the bus configuration information comprises the bus number corresponding to each root port of the CPU;
initializing VGA equipment where the VGA shared memory is located in a first stage of a basic input/output system;
and at a second stage after the first stage of the basic input and output system, carrying out bus resource configuration on each root port according to the bus configuration information in the VGA shared memory.
Optionally, before adding the bus configuration information to the VGA shared memory associated with the baseboard management controller, the method further includes:
acquiring default bus configuration parameters corresponding to the CPU to obtain the bus configuration information; the default bus configuration parameters include a default bus number corresponding to each root port of each CPU.
Optionally, before initializing the VGA device in which the VGA shared memory is located in the first stage of the basic input output system, the method further includes:
acquiring a modification request sent by a user in an out-of-band mode according to a target protocol through the baseboard management controller;
and modifying the bus configuration information according to the modification request to configure the corresponding current target bus number for the target root port of the CPU.
Optionally, the modification request includes a modification command or a modification file in a target format; the target format is a file storage format corresponding to the bus configuration information; the target protocol comprises an intelligent platform management interface protocol and a redfish protocol.
Optionally, the configuring bus resources for each root port according to the bus configuration information in the VGA shared memory includes:
judging whether the bus configuration information contains the current target bus number or not;
and if the bus configuration information contains the current target bus number, performing bus resource configuration for the corresponding root port according to the current target bus number.
Optionally, after determining whether the bus configuration information includes the current target bus number, the method further includes:
and if the bus configuration information does not contain the current target bus number, performing bus resource configuration for the corresponding root port according to the default bus number.
Optionally, at a second stage after the first stage of the basic input output system, performing bus resource configuration for each root port according to the bus configuration information in the VGA shared memory, including:
at a second stage after the first stage of the basic input and output system, reading the bus configuration information in the VGA shared memory in a memory mapping I/O mode;
and carrying out bus resource configuration for each root port according to the bus configuration information.
In a second aspect, the present application discloses a bus resource reservation apparatus, including:
the bus configuration information adding module is used for adding bus configuration information to the VGA shared memory associated with the substrate management controller; the bus configuration information comprises the bus number corresponding to each root port of the CPU;
the initialization module is used for initializing VGA equipment where the VGA shared memory is located in the first stage of a basic input/output system;
and the bus resource configuration module is used for performing bus resource configuration on each root port according to the bus configuration information in the VGA shared memory at a second stage after the first stage of the basic input and output system.
In a third aspect, the present application discloses an electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the aforementioned bus resource reservation method.
In a fourth aspect, the present application discloses a computer readable storage medium for storing a computer program; wherein the computer program when executed by a processor implements the aforementioned bus resource reservation method.
In the application, bus configuration information is added to a VGA shared memory associated with a baseboard management controller; the bus configuration information comprises the bus number corresponding to each root port of the CPU; initializing VGA equipment where the VGA shared memory is located in a first stage of a basic input/output system; and at a second stage after the first stage of the basic input and output system, carrying out bus resource configuration on each root port according to the bus configuration information in the VGA shared memory. Therefore, by storing the bus configuration information in the VGA shared memory associated with the substrate management controller, the basic input/output system can obtain the configuration information of the reserved bus resources corresponding to the root port of the CPU by accessing the VGA shared memory before the bus resource configuration is performed for the first time, and thus, when the bus resource configuration is performed for the first time, the bus number configuration can be directly performed for each root port of the CPU according to the bus configuration information stored in the VGA shared memory, so that the bus reservation scheme is activated and validated at one time without additional restart, and the efficiency of bus resource allocation is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a bus resource reservation method provided in the present application;
fig. 2 is a flowchart of a specific bus resource reservation method provided in the present application;
FIG. 3 is a schematic diagram of specific bus configuration information provided herein;
fig. 4 is a schematic structural diagram of a bus resource reservation apparatus provided in the present application;
fig. 5 is a block diagram of an electronic device provided in the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the prior art, the CPU reserves resources by first acquiring resource information of each PCIE device corresponding to the server, and then determining the maximum resource demand of the PCIE device according to the resource information, and performing resource allocation according to the resource type and the maximum resource demand that can be prefetched. However, the resources required to be reserved for the CPU are obtained by reading the PCIE device configuration space, which is performed after the PCIE device enumeration, and the stage of CPU resource allocation has already passed, so that resource allocation is performed according to the maximum resource demand by restarting at certain time, which causes resource waste and reduces the efficiency of resource allocation. In order to overcome the technical problem, the application provides a method for reserving bus resources based on a VGA shared memory associated with a baseboard management controller, which can improve the efficiency of bus resource allocation.
The embodiment of the application discloses a bus resource reservation method, and as shown in fig. 1, the method may include the following steps:
step S11: adding bus configuration information to a VGA shared memory associated with a substrate management controller; the bus configuration information includes the number of buses corresponding to each root port of the CPU.
In this embodiment, a VGA (Video Graphics Array) shared memory associated with a Baseboard Management Controller (BMC) is used to store BUS configuration information, where the BUS configuration information includes the number of buses corresponding to each Root Port of the CPU, that is, the number of buses reserved for each Root Port of the CPU, and the BUS configuration information may be specifically stored in the shared memory in a JSON format, that is, the BMC stores the number of buses reserved for each Root Port of the CPU in a JSON file manner in the VGA shared memory.
In this embodiment, before adding the bus configuration information to the VGA shared memory associated with the baseboard management controller, the method may further include: acquiring default bus configuration parameters corresponding to the CPU to obtain the bus configuration information; the default bus configuration parameters include a default bus number corresponding to each root port of each CPU. That is, the bus configuration information may be a default bus configuration parameter corresponding to the current CPU, including a default bus number corresponding to each root port of each CPU, where the current CPU may be one or more.
In this embodiment, before initializing the VGA device in which the VGA shared memory is located in the first stage of the basic input output system, the method may further include: acquiring a modification request sent by a user in an out-of-band mode according to a target protocol through the baseboard management controller; and modifying the bus configuration information according to the modification request to configure the corresponding current target bus number for the target root port of the CPU. For example, as shown in fig. 2, after acquiring the default bus number corresponding to each root port, the user may further send a modification request for the bus configuration information by using an out-of-band method according to a target protocol through the baseboard management controller, so that the baseboard management controller modifies the bus configuration information according to the modification request, so that the target root port configuration bus number of the CPU in the bus configuration information is the currently required target bus number, where the target root port may be all root ports of the CPU or a part of root ports. For example, fig. 3 is a schematic diagram showing a specific storage format of BUS configuration information in a VGA shared memory at a BMC end, taking an Intel latest whitley platform icelabel CPU as an example, each CPU has 5 Root ports, on a two-way server, a first column is a position of a Root Port, specifically, a CPU0 Root ports 0-Port4 and a CPU1 Root ports 0-Port4, a second column is a number of buses to be allocated by default, and a third column is a number of currently reserved buses to be modified for a user.
In this embodiment, the modification request may include a modification command or a modification file in a target format; the target format can be a file storage format corresponding to the bus configuration information; the target protocol may include an Intelligent Platform Management Interface (IPMI) protocol and a redfish protocol. The reserved BUS number of a specific Root Port in the BUS configuration information file can be set by the BMC in an out-of-band mode, and the reserved BUS number can be modified by a command or by a mode of importing a JSON file. For example, a user needs to reserve 100 buses on the CPU0 Root Port1 and 80 buses on the CPU1 Root Port3, that is, the number of reserved buses can be modified out of band as shown in fig. 3, and the buses are concentrated under the Root ports with demands by reasonably adjusting the distribution of BUS resources, and the Root ports without demands can distribute a small number of buses. The number of reserved BUSs of the Root ports of the CPU is stored in a VGA shared memory of the BMC in a JSON file mode, and the modification of a user through an IPMI or redfish or other out-of-band protocols is supported, so that the user can modify the reserved BUSs according to requirements before starting up no matter which Root Port the equipment needing to reserve BUSs is connected under, and the flexibility of modifying the reserved parameters of the BUS resources is improved.
Step S12: and initializing the VGA equipment in which the VGA shared memory is positioned in the first stage of the basic input and output system.
In this embodiment, after the BUS configuration information is stored in the VGA shared memory of the baseboard management controller, a Basic Input Output System (BIOS) initializes the VGA device in which the VGA shared memory is located in a first stage of operation, it can be understood that, in an early stage of startup, the BIOS initializes the BMC-associated VGA device before BUS allocation of the CPU Root is completed, so that the BMC-associated VGA device can access the VGA device, and the initialization step is executed immediately after startup, so that the BIOS can be guaranteed to read the BUS configuration information before BUS resource configuration is performed, thereby ensuring that a BUS reservation scheme in the BUS resource configuration is valid when a startup is performed.
Step S13: and at a second stage after the first stage of the basic input and output system, carrying out bus resource configuration on each root port according to the bus configuration information in the VGA shared memory.
In this embodiment, after initializing the BMC VGA device, the bios performs bus resource configuration for each root port according to bus configuration information in the VGA shared memory. It can be understood that before the initialization of the CPU, the BIOS obtains the number of Root Port reserved buses of the CPU by accessing the BMC VGA shared memory, and then the BIOS allocates the number of reserved buses to the Root ports in the CPU.
In this embodiment, the performing, at a second stage after the first stage of the basic input output system, bus resource configuration for each root port according to the bus configuration information in the VGA shared memory may include: at a second stage after the first stage of the basic input and output system, reading the bus configuration information in the VGA shared memory in a memory mapping I/O mode; and carrying out bus resource configuration for each root port according to the bus configuration information. That is, the BIOS may read the content of the JSON file in the VGA shared Memory in a Memory-mapped I/O (MMIO) manner.
In this embodiment, the performing bus resource configuration for each root port according to the bus configuration information in the VGA shared memory may include: judging whether the bus configuration information contains the current target bus number or not; and if the bus configuration information contains the current target bus number, performing bus resource configuration for the corresponding root port according to the current target bus number. And if the bus configuration information does not contain the current target bus number, performing bus resource configuration for the corresponding root port according to the default bus number. To illustrate by taking fig. 3 as an example, after the BIOS reads the bus configuration information in the VGA shared memory, it determines whether the current target bus number in the third row changes from the default bus number in the second row; if yes, the BIOS distributes BUS to Root ports in the CPU according to the requirement of the current target BUS number of the third column in the JSON file; otherwise, the BIOS allocates BUS to the Root Port of the CPU according to the default BUS number in the JSON file, namely, the default average allocation mode.
Therefore, through fully utilizing the VGA shared memory associated with the BMC, the BIOS can be initialized and accessed in the early stage of starting, the BIOS reads the reserved BUS quantity required by a user firstly, then initializes the BUS resources of the CPU, so that the requirement of the reserved BUS can be started once and takes effect immediately, the BIOS is not required to be restarted once again in the starting process, in addition, interfaces for setting the reserved BUS quantity out of band of the user reserved by the BMC are very flexible, the content in the VGA shared memory can be set out of band by protocols such as IPMI and Redfish, and when the user wants to adjust the reserved BUS quantity, the BIOS is not required to be changed, and the realization can be realized by only sending an out-of-band command.
As can be seen from the above, in this embodiment, bus configuration information is added to the VGA shared memory associated with the baseboard management controller; the bus configuration information comprises the bus number corresponding to each root port of the CPU; initializing VGA equipment where the VGA shared memory is located in a first stage of a basic input/output system; and at a second stage after the first stage of the basic input and output system, carrying out bus resource configuration on each root port according to the bus configuration information in the VGA shared memory. Therefore, by storing the bus configuration information in the VGA shared memory associated with the substrate management controller, the basic input/output system can obtain the configuration information of the reserved bus resources corresponding to the root port of the CPU by accessing the VGA shared memory before the bus resource configuration is performed for the first time, and thus, when the bus resource configuration is performed for the first time, the bus number configuration can be directly performed for each root port of the CPU according to the bus configuration information stored in the VGA shared memory, so that the bus reservation scheme is activated and validated at one time without additional restart, and the efficiency of bus resource allocation is improved.
Correspondingly, an embodiment of the present application further discloses a bus resource reservation apparatus, as shown in fig. 4, the apparatus includes:
the bus configuration information adding module 11 is used for adding bus configuration information to the VGA shared memory associated with the baseboard management controller; the bus configuration information comprises the bus number corresponding to each root port of the CPU;
the initialization module 12 is configured to initialize VGA equipment in which the VGA shared memory is located in a first stage of a basic input/output system;
a bus resource configuration module 13, configured to perform, at a second stage after the first stage of the basic input/output system, bus resource configuration for each root port according to the bus configuration information in the VGA shared memory.
As can be seen from the above, in this embodiment, bus configuration information is added to the VGA shared memory associated with the baseboard management controller; the bus configuration information comprises the bus number corresponding to each root port of the CPU; initializing VGA equipment where the VGA shared memory is located in a first stage of a basic input/output system; and at a second stage after the first stage of the basic input and output system, carrying out bus resource configuration on each root port according to the bus configuration information in the VGA shared memory. Therefore, by storing the bus configuration information in the VGA shared memory associated with the substrate management controller, the basic input/output system can obtain the configuration information of the reserved bus resources corresponding to the root port of the CPU by accessing the VGA shared memory before the bus resource configuration is performed for the first time, and thus, when the bus resource configuration is performed for the first time, the bus number configuration can be directly performed for each root port of the CPU according to the bus configuration information stored in the VGA shared memory, so that the bus reservation scheme is activated and validated at one time without additional restart, and the efficiency of bus resource allocation is improved.
In some specific embodiments, the bus resource reservation device may specifically include:
a default bus configuration parameter obtaining unit, configured to obtain a default bus configuration parameter corresponding to the CPU, so as to obtain the bus configuration information; the default bus configuration parameters include a default bus number corresponding to each root port of each CPU.
In some specific embodiments, the bus resource reservation device may specifically include:
a modification request acquisition unit, configured to acquire, by the baseboard management controller, a modification request sent by a user in an out-of-band manner according to a target protocol;
and the modifying unit is used for modifying the bus configuration information according to the modifying request so as to configure the corresponding current target bus number for the target root port of the CPU.
In some embodiments, the modification request may specifically include a modification command or a modification file in a target format; the target format may specifically be a file storage format corresponding to the bus configuration information; the target protocol may specifically include an intelligent platform management interface protocol and a redfish protocol.
In some specific embodiments, the bus resource configuration module 13 may specifically include:
the judging unit is used for judging whether the bus configuration information contains the current target bus number or not;
and the first bus resource configuration unit is used for configuring bus resources for the corresponding root port according to the current target bus number if the bus configuration information contains the current target bus number.
In some specific embodiments, the bus resource configuration module 13 may specifically include:
and the second bus resource configuration unit is configured to, if the bus configuration information does not include the current target bus number, perform bus resource configuration for the corresponding root port according to the default bus number.
In some specific embodiments, the bus resource configuration module 13 may specifically include:
a reading unit, configured to read the bus configuration information in the VGA shared memory in a memory mapped I/O manner at a second stage after the first stage of the basic input output system;
and the configuration unit is used for carrying out bus resource configuration on each root port according to the bus configuration information.
Further, the embodiment of the present application also discloses an electronic device, which is shown in fig. 5, and the content in the drawing cannot be considered as any limitation to the application scope.
Fig. 5 is a schematic structural diagram of an electronic device 20 according to an embodiment of the present disclosure. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input output interface 25, and a communication bus 26. Wherein, the memory 22 is used for storing a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the bus resource reservation method disclosed in any of the foregoing embodiments.
In this embodiment, the power supply 23 is configured to provide a working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and an external device, and a communication protocol followed by the communication interface is any communication protocol applicable to the technical solution of the present application, and is not specifically limited herein; the input/output interface 25 is configured to obtain external input data or output data to the outside, and a specific interface type thereof may be selected according to specific application requirements, which is not specifically limited herein.
In addition, the storage 22 is used as a carrier for resource storage, and may be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc., the resources stored thereon include an operating system 221, a computer program 222, data 223 including bus configuration information, etc., and the storage may be a transient storage or a permanent storage.
The operating system 221 is used for managing and controlling each hardware device and the computer program 222 on the electronic device 20, so as to realize the operation and processing of the mass data 223 in the memory 22 by the processor 21, and may be Windows Server, Netware, Unix, Linux, and the like. The computer program 222 may further include a computer program that can be used to perform other specific tasks in addition to the computer program that can be used to perform the bus resource reservation method performed by the electronic device 20 disclosed in any of the foregoing embodiments.
Further, an embodiment of the present application further discloses a computer storage medium, where computer-executable instructions are stored in the computer storage medium, and when the computer-executable instructions are loaded and executed by a processor, the steps of the bus resource reservation method disclosed in any of the foregoing embodiments are implemented.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The method, the apparatus, the device and the medium for reserving bus resources provided by the present invention are described in detail above, and a specific example is applied in the present document to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A method for reserving bus resources, comprising:
adding bus configuration information to a VGA shared memory associated with a substrate management controller; the bus configuration information comprises the bus number corresponding to each root port of the CPU;
initializing VGA equipment where the VGA shared memory is located in a first stage of a basic input/output system;
and at a second stage after the first stage of the basic input and output system, carrying out bus resource configuration on each root port according to the bus configuration information in the VGA shared memory.
2. The method for reserving bus resources according to claim 1, wherein before adding the bus configuration information to the VGA shared memory associated with the baseboard management controller, the method further comprises:
acquiring default bus configuration parameters corresponding to the CPU to obtain the bus configuration information; the default bus configuration parameters include a default bus number corresponding to each root port of each CPU.
3. The method for reserving bus resources as claimed in claim 2, wherein before initializing the VGA device in which the VGA shared memory is located in the first phase of the basic input output system, the method further comprises:
acquiring a modification request sent by a user in an out-of-band mode according to a target protocol through the baseboard management controller;
and modifying the bus configuration information according to the modification request to configure the corresponding current target bus number for the target root port of the CPU.
4. The method of claim 3, wherein the modification request comprises a modification command or a modification file in a target format; the target format is a file storage format corresponding to the bus configuration information; the target protocol comprises an intelligent platform management interface protocol and a redfish protocol.
5. The method of claim 3, wherein the configuring bus resources for each root port according to the bus configuration information in the VGA shared memory comprises:
judging whether the bus configuration information contains the current target bus number or not;
and if the bus configuration information contains the current target bus number, performing bus resource configuration for the corresponding root port according to the current target bus number.
6. The method of claim 5, wherein after determining whether the current target bus number is included in the bus configuration information, the method further comprises:
and if the bus configuration information does not contain the current target bus number, performing bus resource configuration for the corresponding root port according to the default bus number.
7. The method according to any one of claims 1 to 6, wherein the performing, in a second phase after the first phase of the bios, bus resource configuration for each root port according to the bus configuration information in the VGA shared memory includes:
at a second stage after the first stage of the basic input and output system, reading the bus configuration information in the VGA shared memory in a memory mapping I/O mode;
and carrying out bus resource configuration for each root port according to the bus configuration information.
8. A bus resource reservation apparatus, comprising:
the bus configuration information adding module is used for adding bus configuration information to the VGA shared memory associated with the substrate management controller; the bus configuration information comprises the bus number corresponding to each root port of the CPU;
the initialization module is used for initializing VGA equipment where the VGA shared memory is located in the first stage of a basic input/output system;
and the bus resource configuration module is used for performing bus resource configuration on each root port according to the bus configuration information in the VGA shared memory at a second stage after the first stage of the basic input and output system.
9. An electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the bus resource reservation method of any of claims 1 to 7.
10. A computer-readable storage medium for storing a computer program; wherein the computer program when executed by the processor implements the bus resource reservation method as claimed in any of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210007514.4A CN114020344B (en) | 2022-01-06 | 2022-01-06 | Bus resource reservation method, device, equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210007514.4A CN114020344B (en) | 2022-01-06 | 2022-01-06 | Bus resource reservation method, device, equipment and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114020344A true CN114020344A (en) | 2022-02-08 |
| CN114020344B CN114020344B (en) | 2022-04-22 |
Family
ID=80069963
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210007514.4A Active CN114020344B (en) | 2022-01-06 | 2022-01-06 | Bus resource reservation method, device, equipment and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114020344B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115185874A (en) * | 2022-09-15 | 2022-10-14 | 珠海星云智联科技有限公司 | PCIE resource allocation method and related device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104615572A (en) * | 2015-02-27 | 2015-05-13 | 苏州科达科技股份有限公司 | Hot-plug processing system and method |
| CN108255527A (en) * | 2017-12-05 | 2018-07-06 | 华为技术有限公司 | The method and apparatus of activation system, computing device, readable storage medium storing program for executing |
| US20200301742A1 (en) * | 2019-03-22 | 2020-09-24 | Dell Products L.P. | Bus allocation system |
-
2022
- 2022-01-06 CN CN202210007514.4A patent/CN114020344B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104615572A (en) * | 2015-02-27 | 2015-05-13 | 苏州科达科技股份有限公司 | Hot-plug processing system and method |
| CN108255527A (en) * | 2017-12-05 | 2018-07-06 | 华为技术有限公司 | The method and apparatus of activation system, computing device, readable storage medium storing program for executing |
| US20200301742A1 (en) * | 2019-03-22 | 2020-09-24 | Dell Products L.P. | Bus allocation system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115185874A (en) * | 2022-09-15 | 2022-10-14 | 珠海星云智联科技有限公司 | PCIE resource allocation method and related device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114020344B (en) | 2022-04-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107690622B9 (en) | Method, equipment and system for realizing hardware acceleration processing | |
| WO2019084853A1 (en) | Method and system for discovering hardware attribute of bare metal server | |
| EP2363803B1 (en) | Virtual bus device using management engine | |
| US20100088448A1 (en) | Virtual computing accelerator and program downloading method for server-based virtual computing | |
| CN110908753B (en) | Intelligent fusion cloud desktop server, client and system | |
| US20100169629A1 (en) | Method for configuring computer by bios, server, computer, system startup method and computer system | |
| CN109033328A (en) | A kind of access request processing method, device, equipment and readable storage medium storing program for executing | |
| CN111124508A (en) | Method and device for adjusting PXE (PCI extensions for instrumentation) starting sequence of network card | |
| CN114020344B (en) | Bus resource reservation method, device, equipment and storage medium | |
| CN113282342A (en) | Deployment method, device, system, electronic equipment and readable storage medium | |
| CN116243996B (en) | Service operation switching method and device, storage medium and electronic device | |
| CN115562734A (en) | Data processor configuration method, device, equipment and medium | |
| JP2002288104A (en) | Computer system, and method and program for its resource assigning | |
| CN108108314B (en) | Exchanger system | |
| CN116848519A (en) | Method and device for generating hardware interface signal and electronic equipment | |
| CN113064655B (en) | BIOS network starting method and device and computer readable storage medium | |
| CN113704177B (en) | Storage method, system and related components of server firmware upgrade file | |
| CN114385537A (en) | Page slot number dynamic allocation method, device, equipment and medium | |
| CN115296994A (en) | Starting configuration method, device and medium for pooling heterogeneous computing resources | |
| CN115291951A (en) | UEFI (unified extensible firmware interface) starting method and device, electronic equipment and storage medium | |
| CN114115917A (en) | Operating system installation method and device | |
| CN110096366B (en) | Configuration method and device of heterogeneous memory system and server | |
| CN109656720B (en) | Address space allocation method and device | |
| CN103577382A (en) | Method and device for configuring node controller | |
| US20150212826A1 (en) | Information processing apparatus, information processing method, and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |