CN114020133A

CN114020133A - Storage system

Info

Publication number: CN114020133A
Application number: CN202111255463.9A
Authority: CN
Inventors: 王瑞杰; 华要宇
Original assignee: Inspur Beijing Electronic Information Industry Co Ltd
Current assignee: Inspur Beijing Electronic Information Industry Co Ltd
Priority date: 2021-10-27
Filing date: 2021-10-27
Publication date: 2022-02-08
Anticipated expiration: 2041-10-27
Also published as: CN114020133B

Abstract

The application discloses a storage system, includes: a PSU; a first load module connected with the PSU; the first protection circuit is connected with the input end of the PSU, is used for carrying out soft start when the PSU is powered on, and limits current to flow from the input end of the first protection circuit to the output end of the first protection circuit; the second load module is connected with the output end of the first protection circuit; the second load module comprises a minimum system for completing the data backup function of the storage system; BBU; and the second protection circuit is used for conducting when the PSU is powered down so that the BBU supplies power for the second load module, and limiting current to flow from the input end of the second protection circuit to the output end of the second protection circuit. By applying the scheme of the application, the capacity requirement on the BBU is reduced, and the storage system can finish the storage of data under the BBU with lower capacity.

Description

Storage system

Technical Field

The invention relates to the technical field of storage, in particular to a storage system.

Background

With the continuous development of the technology, the configuration of high-end storage is higher and higher, the number and power of CPUs are continuously increased, and the power of the whole computer is also higher and higher, which provides a great challenge for a Battery Backup Unit (BBU) supporting power supply during storage data Backup.

If powerful support is required, a large capacity of BBU is required, but this also makes the BBU very large in size, making it difficult to have enough space for the BBU to be placed in the present compact memory device.

In summary, how to effectively reduce the capacity requirement for BBUs so that a memory system can complete the storage of data under BBUs with lower capacity is a technical problem that needs to be solved urgently by those skilled in the art.

Disclosure of Invention

The invention aims to provide a memory system to effectively reduce the capacity requirement of BBU, so that the memory system can finish the storage of data under the condition of BBU with lower capacity.

In order to solve the technical problems, the invention provides the following technical scheme:

a storage system, comprising:

the PSU is used for converting the received alternating current into direct current;

the first load module is connected with the output end of the PSU;

the first protection circuit is used for carrying out soft start when the PSU is powered on, and limiting current to flow from the input end of the first protection circuit to the output end of the first protection circuit;

the second load module is connected with the output end of the first protection circuit; the second load module comprises a minimum system for completing the data backup function of the storage system;

BBU；

and the second protection circuit is used for conducting when the PSU is powered down so that the BBU supplies power for the second load module and limits current to flow from the input end of the second protection circuit to the output end of the second protection circuit.

Preferably, the first protection circuit includes:

the first end of the first MOS tube is connected with the output end of the PSU, and the second end of the first MOS tube is connected with the second end of the second MOS tube;

the first end of the second MOS tube is connected with the second load module, and the body diode of the first MOS tube and the second MOS tube body diode are in a reverse series connection structure;

the first controller is respectively connected with the output end of the PSU, the control end of the first MOS tube and the control end of the second MOS tube, and is used for charging the first capacitor after the PSU is powered on, and controlling the first MOS tube and the second MOS tube to be switched on from disconnection to complete connection from the beginning of charging the first capacitor until the first capacitor is charged.

Preferably, the method further comprises the following steps:

and the cathode is connected with the output end of the PSU, and the anode is grounded.

Preferably, the method further comprises the following steps:

the first resistor is connected with the cathode of the TVS diode at a first end, and connected with the first end of the second capacitor at a second end;

and the second end of the second capacitor is grounded.

Preferably, the method further comprises the following steps:

and the cathode of the Schottky diode is connected with the second load module, and the anode of the Schottky diode is grounded.

Preferably, the method further comprises the following steps:

the input end is connected with the output end of the PSU, the output end of the third protection circuit is connected with the first load module, soft start is carried out when the PSU is powered on, and the limiting current can only flow from the input end of the third protection circuit to the output end of the third protection circuit.

Preferably, the second protection circuit includes:

a third MOS tube having a first end connected to the second load module and a second end connected to the output end of the BBU;

the first controller is connected with the control end of the third MOS tube, and is used for controlling the third MOS tube to be in a turn-off state when the voltage of the first end of the third MOS tube is greater than or equal to the voltage of the second end of the third MOS tube, and controlling the third MOS tube to be in a turn-on state when the voltage of the first end of the third MOS tube is less than the voltage of the second end of the third MOS tube.

Preferably, the method further comprises the following steps:

the power monitoring circuit is used for monitoring the discharge power of the BBU;

and the third controller is used for controlling the second load module to be in a second state when the discharge power is higher than a preset power threshold value so as to reduce the power consumption of the second load module.

Preferably, the second load module comprises a CPU, a DIMM, a fan, a system disk and a memory;

the third controller is specifically configured to:

and when the discharge power is higher than a preset power threshold, controlling the CPU to reduce the frequency, and/or reducing the rotating speed of the fan, and/or controlling the memory to reduce the frequency.

Preferably, the third controller is a BMC or a CPLD

By applying the technical scheme provided by the embodiment of the invention, the PSU can convert the received alternating current into the direct current, the first load module is connected with the PSU, the second load module is connected with the PSU through the first protection circuit, and when the PSU is powered on, the first protection circuit limits the current to flow from the input end of the first protection circuit to the output end of the first protection circuit, so that when the PSU is normal, the first load module and the second load module can both obtain the power supply of the PSU. When the BBU is powered on, the connection relation shows that the BBU only supplies power to the second load module through the second protection circuit, and the second load module comprises a minimum system for completing the data backup function of the storage system, so that the storage system can complete the data storage when the BBU is powered on. And because the BBU does not need to supply power to the first load module, the scheme of the application reduces the capacity requirement for the BBU. In addition, when the PSU is powered on, the first protection circuit can realize soft start, and the safe power-on of the second load module can be effectively guaranteed. In addition, due to the anti-backflow function of the first protection circuit and the second protection circuit, the current of the PSU cannot flow into the BBU, and the current of the BBU cannot flow into the PSU, so that the safety of the memory system is further guaranteed.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a memory system according to the present invention;

FIG. 2 is a schematic diagram of a first protection circuit according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a second protection circuit according to an embodiment of the invention.

Detailed Description

The core of the invention is to provide a memory system, which reduces the capacity requirement for BBU, the memory system can also finish the data storage under the BBU with lower capacity, the safe power-on of the second load module can be ensured through soft start, the current of PSU can not flow into BBU and the current of BBU can not flow into PSU due to the anti-reflux function of the first protection circuit and the second protection circuit, and the safety of the memory system is further ensured.

In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a memory system according to the present invention, where the memory system may include:

a PSU10(Power Supply Unit) for converting received ac Power into dc Power;

a first load module 20 connected to an output of the PSU 10;

a first guard circuit 30 having an input connected to the output of the PSU10 for soft start when the PSU10 is powered on and limiting current flow only from the input of the first guard circuit 30 to the output of the first guard circuit 30;

a second load module 50 connected to an output terminal of the first protection circuit 30; the second load module 50 includes a minimum system that performs a data backup function of the storage system;

BBU60；

a second guard circuit 40 having an input connected to the output of BBU60 and an output connected to second load module 50, for turning on when PSU10 is powered down, such that BBU60 supplies second load module 50 and limits current to flow only from the input of second guard circuit 40 to the output of second guard circuit 40.

Specifically, the PSU10 is used as a power supply device of the storage system, and the specific circuit configuration can be set and adjusted according to actual needs. The PSU10 can convert the received ac power into dc power, and in practical applications, it usually converts the received 220V commercial power into 12V dc power, where P12V _ PSU in fig. 2 represents 12V dc power output from the PSU10 output terminal, and P12V _ BBU in fig. 3 represents 12V dc power output from the BBU60 output terminal.

The specific load type in the first load module 20 may be set and adjusted according to actual situations, but it should be noted that, when the PSU10 can normally output dc power, the first load module 20 connected to the output terminal of the PSU10 can be powered, and when the PSU10 cannot normally output power, the first load module 20 may not be powered by the BBU60, so that the components in the first load module 20 should be components that do not relate to the data backup function of the storage system, and direct power down is allowed when the PSU is powered down, for example, in actual applications, the first load module 20 may specifically include peripherals that do not relate to data backup, such as OCP cards and SSDs.

Through the first protection circuit 30, when the PSU10 is powered on, soft start can be performed, so that safe power-on of the second load module 50 can be effectively guaranteed, and hot plug is realized. Moreover, the first protection circuit 30 limits the current to flow only from the input terminal of the first protection circuit 30 to the output terminal of the first protection circuit 30, so that, when the BBU60 is supplying power, the power of the BBU60 cannot be supplied to the first load module 20, and cannot flow back to the PSU 10. The specific circuit configuration of the first protection circuit 30 may be set and adjusted according to actual needs, and the functions of the present application may be implemented.

For example, in an embodiment of the present invention, the first protection circuit 30 specifically includes:

a first MOS transistor Q1 with a body diode, a first end of the first MOS transistor Q1 is connected with the output end of the PSU10, and a second end of the first MOS transistor Q1 is connected with a second end of the second MOS transistor Q2;

a second MOS transistor Q2 having a body diode, a first end of the second MOS transistor Q2 is connected to the second load module 50, and the body diode of the first MOS transistor Q1 and the body diode of the second MOS transistor Q2 are in an inverse series structure;

the first controller is respectively connected with the output end of the PSU10, the control end of the first MOS transistor Q1 and the control end of the second MOS transistor Q2, and is used for charging the first capacitor C1 after the PSU10 is powered on, and controlling the first MOS transistor Q1 and the second MOS transistor Q2 to be switched from off to full on from the beginning of charging the first capacitor C1 to the end of charging the first capacitor C1.

Referring to fig. 2, in the embodiment of fig. 2, the first controller is specifically selected to be a TPS24741 chip, and in other embodiments, the chip type of the first controller may be selected as needed.

The soft start is realized by utilizing the conducting property of the MOS tube, namely, certain time consumption exists when the MOS tube is switched from the off state to the on state, the current in the circuit can be gradually increased by controlling the time consumption, and the damage of surge current to a rear-stage circuit is avoided. This time is the time consumed for charging the first capacitor C1. That is, when the PSU10 supplies power, the first controller charges the first capacitor C1 connected to the first controller, and the first capacitor C1 controls the first MOS transistor Q1 and the second MOS transistor Q2 to be turned on from off to full from the beginning of charging to the end of charging, thereby implementing the soft start process. It will be appreciated that the adjustment to the soft start duration may be achieved by configuring and adjusting the capacitance value of the first capacitor C1.

The body diode of the first MOS transistor Q1 and the body diode of the second MOS transistor Q2 are in an anti-series structure, which means that the cathodes of the body diodes of the first MOS transistor Q1 and the second MOS transistor Q2 are connected with each other, or the anodes of the body diodes of the first MOS transistor Q1 and the second MOS transistor Q2 are connected with each other, so that when the PSU10 is powered off and powered by the BBU60, the output power of the BBU60 cannot flow back to the PSU10 through the first MOS transistor Q1 and the second MOS transistor Q2.

In the embodiment of fig. 2, the first controller of the present application is implemented by a TPS24741 chip, the TPS24741 chip receives power output by the PSU10 through a VDD pin, and when an ENOR pin and an ENHS pin of the TPS24741 chip are pulled high by an output of the PSU10, the TPS24741 chip charges the first capacitor C1, and during the charging process, the first MOS transistor Q1 and the second MOS transistor Q2 are controlled to be gradually turned on until the first capacitor C1 is completely charged, and the first MOS transistor Q1 and the second MOS transistor Q2 are completely turned on. In the embodiment of fig. 2, a current limiting resistor R11 is further arranged in series between the control terminal of the first MOS transistor Q1 and the TPS24741 chip, and a current limiting resistor R22 is further arranged in series between the control terminal of the second MOS transistor Q2 and the TPS24741 chip. In addition, a current limiting resistor R33 connected in series with the first MOS transistor Q1 is provided in a branch of the PSU10 for supplying power to the second load module 50.

Further, in an embodiment of the present invention, the method may further include:

and a TVS diode D1 with a cathode connected to the output of the PSU10 and an anode connected to ground.

The TVS diode is a transient suppression diode, has good surge absorption capacity, has extremely fast response time, and effectively protects the following circuit. In fig. 2 of the present application, a TVS diode D1 is provided to further protect against voltage surge caused by hot plugging.

Further, referring to fig. 2, the method may further include:

a first resistor R1 having a first terminal connected to the cathode of the TVS diode D1 and a second terminal connected to the first terminal of the second capacitor C2;

and a second terminal of the second capacitor C2 is grounded.

In the implementation mode, the RC circuit is arranged to be connected with the TVS diode D1 in parallel, so that the buffering effect can be further achieved, and voltage impact caused by hot plugging is avoided.

Further, referring to fig. 2, the method may further include:

a schottky diode D2 with its cathode connected to the second load module 50 and its anode connected to ground.

In order to avoid damage to the TPS24741 chip in fig. 2 in order to avoid the transient negative voltage from damaging the first controller when the PSU10 is suddenly powered down, a schottky diode D2 is disposed at the output end of the first protection circuit 30, i.e., the input end of the second load module 50, so as to effectively avoid damage to the chip caused by the negative voltage when the PSU10 is powered down. In addition, the output terminal of the first protection circuit 30 in fig. 2 is denoted as P12V _ AUX, and a third capacitor C3 connected in parallel with the schottky diode D2 is further provided in fig. 2 to achieve the voltage stabilizing effect.

The BBU60, as a backup battery, can supply power to the second load module 50 when the PSU10 cannot supply power, so that the storage system can complete data backup, and data loss caused by power failure is avoided. Therefore, the second load module 50 needs to include a minimum system for performing the data backup function of the storage system, that is, components related to the data backup function of the storage system, which are listed in the second load module 50. For example, in practical applications, the second load module 50 may specifically include components such as a CPU, a fan, a system disk, a memory, a DIMM, and the like.

The BBU60 supplies power to the second load module 50 through the second guard circuit 40, and since the second guard circuit 40 is turned on when the PSU10 is powered down, the BBU60 supplies power to the second load module 50, and the second guard circuit 40 can limit the current to flow only from the input terminal of the second guard circuit 40 to the output terminal of the second guard circuit 40, so that the current can be prevented from flowing into the BBU60 when the PSU10 supplies power.

The specific circuit configuration of the second protection circuit 40 can also be set and adjusted as required, for example, in the embodiment of fig. 3, the second protection circuit 40 is implemented by a switch tube and a corresponding controller, that is, the second protection circuit 40 may include:

a third MOS transistor Q3 having a first end connected to the second load module 50 and a second end connected to the output terminal of the BBU 60;

the second controller is connected to the first end of the third MOS transistor Q3, the second end of the third MOS transistor Q3, and the control end of the third MOS transistor Q3, and is configured to control the third MOS transistor Q3 to be in an off state when the voltage at the first end of the third MOS transistor Q3 is greater than or equal to the voltage at the second end of the third MOS transistor Q3, and control the third MOS transistor Q3 to be in an on state when the voltage at the first end of the third MOS transistor Q3 is less than the voltage at the second end of the third MOS transistor Q3.

In fig. 3, the second controller is specifically an LM5050 chip, when the PSU10 supplies power normally, the voltage at the first end of the third MOS transistor Q3 is greater than or equal to the output voltage of the voltage at the second end of the third MOS transistor Q3, so the second controller controls the third MOS transistor Q3 to be in an off state, otherwise, when the voltage at the first end of the third MOS transistor Q3 is less than the voltage at the second end of the third MOS transistor Q3, the second controller controls the third MOS transistor Q3 to be in an on state.

In an embodiment of the present invention, the method may further include:

the power monitoring circuit is used for monitoring the discharge power of the BBU 60;

and a third controller, configured to control the second load module 50 to be in the second state when the discharging power is higher than the preset power threshold, so as to reduce power consumption of the second load module 50.

In the foregoing embodiment, the capacity requirement for BBU60 is effectively reduced by making a distinction between first load module 20 and second load module 50, which in this embodiment can further reduce the capacity requirement for BBU 60.

Specifically, in this embodiment, the discharge power of the BBU60 may be monitored by the power monitoring circuit, and if the discharge power is higher than the preset power threshold, it indicates that the current load power consumption is large, and data backup may not be effectively completed, so that the third controller may control the second load module 50 to be in the second state to reduce the power consumption of the second load module 50, which effectively prolongs the power supply time of the BBU60, and further effectively reduces the capacity requirement on the BBU 60.

The specific value of the preset power threshold may be set and adjusted according to actual needs, for example, in a specific situation, 180 seconds are required to implement data backup of the memory system, that is, to satisfy data storage, 180 seconds are required to flush data, for example, the capacity of the BBU60 is 20WH, when the BBU60 supplies power, the average maximum power is 20WH/180s is 400W, considering reliability, the preset power threshold may be lower than 400W, for example, may be set to 280W, that is, when the monitored discharge power of the BBU60 exceeds 280W, in this embodiment, the second load module 50 is controlled to be in the second state, so as to reduce the power consumption of the second load module 50, and further satisfy the requirement of the power supply process. In this embodiment, the data reliability requirements of the memory system are met by controlling power consumption during power backup with limited BBU60 capacity.

There may be various specific means for reducing the power consumption of the second load module 50, for example, in one embodiment of the present invention, the second load module 50 includes a CPU, a DIMM, a fan, a system disk, and a memory;

a third controller, specifically configured to:

In this embodiment, the CPU is controlled to reduce the frequency, the rotation speed of the fan is reduced, and the memory is controlled to reduce the frequency, so that the power consumption of the second load module 50 can be effectively reduced, and the influence on the data refreshing is small, that is, the data backup process of the storage system is not greatly influenced. Of course, in other embodiments, other operations may be provided to reduce the power consumption of second load module 50 when BBU60 is powered, depending on the circumstances.

Since the power consumption of the second load module 50 needs to be reduced, the third controller may be generally selected as a BMC or a CPLD, which may effectively meet the functional requirements of the third controller of the present application.

The specific circuit configuration of the power monitoring circuit can be set and adjusted as required, for example, in the embodiment of fig. 3, the third resistor R3 is connected in series as a precision resistor at the output end of the BBU60, and the discharge voltage, the discharge current and the discharge power of the BBU60 can be monitored by the INA219 chip.

In an embodiment of the present invention, the method may further include:

the third protection circuit, the input end of which is connected with the output end of the PSU10, and the output end of which is connected with the first load module 20, performs soft start when the PSU10 is powered on, and limits current to flow from the input end of the third protection circuit to the output end of the third protection circuit only.

In this embodiment, the third protection circuit avoids the impact on the first load module 20 when the PSU10 is powered on, and effectively ensures that the storage system realizes hot plug. The specific circuit configuration of the third protection circuit may be set according to actual needs, for example, referring to the foregoing embodiment, the capacitor is charged, and the corresponding MOS transistor is controlled to be gradually turned on to implement soft start.

By applying the technical solution provided by the embodiment of the present invention, the PSU10 can convert the received ac power into dc power, the first load module 20 is connected to the PSU10, the second load module 50 is connected to the PSU10 through the first protection circuit 30, and when the PSU10 is powered on, the first protection circuit 30 limits the current to only flow from the input terminal of the first protection circuit 30 to the output terminal of the first protection circuit 30, so that when the PSU10 is normal, both the first load module 20 and the second load module 50 can be powered by the PSU 10. When the BBU60 supplies power, it can be known from the connection relationship that the BBU60 only supplies power to the second load module 50 through the second protection circuit 40, and since the second load module 50 includes a minimum system that performs a data backup function of the memory system, the memory system can complete data storage when the BBU60 supplies power. And because BBU60 does not need to power first load module 20, the solution of the present application reduces the capacity requirements for BBU 60. In addition, when the PSU10 is powered on, the first protection circuit 30 can realize soft start, which can effectively ensure that the second load module 50 is powered on safely. In addition, due to the backflow prevention function of the first protection circuit 30 and the second protection circuit 40, the current of the PSU10 cannot flow into the BBU60, and the current of the BBU60 cannot flow into the PSU10, so that the safety of the memory system is further guaranteed.

It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The principle and the implementation of the present invention are explained in the present application by using specific examples, and the above description of the embodiments is only used to help understanding the technical solution and the core idea of the present invention. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.

Claims

1. A storage system, comprising:

the first load module is connected with the output end of the PSU;

BBU；

2. The memory system of claim 1, wherein the first guard circuit comprises:

3. The storage system of claim 2, further comprising:

4. The storage system of claim 3, further comprising:

and the second end of the second capacitor is grounded.

5. The storage system of claim 2, further comprising:

6. The storage system of claim 1, further comprising:

7. The memory system of claim 1, wherein the second guard circuit comprises:

8. The storage system according to any one of claims 1 to 7, further comprising:

9. The storage system of claim 8, wherein the second load module comprises a CPU, DIMM, fan, system disk, memory;

the third controller is specifically configured to:

10. The storage system of claim 8, wherein the third controller is a BMC or a CPLD.