CN114020132A - PG signal circuit - Google Patents
PG signal circuit Download PDFInfo
- Publication number
- CN114020132A CN114020132A CN202111206869.8A CN202111206869A CN114020132A CN 114020132 A CN114020132 A CN 114020132A CN 202111206869 A CN202111206869 A CN 202111206869A CN 114020132 A CN114020132 A CN 114020132A
- Authority
- CN
- China
- Prior art keywords
- voltage
- resistor
- output
- dividing resistor
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001105 regulatory effect Effects 0.000 claims description 4
- 238000000034 method Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Direct Current Feeding And Distribution (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The application discloses PG signal output circuit includes: the negative electrode input end of a voltage comparator U1 is connected with the voltage output end of an E-Fuse chip U3, the positive electrode input end of a voltage comparator U1 is respectively connected with one end of a reference resistor R1 and one end of a positive feedback resistor R3, the output end of a voltage comparator U1 and the other end of a positive feedback resistor R3 are connected with the control end of a controllable switch U2, and the positive power supply end of the voltage comparator U1 is connected with an external stabilized voltage power supply; the output end of the controllable switch U2 is grounded, and the input end of the controllable switch U2 is connected with one end of the first divider resistor R7, one end of the second divider resistor R8 and the enabling end of the time sequence control chip; the other end of the second voltage-dividing resistor R8 is grounded, and the other end of the first voltage-dividing resistor R7 is connected with the voltage output end of the E-Fuse chip U3; the other end of the reference resistor R1 is connected to a reference voltage. Under the condition that the voltage output by the E-Fuse chip U3 fluctuates, the P12V _ PG signal cannot be suddenly increased, and the continuous stability of the P12V _ PG signal is ensured.
Description
Technical Field
The invention relates to the field of power electronics, in particular to a PG signal circuit.
Background
With the rapid development of server performance, the security and stability of the server during long-term high-load operation are receiving general market attention.
From the security point of view: the PSU is a direct power supply for supplying power to most servers, but for safety reasons and the fact that part of the boards support hot plug functions, the voltage of P12V used on a general board is not directly supplied by the PSU, and generally, the voltage after E-Fuse is used as the P12V of the board after the voltage of the PSU on the board is output through an E-Fuse chip, so that the hot plug function is supported, and the function of protecting the board can be achieved.
From the stability point of view: the timing control of the mainboard can effectively prevent downtime and chip burning. For more complicated timing control, a timing control chip is used to control the timing, such as: after the P12V voltage is established, a corresponding P12V PG signal (generally high level) is provided to the timing control chip, and then the timing control chip enables the power chip of the next stage 3.3V (generally high level), so as to realize the timing requirement that the P12V voltage is established first and then the chip of the next stage starts to work.
When the power is off, the level of the P12V PG is correspondingly converted (from high level to low level), the signal is sent to the time sequence management chip, and then the time sequence management chip pulls down the enable of the next stage, so that the time sequence requirement that the power of the P12V voltage is firstly off and the power of the next stage chip is started to be off is realized.
For a simpler timing control, the PG signal of the previous stage is generally directly used as the enable signal of the next stage, for example, the PG signal of P12V is used as the enable signal of the next stage of 3.3V, so that the PG signal pulled up to enable 3.3V after the P12V voltage is established can also be realized.
However, in practical applications, part of the E-Fuse chip has a pin for PG signal, and can be directly used by external pull-up, and part of the E-Fuse chip does not have a pin for PG. Therefore, a PG signal must be designed according to the output condition of P12V to achieve the purpose of timing control.
The existing partial design scheme is schematically shown in fig. 1: when the power is on, the P12V _ PSU _ Vin is input, the voltage of the P12V _ Vout is gradually increased, and V1 is obtained through the voltage division of R5 and R6. When the voltage of the U1 reaches the turn-on voltage of the U1MOS transistor, the U1 is turned on, the V2 is low voltage, the U2 MOS transistor is turned off, and the P12V _ PG is divided by the P12V _ Vout to obtain a high level, so that the U4 is enabled.
When power is lost, when the voltage V1 is lower than the turn-on voltage of U1, U1 is turned off, the voltage V2 is P12_ PSU _ Vin, at this time, V2 is still higher than the turn-on voltage of U2, U2 is turned on, P12V _ PG is at a low level, when the voltage V2 drops to a point below the turn-on voltage of U2, U2 is turned off, at this time, the voltage P12V _ Vout is already at a low level after being divided, and the logic of P12V _ PG is also kept at a low level.
With reference to fig. 1, the power-up process is relatively fast and there is no problem, but the PSU power supply has a very large internal capacitance, and the power-down speed of P12V _ Vout is very slow due to the capacitance in the PSU during AC power-down.
At the threshold of the turn-on voltage of U1, there is a possibility that the turn-on, and turn-off processes of U1 occur frequently and rapidly in a short time, which causes the turn-on, turn-off, and turn-on of U2, and the P12V _ PG changes from low, high, and low.
The enable of U4 also varies low, high, and low, which causes the voltage output of the subsequent stage to be not monotonous and even causes timing disorder. As shown in fig. 2, for this design, the waveform of the output voltage of U4 during the power-off test is obviously not monotonous.
Therefore, a PG circuit capable of ensuring the stability of the PG enable signal during the slow power-down of the power supply is needed.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a PG signal circuit, which can ensure that a PG enable signal is stable and does not cause timing disorder during a slow power-down process of a power supply. The specific scheme is as follows:
a PG signal output circuit comprising: the voltage comparator U1, the positive feedback resistor R3, the controllable switch U2, the reference resistor R1, the first voltage-dividing resistor R7 and the second voltage-dividing resistor R8;
the negative electrode input end of the voltage comparator U1 is connected with the voltage output end of an E-Fuse chip U3, the positive electrode input end of the voltage comparator U1 is respectively connected with one end of a reference resistor R1 and one end of a positive feedback resistor R3, the output end of the voltage comparator U1, the other end of the positive feedback resistor R3 and the control end of the controllable switch U2 are connected, and the positive power supply end of the voltage comparator U1 is connected with an external stabilized voltage power supply;
the output end of the controllable switch U2 is grounded, and the input end of the controllable switch U2 is connected with one end of the first divider resistor R7, one end of the second divider resistor R8 and the enabling end of a time sequence control chip;
the other end of the second voltage-dividing resistor R8 is grounded, and the other end of the first voltage-dividing resistor R7 is connected with the voltage output end of the E-Fuse chip U3;
the other end of the reference resistor R1 is connected to a reference voltage.
Optionally, the negative input terminal of the voltage comparator U1 is connected to the voltage output terminal of the E-Fuse chip U3 through a first resistor R1.
Optionally, the voltage output terminal of the E-Fuse chip U3 includes: a third voltage dividing resistor R5 and a fourth voltage dividing resistor R6;
one end of the third voltage dividing resistor R5 is connected to the output end of the E-Fuse chip U3, the other end of the third voltage dividing resistor R5 is connected to one end of the fourth voltage dividing resistor R6 as the voltage output end of the E-Fuse chip U3, and the other end of the fourth voltage dividing resistor R6 is grounded.
Optionally, the controllable switch U2 is an N-MOS transistor.
Optionally, the reference resistor R1 and the positive feedback resistor R3 are set so that a low-order comparison voltage of the voltage comparator U1 is smaller than a high-order comparison voltage of the voltage comparator U1, and after a voltage output by the voltage output terminal of the E-Fuse chip U3 is lower than the low-order comparison voltage, a ripple voltage output by the voltage output terminal of the E-Fuse chip U3 is not higher than the high-order comparison voltage;
wherein, the low-order comparison voltage expression is as follows: (Vref-Vol) × R3/(R2+ R3);
the high-order comparison voltage expression is as follows: (Voh-Vref) R2/(R2+ R3);
in the formula, Vref represents the reference voltage, Vol represents the low-order output voltage of the voltage comparator U1, R2 represents the resistance value of the reference resistor R1, R3 represents the resistance value of the positive feedback resistor R3, and Voh represents the high-order output voltage of the voltage comparator U1, which is equal to the voltage output by the external regulated power supply.
Optionally, the resistances of the reference resistor R1, the positive feedback resistor R3, the first resistor R1, the fourth divider resistor R6, and the second divider resistor R8 are all 1K Ω, the resistance of the third divider resistor R5 is 5K Ω, and the resistance of the first divider resistor R7 is 3K Ω.
In the present invention, a PG signal output circuit includes: the voltage comparator U1, the positive feedback resistor R3, the controllable switch U2, the reference resistor R1, the first voltage-dividing resistor R7 and the second voltage-dividing resistor R8; the negative electrode input end of the voltage comparator U1 is connected with the voltage output end of an E-Fuse chip U3, the positive electrode input end of the voltage comparator U1 is respectively connected with one end of a reference resistor R1 and one end of a positive feedback resistor R3, the output end of the voltage comparator U1, the other end of the positive feedback resistor R3 and the control end of the controllable switch U2 are connected, and the positive power supply end of the voltage comparator U1 is connected with an external stabilized voltage power supply; the output end of the controllable switch U2 is grounded, and the input end of the controllable switch U2 is connected with one end of the first divider resistor R7, one end of the second divider resistor R8 and the enabling end of a time sequence control chip; the other end of the second voltage-dividing resistor R8 is grounded, and the other end of the first voltage-dividing resistor R7 is connected with the voltage output end of the E-Fuse chip U3; the other end of the reference resistor R1 is connected to a reference voltage.
The invention is provided with the positive feedback comparator, so that the low-order comparison voltage of the voltage comparator U1 is lower than the high-order comparison voltage, and under the condition that the voltage output by the E-Fuse chip U3 fluctuates, even if the low-order comparison voltage is exceeded, the controllable switch U2 can be ensured to be turned off as long as the low-order comparison voltage is continuously lower than the high-order comparison voltage, the P12V _ PG signal cannot be suddenly increased, and the continuous stability of the P12V _ PG signal is ensured.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic diagram of a PG signal circuit in the prior art.
FIG. 2 is a diagram of a PG signal in the prior art.
Fig. 3 is a schematic diagram of a PG signal circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention discloses a PG signal circuit, which is shown in figure 3 and comprises the following components: the voltage comparator U1, the positive feedback resistor R3, the controllable switch U2, the reference resistor R1, the first voltage-dividing resistor R7 and the second voltage-dividing resistor R8;
the negative electrode input end of a voltage comparator U1 is connected with the voltage output end of an E-Fuse chip U3, the positive electrode input end of a voltage comparator U1 is respectively connected with one end of a reference resistor R1 and one end of a positive feedback resistor R3, the output end of a voltage comparator U1 and the other end of a positive feedback resistor R3 are connected with the control end of a controllable switch U2, and the positive power supply end of the voltage comparator U1 is connected with an external stabilized voltage power supply;
the output end of the controllable switch U2 is grounded, and the input end of the controllable switch U2 is connected with one end of the first divider resistor R7, one end of the second divider resistor R8 and the enabling end of the time sequence control chip;
the other end of the second voltage-dividing resistor R8 is grounded, and the other end of the first voltage-dividing resistor R7 is connected with the voltage output end of the E-Fuse chip U3;
the other end of the reference resistor R1 is connected to a reference voltage.
Specifically, the voltage at the output terminal V2 of the voltage comparator U1 has only two states, i.e., a high-level high-order output voltage Voh and a low-level low-order output voltage Vol, Voh is equal to the positive power supply voltage Vcc at the positive power terminal, i.e., the voltage output by the external regulated power supply, the low-order output voltage Vol is approximately 0, when the output voltage V2 is the low-order output voltage Vol, the voltage at the positive electrode of the voltage comparator U1 is (Vref-Vol) × R3/(R2+ R3), the voltage is used as the low-order comparison voltage Vtl of the comparator, when the output voltage V2 is the high-order output voltage Voh, the voltage at the positive electrode of the voltage comparator U1 is (Voh-Vref) × R2/(R2+ R3), and the voltage is used as the high-order comparison voltage Vth of the comparator. Where Vref is the reference voltage, R3 represents the resistance of the positive feedback resistor R3, and R2 represents the resistance of the reference resistor R1. The reference resistor R1 and the positive feedback resistor R3 are set so that the low-order comparison voltage of the voltage comparator U1 is smaller than the high-order comparison voltage of the voltage comparator U1, and the fluctuation voltage output by the voltage output end of the E-Fuse chip U3 is not higher than the high-order comparison voltage after the voltage output by the voltage output end of the E-Fuse chip U3 is lower than the low-order comparison voltage.
Specifically, referring to fig. 1, when power is turned on, P12V _ Vout is gradually established, and before V2 reaches 12V, V is high, the controllable switch U2 is turned on, and the circuit is grounded, so that P12V _ PG cannot receive the voltage transmitted by P12V _ Vout at the first voltage dividing resistor R7, and therefore P12V _ PG is low, and the next stage of circuit cannot be enabled. When the voltage output end V1 of the E-Fuse chip U3 reaches the high comparison voltage VTh threshold when the P12V _ Vout reaches 12V, and the V2 becomes low level, the controllable switch U2 is turned off, the P12V _ PG becomes high level, and the EN end of the next-stage circuit U4 obtains an enable signal.
Specifically, when the power is turned off, when the voltage P12V _ Vout is slowly decreased to about 3V, V1 reaches Vtl threshold 0.5V, V2 becomes high, P12V _ PG becomes low, and the next stage circuit U4 is enabled to pull low.
After P12V _ Vout is slowly powered down to V1 to Vtl, even though V1 may be higher than Vtl due to fluctuation of the voltage output by E-Fuse chip U3, since the threshold of the primary Vth is not met, V2 will not change, and controllable switch U2 will not be turned on, so the state of P12V _ PG will not change.
Therefore, the embodiment of the invention is provided with the positive feedback comparator, so that the low-order comparison voltage of the voltage comparator U1 is lower than the high-order comparison voltage, and even if the low-order comparison voltage is exceeded under the condition that the voltage output by the E-Fuse chip U3 fluctuates, the controllable switch U2 can be ensured to be turned off as long as the low-order comparison voltage is continuously lower than the high-order comparison voltage, the P12V _ PG signal cannot be suddenly increased, and the P12V _ PG signal is ensured to be continuously stable.
Furthermore, the negative electrode input end of the voltage comparator U1 is connected with the voltage output end of the E-Fuse chip U3 through a first resistor R1.
Specifically, the voltage output terminal of the E-Fuse chip U3 includes: a third voltage dividing resistor R5 and a fourth voltage dividing resistor R6;
one end of the third voltage dividing resistor R5 is connected with the output end of the E-Fuse chip U3, the other end of the third voltage dividing resistor R5 is connected with one end of the fourth voltage dividing resistor R6 to be used as the voltage output end of the E-Fuse chip U3, and the other end of the fourth voltage dividing resistor R6 is grounded.
Specifically, the controllable switch U2 is an N-MOS transistor.
Specifically, the present invention also discloses a specific embodiment of the PG signal circuit, in which the resistances of the reference resistor R1, the positive feedback resistor R3, the first resistor R1, the fourth voltage-dividing resistor R6, and the second voltage-dividing resistor R8 are all 1K Ω, the resistance of the third voltage-dividing resistor R5 is 5K Ω, the resistance of the first voltage-dividing resistor R7 is 3K Ω, the external regulated power supply VCC is 3V — Voh, Vth — 2V, Vtl is 0.5V, and Vref is 1V.
It can be understood that the resistance values of R2, R3, R5, R6, etc. can be adjusted appropriately to match the design requirements according to the type selection and the chip parameters.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The technical content provided by the present invention is described in detail above, and the principle and the implementation of the present invention are explained in this document by applying specific examples, and the above description of the examples is only used to help understanding the method of the present invention and the core idea thereof; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (6)
1. A PG signal output circuit, comprising: the voltage comparator U1, the positive feedback resistor R3, the controllable switch U2, the reference resistor R1, the first voltage-dividing resistor R7 and the second voltage-dividing resistor R8;
the negative electrode input end of the voltage comparator U1 is connected with the voltage output end of an E-Fuse chip U3, the positive electrode input end of the voltage comparator U1 is respectively connected with one end of a reference resistor R1 and one end of a positive feedback resistor R3, the output end of the voltage comparator U1, the other end of the positive feedback resistor R3 and the control end of the controllable switch U2 are connected, and the positive power supply end of the voltage comparator U1 is connected with an external stabilized voltage power supply;
the output end of the controllable switch U2 is grounded, and the input end of the controllable switch U2 is connected with one end of the first divider resistor R7, one end of the second divider resistor R8 and the enabling end of a time sequence control chip;
the other end of the second voltage-dividing resistor R8 is grounded, and the other end of the first voltage-dividing resistor R7 is connected with the voltage output end of the E-Fuse chip U3;
the other end of the reference resistor R1 is connected to a reference voltage.
2. The PG signal circuit of claim 1, characterized in that the negative input terminal of the voltage comparator U1 is connected with the voltage output terminal of the E-Fuse chip U3 through a first resistor R1.
3. The PG signal circuit of claim 2, wherein the voltage output terminal of the E-Fuse chip U3 comprises: a third voltage dividing resistor R5 and a fourth voltage dividing resistor R6;
one end of the third voltage dividing resistor R5 is connected to the output end of the E-Fuse chip U3, the other end of the third voltage dividing resistor R5 is connected to one end of the fourth voltage dividing resistor R6 as the voltage output end of the E-Fuse chip U3, and the other end of the fourth voltage dividing resistor R6 is grounded.
4. A PG signal circuit as claimed in claim 3, characterized in that said controllable switch U2 is an N-MOS transistor.
5. The PG signal circuit as claimed in any one of claims 1 to 4, wherein said reference resistor R1 and said positive feedback resistor R3 are set such that a low comparison voltage of said voltage comparator U1 is lower than a high comparison voltage of said voltage comparator U1, and a ripple voltage outputted from a voltage output terminal of said E-Fuse chip U3 is not higher than said high comparison voltage after a voltage outputted from a voltage output terminal of said E-Fuse chip U3 is lower than said low comparison voltage;
wherein, the low-order comparison voltage expression is as follows: (Vref-Vol) × R3/(R2+ R3);
the high-order comparison voltage expression is as follows: (Voh-Vref) R2/(R2+ R3);
in the formula, Vref represents the reference voltage, Vol represents the low-order output voltage of the voltage comparator U1, R2 represents the resistance value of the reference resistor R1, R3 represents the resistance value of the positive feedback resistor R3, and Voh represents the high-order output voltage of the voltage comparator U1, which is equal to the voltage output by the external regulated power supply.
6. The PG signal circuit as claimed in claim 5, wherein the reference resistor R1, the positive feedback resistor R3, the first resistor R1, the fourth voltage-dividing resistor R6 and the second voltage-dividing resistor R8 all have a resistance of 1K Ω, the third voltage-dividing resistor R5 has a resistance of 5K Ω, and the first voltage-dividing resistor R7 has a resistance of 3K Ω.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111206869.8A CN114020132B (en) | 2021-10-15 | 2021-10-15 | PG signal circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111206869.8A CN114020132B (en) | 2021-10-15 | 2021-10-15 | PG signal circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114020132A true CN114020132A (en) | 2022-02-08 |
| CN114020132B CN114020132B (en) | 2023-07-14 |
Family
ID=80056367
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111206869.8A Active CN114020132B (en) | 2021-10-15 | 2021-10-15 | PG signal circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114020132B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120126907A1 (en) * | 2010-11-24 | 2012-05-24 | Fujitsu Semiconductor Limited | Oscillation circuit |
| CN206074715U (en) * | 2016-01-09 | 2017-04-05 | 惠州市物联微电子有限公司 | A kind of direct current power-fail detection circuit |
| CN112953311A (en) * | 2021-03-03 | 2021-06-11 | 珞石（北京）科技有限公司 | Hysteresis comparison voltage bleeder circuit |
| CN113225875A (en) * | 2021-04-20 | 2021-08-06 | 深圳市崧盛电子股份有限公司 | Drive power supply and output short-circuit protection circuit thereof |
-
2021
- 2021-10-15 CN CN202111206869.8A patent/CN114020132B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120126907A1 (en) * | 2010-11-24 | 2012-05-24 | Fujitsu Semiconductor Limited | Oscillation circuit |
| CN206074715U (en) * | 2016-01-09 | 2017-04-05 | 惠州市物联微电子有限公司 | A kind of direct current power-fail detection circuit |
| CN112953311A (en) * | 2021-03-03 | 2021-06-11 | 珞石（北京）科技有限公司 | Hysteresis comparison voltage bleeder circuit |
| CN113225875A (en) * | 2021-04-20 | 2021-08-06 | 深圳市崧盛电子股份有限公司 | Drive power supply and output short-circuit protection circuit thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114020132B (en) | 2023-07-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109213247B (en) | Circuit and method for supplying regulated voltage to target circuit | |
| CN113110694B (en) | Low dropout regulator circuit with current surge suppression | |
| US7109690B2 (en) | Fast-disabled voltage regulator circuit with low-noise feedback loop and operating method thereof | |
| WO2009044326A1 (en) | Capless low drop-out voltage regulator with fast overvoltage response | |
| US6188210B1 (en) | Methods and apparatus for soft start and soft turnoff of linear voltage regulators | |
| US5898844A (en) | Data processing system including a hot-plug circuit for receiving high-power adaptor cards | |
| KR101831462B1 (en) | Apparatus and method for host power-on reset control | |
| WO2015069388A1 (en) | Limiting current in a low dropout linear voltage regulator | |
| CN105988495A (en) | LDO (Low Drop-out voltage regulator) overshooting protection circuit | |
| CN217469914U (en) | Power-on reset circuit | |
| US20060267673A1 (en) | [modulator] | |
| CN114020132B (en) | PG signal circuit | |
| CN113484589B (en) | Power failure detection circuit with hysteresis function and control system | |
| CN203708211U (en) | Power-on delay circuit of low dropout linear regulator | |
| CN111400985A (en) | Time sequence control circuit applied to integrated circuit and server board card | |
| US10965137B2 (en) | Charging device and charging method thereof | |
| US7388356B2 (en) | System and method for providing voltage regulation in a multi-voltage power system | |
| KR20010012426A (en) | Voltage regulating circuit for eliminating latch-up | |
| US7594130B1 (en) | Circuit for regulating timing sequence | |
| US20200321866A1 (en) | Buck Converter With Variable Sized Switches | |
| WO2024135656A1 (en) | Power supply device and power system | |
| CN221804231U (en) | MAX 706-based power supply power failure detection circuit | |
| CN113612209B (en) | Current limiting circuit | |
| CN112787486B (en) | Power ready signal generating device and operation method thereof | |
| CN216697201U (en) | Mainboard self-adaptation mains voltage's structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |