CN114019295A - Method and device for analyzing three-phase disconnection fault of two lines of four-line circuit on same pole - Google Patents

Method and device for analyzing three-phase disconnection fault of two lines of four-line circuit on same pole Download PDF

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CN114019295A
CN114019295A CN202111069613.7A CN202111069613A CN114019295A CN 114019295 A CN114019295 A CN 114019295A CN 202111069613 A CN202111069613 A CN 202111069613A CN 114019295 A CN114019295 A CN 114019295A
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sequence
voltage
current
phase
constraint
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陆政君
杨嘉靖
石桂学
石怀强
汪凤月
李泳龙
童理
韦昌伟
庞泽
赵铎
覃正红
唐纬
黄宗启
覃雪梅
甘琦
唐广
杨超群
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Datang Hydropower Science and Technology Research Institute Co Ltd
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Datang Hydropower Science and Technology Research Institute Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/08—Locating faults in cables, transmission lines, or networks
    • G01R31/081—Locating faults in cables, transmission lines, or networks according to type of conductors
    • G01R31/085—Locating faults in cables, transmission lines, or networks according to type of conductors in power transmission or distribution lines, e.g. overhead
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/54—Testing for continuity
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/58—Testing of lines, cables or conductors

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Abstract

The invention discloses a method, a device, equipment and a computer readable storage medium for analyzing three-phase disconnection faults of two circuits of a same-pole four-circuit line, wherein the method comprises the following steps: determining voltage constraint and current constraint according to boundary conditions of two-loop three-phase disconnection faults in four loops; drawing a composite sequence network diagram when the two loops of three-phase disconnection fails according to the relation between the voltage constraint and the current constraint middle-sequence component; determining each sequence voltage and each sequence current according to a composite sequence network diagram, voltage constraint and current constraint when the two-loop three-phase disconnection fails; calculating the line break voltage and the normal phase current at the line break position according to the voltage of each sequence, the current of each sequence and the relation between the voltage and the current of each sequence at the line break position; analyzing the two-circuit three-phase disconnection fault according to the disconnection voltage and the normal phase current at the disconnection position; the method effectively solves the problem of the same-pole four-circuit two-circuit three-phase line break fault, and makes up the vacancy of the same-pole four-circuit line break fault analysis.

Description

Method and device for analyzing three-phase disconnection fault of two lines of four-line circuit on same pole
Technical Field
The invention relates to the technical field of power transmission, in particular to a method, a device, equipment and a computer readable storage medium for analyzing three-phase line breaking faults of two lines of a same-pole four-line circuit.
Background
With the application of four circuit lines on the same pole becoming more and more extensive, the technical problems are brought while the transmission capacity is improved and the construction cost is saved. The four circuit lines on the same pole are 12 lines in total, the coupling condition is complex, mutual inductance exists between lines besides phase-to-phase mutual inductance, the faults are various, line crossing faults can occur besides single circuit line faults, line breaking faults can occur besides short circuit faults, and difficulty is brought to relay protection configuration work. At present, a relatively mature symmetric component method and a six-sequence component method are widely applied to single-circuit and double-circuit fault analysis, and researches on fault phase selection, fault distance measurement, protection configuration and the like are greatly developed.
In recent years, the fault analysis of the same-pole multi-circuit transmission line is based on phase-mode transformation. The phase-mode transformation method for double-circuit lines on the same pole is a six-sequence component method. The phase-mode conversion method popularized by the symmetrical component method creates concepts of the same vector and the opposite vector, and therefore the inter-line decoupling is completed. According to the decoupling thought, a twelve-sequence component method for the same-pole four-loop line is provided. The method inherits the line-to-line decoupling thought of a six-sequence component method, reserves a group of same vectors, popularizes the inverse vectors into three groups of loop flows in a high-order modulus space, successfully completes line-to-line decoupling, and finally realizes fault analysis. However, the above researches only aim at short-circuit faults, but have different fault analysis methods for disconnection faults, fault sequence network diagrams, comprehensive electromotive force, composite sequence network diagrams and the like, and currently, corresponding researches are lacked, so that the method has important practical significance for filling the blank of disconnection fault analysis.
The 12-sequence component method skillfully eliminates mutual inductance among the loops, eliminates mutual inductance among phases to obtain independent 12-sequence components, and is popularized and applied in the aspects of short circuit fault analysis, fault distance measurement, fault phase selection and the like of four loops on the same pole. The method mainly solves the problem of how to calculate the fault voltage and current of the same-pole four-circuit line, but does not analyze the characteristics of the line break fault, and the line break fault sequence network and the fault component equations of each sequence are different from the short-circuit fault, so that the contents of a boundary condition equation set, a composite sequence network diagram and the like need to be deeply researched.
In summary, it can be seen that how to analyze the three-phase disconnection fault of the four-circuit line on the same pole by using the twelve-sequence component method is a problem to be solved at present.
Disclosure of Invention
The invention aims to provide a method, a device, equipment and a computer readable storage medium for analyzing three-phase line-break faults of two lines of a same-pole four-line circuit, so as to solve the problem to be solved in line-break fault analysis in the prior art.
In order to solve the technical problem, the invention provides a method for analyzing a three-phase disconnection fault of two lines of a same-pole four-line circuit, which comprises the following steps: determining voltage constraint and current constraint according to boundary conditions of two-loop three-phase disconnection faults in four loops; drawing a composite sequence network diagram when the two-loop three-phase disconnection fault occurs according to the relation between the voltage constraint and the current constraint middle-sequence component; determining each sequence voltage and each sequence current according to a composite sequence network diagram, the voltage constraint and the current constraint when the two-loop three-phase disconnection fault occurs; calculating the line break voltage and the normal phase current at the line break position according to the relation among the voltage, the current and the voltage and the current at the line break position; and analyzing the two-circuit three-phase disconnection fault according to the disconnection voltage at the disconnection position and the normal phase current.
In an embodiment of the present invention, the boundary conditions of the two-loop three-phase disconnection fault in the four-loop are as follows:
Figure BDA0003259621990000021
wherein the content of the first and second substances,
Figure BDA0003259621990000022
is a return line A phase current at the broken line,
Figure BDA0003259621990000023
is a return line B phase current at the broken line,
Figure BDA0003259621990000024
is a return line C phase current at the broken line,
Figure BDA0003259621990000025
the phase A current of the two return wires at the broken wire position,
Figure BDA0003259621990000026
the B-phase current of the two return wires at the broken wire position,
Figure BDA0003259621990000027
the phase C current of the two return wires at the broken wire position,
Figure BDA0003259621990000028
the voltage drop of phase A of the three return lines at the broken line position,
Figure BDA0003259621990000029
the voltage drop of the phase B of the three return lines at the broken line position,
Figure BDA00032596219900000210
the voltage drop of the phase C of the three return lines at the broken line position,
Figure BDA00032596219900000211
for the phase A voltage drop of the four-circuit line at the broken line,
Figure BDA00032596219900000212
for the voltage drop of the phase B of the four-circuit line at the broken line,
Figure BDA00032596219900000213
the voltage drop of the phase C of the four-circuit line at the broken line is shown.
In an embodiment of the present invention, the drawing a composite sequence grid diagram at the time of the two-loop three-phase disconnection fault according to the relation between the voltage constraint and the current constraint sequence component includes:
determining a relationship of the voltage constraint and a neutral component of the current constraint according to the voltage constraint and the current constraint;
analyzing the series-parallel connection relation among the sequences according to the relation between the voltage constraint and the current constraint intermediate-sequence component, and calculating the impedance relation among the sequences;
and drawing a composite sequence network diagram when the two-loop three-phase disconnection fails according to the series-parallel connection among the sequences and the impedance relation among the sequences.
In one embodiment of the present invention, the relationship of the voltage constraint and the current constraint neutral-order component is:
Figure BDA0003259621990000031
wherein the content of the first and second substances,
Figure BDA0003259621990000032
is the current of the sequence e0,
Figure BDA0003259621990000033
is the current of the sequence e1,
Figure BDA0003259621990000034
is the current of the sequence e2,
Figure BDA0003259621990000035
is the current of the sequence f0,
Figure BDA0003259621990000036
is the current of the sequence f1,
Figure BDA0003259621990000037
is the current of the sequence f2,
Figure BDA0003259621990000038
is the current of the sequence g0,
Figure BDA0003259621990000039
is the current of the sequence g1,
Figure BDA00032596219900000310
is the current of the sequence g2,
Figure BDA00032596219900000311
is the voltage of the sequence e0 and,
Figure BDA00032596219900000312
is the voltage of the sequence e1 and,
Figure BDA00032596219900000313
is the voltage of the sequence e2 and,
Figure BDA00032596219900000314
is the voltage of the sequence g0 and,
Figure BDA00032596219900000315
is the voltage of the sequence g1 and,
Figure BDA00032596219900000316
is the voltage of the sequence g2 and,
Figure BDA00032596219900000317
is the voltage of the sequence h0,
Figure BDA00032596219900000318
is the voltage of the sequence h1,
Figure BDA00032596219900000319
is h2 series voltage.
In an embodiment of the present invention, the analyzing the series-parallel relationship between the sequences according to the relationship between the voltage constraint and the current constraint order component, and calculating the impedance relationship between the sequences:
voltage in relation to the voltage constraint and the current constraint neutral component
Figure BDA00032596219900000320
Figure BDA00032596219900000321
Determining the e1 sequence and the g1 sequence as a parallel relation;
current in a relationship according to the voltage constraint and the current constraint neutral component
Figure BDA00032596219900000322
Figure BDA00032596219900000323
Combined U ═Z is multiplied by I, and the impedance of the g1 order is calculated to be 4Zg1；
Wherein U is voltage, Z is impedance, I is current, and Z isg1Is a g1 series impedance.
In an embodiment of the present invention, the determining the sequence voltages and the sequence currents according to the composite sequence grid diagram at the time of the two-loop three-phase disconnection fault, the voltage constraints and the current constraints includes:
calculating e1 sequence voltage by using the composite sequence network diagram during the two-loop three-phase disconnection fault
Figure BDA0003259621990000041
Calculating sequence voltages of f1 sequence, g1 sequence and h1 sequence and the sequence currents according to the voltage constraint and the current constraint;
wherein Z isg1Is g1 order impedance, Ze1Is an e 1-sequence impedance,
Figure BDA0003259621990000042
the comprehensive electromotive force is seen into the system at the broken line.
In one embodiment of the present invention, the analyzing the two-loop three-phase disconnection fault according to the disconnection voltage at the disconnection point and the normal phase current comprises:
identifying a loop with a broken line fault according to the broken line voltage and the normal phase current at the broken line position;
and judging the position of the broken line fault according to the change of the voltage in each sequence before and after the broken line.
The invention also provides a device for analyzing the three-phase disconnection fault of the two circuits of the same-pole four-circuit line, which comprises the following components:
the determining and restraining module is used for calculating to obtain voltage restraint and current restraint according to boundary conditions given by two-loop three-phase disconnection faults in the four-loop;
the sequence network diagram drawing module is used for drawing a composite sequence network diagram when the two-loop three-phase disconnection fault occurs according to the relation between the voltage constraint and the current constraint sequence component;
the sequence voltage and current calculation module is used for calculating each sequence voltage and each sequence current through the composite sequence network diagram;
the line break voltage and current calculation module is used for calculating line break voltage and normal phase current between two line break points according to the voltage and the current of each sequence and by utilizing the relation between the voltage and the current of each sequence at the line break position;
and the fault analysis module is used for analyzing the two-circuit three-phase disconnection fault according to the disconnection voltage at the disconnection position and the normal phase current.
The invention also provides a device for analyzing the same-pole four-circuit two-circuit three-phase disconnection fault, which comprises:
a memory for storing a computer program; and the processor is used for realizing the steps of the method for analyzing the three-phase broken line fault of the two-circuit line and the three-phase broken line of the same pole with four circuit lines when executing the computer program.
The invention also provides a computer readable storage medium, wherein a computer program is stored on the computer readable storage medium, and when the computer program is executed by a processor, the steps of the same-pole four-circuit-line two-loop three-phase disconnection fault analysis method are realized.
The invention provides a method for analyzing two-circuit three-phase disconnection faults of a same-pole four-circuit line, which comprises the steps of firstly determining voltage constraint and current constraint according to boundary conditions of the two-circuit three-phase disconnection faults, then determining the series-parallel connection relation and impedance relation among the sequences according to the component relation among the voltage constraint and the current constraint, drawing a composite sequence network diagram when the two-circuit three-phase disconnection faults occur, determining the voltage and the current of each sequence according to the composite sequence network diagram, the voltage constraint and the current constraint, calculating the disconnection voltage and the normal phase current of the disconnection position according to the voltage, the current and the relation between the voltage and the current of each sequence of the disconnection position, and finally analyzing the two-circuit three-phase disconnection faults of the same-pole four-circuit line, and the three-phase disconnection faults of the same-pole four-circuit line, greatly reduce the calculation difficulty, the method improves the calculation accuracy and makes up the defect of line break fault analysis of the same pole four-circuit line fault.
Drawings
In order to more clearly illustrate the embodiments or technical solutions of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
Fig. 1 is a flowchart of a method for analyzing a three-phase disconnection fault of two lines on a same-pole four-line circuit according to a first embodiment of the present invention;
fig. 2 is a flowchart of a method for analyzing a three-phase disconnection fault of two lines on a same-pole four-line circuit according to a second embodiment of the present invention;
FIG. 3 is a diagram of impedance structure of four loops on the same pole;
FIG. 4a is a generic positive sequence diagram;
FIG. 4b is an e-sequence diagram;
FIG. 5 is a 12-order fault component sequence diagram;
FIG. 5a is a net view of e1 and e 2;
FIG. 5b is a net view of e 0;
FIG. 5c is a net graph of sequences f1, g1, h1, f2, g2, h 2;
FIG. 5d is a net view of f0, g0, h 0;
FIG. 6 is a composite sequence diagram of two-circuit three-phase simultaneous outage faults;
fig. 7 is a block diagram of a device for analyzing a three-phase disconnection fault of two lines on a same-pole four-line circuit according to an embodiment of the present invention.
Detailed Description
The core of the invention is to provide a method, a device, equipment and a computer readable storage medium for analyzing the two-circuit three-phase disconnection fault of the same-pole four-circuit line, thereby effectively solving the problem of the two-circuit three-phase disconnection fault.
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a flowchart illustrating a method for analyzing a three-phase disconnection fault of two lines on a same-pole four-line circuit according to a first embodiment of the present invention; the specific operation steps are as follows:
step S101: determining voltage constraint and current constraint according to boundary conditions of two-loop three-phase disconnection faults in four loops on the same pole;
step S102: drawing a composite sequence network diagram when the two-loop three-phase disconnection fault occurs according to the relation between the voltage constraint and the current constraint middle-sequence component;
step S103: determining each sequence voltage and each sequence current according to a composite sequence network diagram, the voltage constraint and the current constraint when the two-loop three-phase disconnection fault occurs;
step S104: calculating the line break voltage and the normal phase current at the line break position according to the relation among the voltage, the current and the voltage and the current at the line break position;
step S105: and analyzing the two-circuit three-phase disconnection fault according to the disconnection voltage at the disconnection position and the normal phase current.
In the method provided by the embodiment, voltage constraint and current constraint are determined according to the boundary condition of the two-loop three-phase disconnection fault, a composite sequence network diagram is drawn according to the sequence component relation in the constraint condition, then, the voltage and the current of each sequence are calculated according to the composite sequence network diagram, and then, the disconnection voltage and the normal phase current at the disconnection position are calculated for fault analysis; the method carries out deep research on the same-pole four-circuit line disconnection fault analysis, researches a calculation and analysis method of the same-pole four-circuit line disconnection fault, makes up for the same-pole four-circuit line disconnection fault analysis, and has important significance for perfecting the same-pole four-circuit line disconnection fault analysis.
Based on the above embodiment, in this embodiment, the above embodiment is described in more detail, first, a 12-sequence component method is used to decouple a four-circuit matrix on the same pole, and the decoupled matrix is used to perform disconnection fault analysis; referring to fig. 2, fig. 2 is a flowchart illustrating a method for analyzing a three-phase disconnection fault of two circuit lines and three phase lines of a four-circuit line on the same tower according to a second embodiment of the present invention; the method provided by the embodiment specifically comprises the following operation steps:
step S201: decoupling the same-pole four-loop matrix by using a 12-sequence component algorithm;
as shown in FIG. 3, the structure of the same pole four-wire loop is that the self-impedance of the line is set to ZsThe mutual impedances of the lines are respectively equal and are ZmThe mutual impedances of different loops are also equal, denoted as Zx。
In the same-pole four-loop shown in the above figure, the phase voltage and the phase current of the four-loop have a matrix equation (1-1) between them:
Figure BDA0003259621990000071
it is briefly described as
Figure BDA0003259621990000072
Wherein
Figure BDA0003259621990000073
Figure BDA0003259621990000074
Figure BDA0003259621990000075
Is the voltage drop of the three phases of the first loop,
Figure BDA0003259621990000076
Figure BDA0003259621990000081
Figure BDA0003259621990000082
is the voltage drop of the three phases of the second loop,
Figure BDA0003259621990000083
Figure BDA0003259621990000084
Figure BDA0003259621990000085
is the voltage drop of the three phases of the third loop,
Figure BDA0003259621990000086
Figure BDA0003259621990000087
Figure BDA0003259621990000088
voltage drop of three phases of the fourth circuit is achieved;
Figure BDA0003259621990000089
Figure BDA00032596219900000810
Figure BDA00032596219900000811
the phase currents for the three phases of the first loop,
Figure BDA00032596219900000812
Figure BDA00032596219900000813
Figure BDA00032596219900000814
the phase currents of the three phases of the second return line,
Figure BDA00032596219900000815
Figure BDA00032596219900000816
Figure BDA00032596219900000817
the phase currents of three phases of the third circuit are returned,
Figure BDA00032596219900000818
Figure BDA00032596219900000819
Figure BDA00032596219900000820
the phase current of the three phases of the fourth circuit is shown.
Figure BDA00032596219900000821
For the same pole four-circuit line voltage drop,
Figure BDA00032596219900000822
phase current column vector of four loops on the same pole, [ Z ]]The impedance matrix of four loops is shown, the elements on the diagonal line represent the self-impedance of each phase, and the elements on the non-diagonal line represent the inter-phase mutual impedance of each phase on the single loop and the inter-line mutual impedance of each loop respectively. Because mutual inductance exists between 12 electrical quantities of the ABC three phases of the four loops on the same pole, decoupling needs to be researched firstly when the four loops are researched, namely the mutual inductance is eliminated. The decoupling is carried out in two steps: and the mutual inductance between the outside lines of the loops is eliminated, and then the mutual inductance between the phases inside the loops is eliminated. The impedance matrix is transformed into a diagonal matrix, namely, other elements except the diagonal are zero, 12 electrical quantities are decoupled into independent 12-sequence components, and mutual inductance does not exist any more.
Let the decoupling matrix be:
Figure BDA00032596219900000823
wherein
Figure BDA00032596219900000824
The decoupled voltage and current matrix is:
Figure BDA0003259621990000091
the two-loop phase-mode transformation is noted as:
Figure BDA0003259621990000092
wherein the content of the first and second substances,
Figure BDA0003259621990000093
is a sequence voltage of a 12-sequence component,
Figure BDA0003259621990000094
is the voltage of the sequence e0 and,
Figure BDA0003259621990000095
is the voltage of the sequence f0,
Figure BDA0003259621990000096
is the voltage of the sequence g0 and,
Figure BDA0003259621990000097
is the voltage of the sequence h0,
Figure BDA0003259621990000098
is the voltage of the sequence e1 and,
Figure BDA0003259621990000099
is the voltage of the sequence f1,
Figure BDA00032596219900000910
is the voltage of the sequence g1 and,
Figure BDA00032596219900000911
is the voltage of the sequence h1,
Figure BDA00032596219900000912
is the voltage of the sequence f2,
Figure BDA00032596219900000913
is the voltage of the sequence f2,
Figure BDA00032596219900000914
is the voltage of the sequence g2 and,
Figure BDA00032596219900000915
h2 series voltage;
Figure BDA00032596219900000916
is a sequence current of a 12-sequence component,
Figure BDA00032596219900000917
is the current of the sequence e0,
Figure BDA00032596219900000918
is the current of the sequence e1,
Figure BDA00032596219900000919
is the current of the sequence e2,
Figure BDA00032596219900000920
is the current of the sequence f0,
Figure BDA00032596219900000921
is the current of the sequence f1,
Figure BDA00032596219900000922
is the current of the sequence f2,
Figure BDA00032596219900000923
is the current of the sequence g0,
Figure BDA00032596219900000924
is the current of the sequence g1,
Figure BDA00032596219900000925
is the current of the sequence g2,
Figure BDA00032596219900000926
is the current of the h0 series,
Figure BDA00032596219900000927
is the current of the h1 series,
Figure BDA00032596219900000928
is h2 series current.
From equation (1-2), one can deduce:
Figure BDA00032596219900000929
unfolding the formula (1-3) to obtain:
Figure BDA0003259621990000101
wherein z ise0＝zs+2zm+9zx，zf0＝zg0＝zh0＝zs+2zm-3zx，
ze1＝zf1＝zg1＝zh1＝ze2＝zf2＝zg2＝zh2＝zs-zm；
ze0Is an e0 series impedance, zf0Is f0 order impedance, zg0Is the g0 series impedance; z is a radical ofh0Is h0 order impedance, ze1Is an e0 series impedance, zf1Is f0 order impedance, zg1Is the g0 series impedance; z is a radical ofh1Is h0 order impedance, ze2Is an e0 series impedance, zf2Is f0 order impedance, zg2Is the g0 series impedance; z is a radical ofh2Is an h0 series impedance.
It can be seen from the inverse matrix of M that the e-sequence component reflects the co-current of the four lines, and the f-sequence component, g-sequence component and h-sequence component reflect the loop current in the four lines on the same pole. The f-sequence component, the g-sequence component and the h-sequence component only circulate in the same pole four-circuit line and do not flow out of the same pole four-circuit line, so that the voltages of the sequence components f, g and h on the buses at two ends of the same pole four-circuit line are zero, and only e-sequence voltage and current exist outside the same pole four-circuit line.
The connection between the four-circuit line on the same pole and the external system is embodied by the e-sequence component, but the e-sequence component is not directly connected with the positive sequence network of the external system but needs to be correspondingly processed. From the inverse matrix of M:
Figure BDA0003259621990000111
wherein, (i ═ 0,1, 2).
As can be seen from the equation, the e1 sequence voltage is equal to the positive sequence voltage of the four-circuit line divided by 4, i.e., the average value. Referring to the positive sequence (012) diagram of fig. 4, since the four lines are all connected to the line left end bus M, the positive sequence voltages of the four lines are equal, and thus the voltage at bus M, e1 is equal to the normal positive sequence voltage. For current, the e1 current flowing through the system impedance is equal to the sum of the positive sequence currents of the four-circuit line divided by 4, whereas the positive sequence current flowing through the system impedance in a normal positive sequence network is the sum of the positive sequence currents of the four-circuit line, so the e1 sequence current is 1/4 of the normal positive sequence current. According to ohm's law, the left system impedance in the e1 grid graph should be corrected to 4 times the value of the system impedance of the normal positive grid. The same applies to the e0 procedure and the e2 procedure, and the N-side system impedance correction method is the same as the M-side. The common positive net-ordering diagram and the e-net-ordering diagram of the four-circuit line on the same pole can be seen in fig. 4.
Step S202: drawing each sequence network diagram of the broken line fault according to each sequence network diagram of the short circuit fault, and determining the relation between each sequence voltage and current at the broken line;
according to the sequence network diagrams of the short-circuit faults, the sequence network diagrams of the broken line faults can be drawn, but when the broken line faults are different from the short-circuit faults, the sequence impedance is in a series relation when the broken line faults are seen from the broken port. A 12-order fault component sequence net diagram is shown in fig. 5.
From the 12-sequence component method, only the e1 sequence is an active network, and the other sequence components are passive networks. The voltage and current equations at the line break are as follows:
Figure BDA0003259621990000121
Figure BDA0003259621990000122
Figure BDA0003259621990000123
Figure BDA0003259621990000124
Figure BDA0003259621990000125
(i is 0,1,2) is the voltage component of each sequence at the broken line,
Figure BDA0003259621990000126
for the combined electromotive force of the broken wire looking into the system, wherein
Figure BDA0003259621990000127
E is the equivalent electromotive force on both sides of the line, delta is the phase angle between the electromotive forces on both sides of the line,
Figure BDA0003259621990000128
Figure BDA0003259621990000129
Figure BDA00032596219900001210
Figure BDA00032596219900001211
(i is 0,1,2) is the current component of each sequence at the broken line,
Figure BDA00032596219900001212
Figure BDA00032596219900001213
Figure BDA00032596219900001214
Figure BDA00032596219900001215
each sequence impedance is seen from the broken line to the system (i is 0,1, 2).
Step S203: determining voltage constraint and current constraint according to boundary conditions of three-phase disconnection faults of two lines of a four-line circuit;
taking I, II loop three-phase disconnection fault as an example, the boundary conditions are:
Figure BDA00032596219900001216
wherein the content of the first and second substances,
Figure BDA00032596219900001217
is a return line A phase current at the broken line,
Figure BDA00032596219900001218
is a return line B phase current at the broken line,
Figure BDA00032596219900001219
is a return line C phase current at the broken line,
Figure BDA00032596219900001220
the phase A current of the two return wires at the broken wire position,
Figure BDA00032596219900001221
the B-phase current of the two return wires at the broken wire position,
Figure BDA00032596219900001222
the phase C current of the two return wires at the broken wire position,
Figure BDA00032596219900001223
the voltage drop of phase A of the three return lines at the broken line position,
Figure BDA00032596219900001224
the voltage drop of the phase B of the three return lines at the broken line position,
Figure BDA00032596219900001225
the voltage drop of the phase C of the three return lines at the broken line position,
Figure BDA00032596219900001226
for the phase A voltage drop of the four-circuit line at the broken line,
Figure BDA00032596219900001227
for the voltage drop of the phase B of the four-circuit line at the broken line,
Figure BDA00032596219900001228
the voltage drop of the phase C of the four-circuit line at the broken line is shown.
By substituting the above formula (2-1) for the formula (1-2), the relationship of the respective sequence components can be obtained as follows:
Figure BDA0003259621990000131
through simplification, the method can obtain:
Figure BDA0003259621990000132
wherein the content of the first and second substances,
Figure BDA00032596219900001321
Figure BDA0003259621990000133
is the current of the sequence e0,
Figure BDA0003259621990000134
is the current of the sequence e1,
Figure BDA0003259621990000135
is the current of the sequence e2,
Figure BDA0003259621990000136
is the current of the sequence f0,
Figure BDA0003259621990000137
is the current of the sequence f1,
Figure BDA0003259621990000138
is the current of the sequence f2,
Figure BDA0003259621990000139
is the current of the sequence g0,
Figure BDA00032596219900001310
is the current of the sequence g1,
Figure BDA00032596219900001311
is the current of the sequence g2,
Figure BDA00032596219900001312
is the voltage of the sequence e0 and,
Figure BDA00032596219900001313
is the voltage of the sequence e1 and,
Figure BDA00032596219900001314
is the voltage of the sequence e2 and,
Figure BDA00032596219900001315
is the voltage of the sequence g0 and,
Figure BDA00032596219900001316
is the voltage of the sequence g1 and,
Figure BDA00032596219900001317
is the voltage of the sequence g2 and,
Figure BDA00032596219900001318
is the voltage of the sequence h0,
Figure BDA00032596219900001319
is the voltage of the sequence h1,
Figure BDA00032596219900001320
is h2 series voltage.
Step S204: analyzing the series-parallel relation among the sequences according to the relation between the voltage constraint and the current constraint medium sequence component, calculating the impedance relation among the sequences, and drawing a composite sequence network diagram when the two-loop three-phase disconnection fails;
according to the voltage constraint and the current constraint conditions, a composite sequence network diagram of the I, II loop when the three-phase disconnection fault occurs can be drawn, as shown in fig. 6, the specific analysis is as follows:
except the sequence e1, the other 11-sequence components are passive networks, the sequence component which has no direct relation with the sequence e1 is 0 according to the relation between voltage and current, and the sequence components except the sequences e1, f1, g1 and h1 are all 0.
According to voltage relation
Figure BDA0003259621990000141
The voltage of e1 sequence can be set to be connected in parallel with g1 sequence after passing through a transformer with a transformation ratio of 1: 2.
According to the current relation
Figure BDA0003259621990000142
The sequence e1 is connected with the sequence g1 in parallel. By comprehensively considering the voltage relation and the current relation, the e1 and g1 sequence voltage and sequence current proportionality coefficients are not 1, and g1 sequence impedance needs to be corrected. Setting the sequence g1 as the primary side of the transformer, and keeping the secondary side current of the transformer
Figure BDA0003259621990000143
The temperature of the molten steel is not changed,
Figure BDA0003259621990000144
after passing through a transformer with a transformation ratio of 1: 2, the primary side current becomes
Figure BDA0003259621990000145
Maintaining sequence voltage on sequence impedance
Figure BDA0003259621990000146
Ratio ofThe coefficient is 1, namely the primary voltage of the transformer is not changed, and g 1-sequence impedance correction is 4Zg1。
Step S205: determining each sequence voltage and each sequence current according to a composite sequence network diagram, the voltage constraint and the current constraint when the two-loop three-phase disconnection fault occurs;
from FIG. 4, it can be quickly deduced
Figure BDA00032596219900001412
The equation (2-4) of (a),
Figure BDA0003259621990000147
the g1 and h1 series voltages can be calculated by the formula (2-3),
Figure BDA0003259621990000148
according to the e1 and f1 sequence current relationship in the formula (2-3)
Figure BDA0003259621990000149
The relationship between the e1 and the f1 sequence voltage can be obtained
Figure BDA00032596219900001410
After e1, f1, g1 and h1 sequence voltages are obtained, the sequence currents can be calculated through (1-5);
wherein Z ise1Is an e1 series impedance, Zg1Is g1 order impedance, Zf1Is an impedance of the order of f1,
Figure BDA00032596219900001411
the comprehensive electromotive force is seen into the system at the broken line.
Step S206: calculating the line break voltage and the normal phase current at the line break position according to the relation among the voltage, the current and the voltage and the current at the line break position;
using the above-obtained e1, f1, g1 and h1 series voltages and e1, f1, g1 and h1 series currents according to the formula (1-2)
Figure BDA0003259621990000151
And calculating the voltage between the two points of the broken line and the normal phase current.
Step S207: and analyzing the two-circuit three-phase disconnection fault according to the disconnection voltage at the disconnection position and the normal phase current.
The extreme operation condition of the four circuit lines on the same tower is considered, when a certain circuit is broken, the network structure change and various electrical quantity characteristics under the broken line fault are researched, the stability analysis can be carried out on the abnormal state operation of the four circuit line power transmission system, and the relay protection configuration of the four circuit lines can be perfected. By analyzing the distribution characteristics of the sequential voltage after the line break of the power transmission line, the imbalance and the discontinuous voltage of the system caused by the longitudinal line break are pointed out, and the amplitude difference of the sequential voltage at two sides of the break is larger.
The method provided by the embodiment of the invention comprises the steps of calculating a matrix of four circuit lines on the same pole by using a 12-sequence component method to obtain a decoupled matrix, determining voltage and current constraints according to boundary conditions of a three-phase disconnection fault of two circuit lines, analyzing the voltage and current relationship among the sequences, drawing a composite sequence network diagram, calculating e 1-sequence voltage with only one unknown quantity by using the composite sequence network diagram, calculating other-sequence voltage and sequence current according to the voltage constraint and current constraint relationship, calculating disconnection voltage and normal phase current at the disconnection position by using the sequence voltage and the sequence current, and analyzing the disconnection circuit and the disconnection fault position, wherein the method provided by the invention can be used as a basic theory for analyzing the electrical quantity characteristic when any two disconnection lines on the same pole run by using the 12-sequence component method to analyze the three-phase disconnection fault of the two circuit lines, reduces the calculation difficulty, improves the calculation precision, makes up the disconnection fault calculation and analysis of the four circuit lines on the same pole, an effective tool is provided for the research of protection action characteristics and system stability, and the method has important significance for perfecting fault analysis of four circuit lines on the same pole.
Referring to fig. 7, fig. 7 is a block diagram of a device for analyzing a three-phase disconnection fault of two lines on a same-pole four-line circuit according to an embodiment of the present invention; the specific device may include:
the constraint determining module 100 is configured to calculate voltage constraint and current constraint according to a boundary condition given by a two-loop three-phase disconnection fault in four loops;
a grid-sequence diagram drawing module 200, configured to draw a composite grid-sequence diagram when the two-loop three-phase disconnection fault occurs according to a relationship between the voltage constraint and a neutral-sequence component of the current constraint;
a sequence voltage and current calculation module 300, configured to calculate each sequence voltage and each sequence current through the composite sequence net diagram;
a line break voltage and current calculating module 400, configured to calculate, according to the voltages and currents of the sequences, a line break voltage and a normal phase current between two points of line break by using a relationship between the voltages and currents of the sequences at the line break;
and the fault analysis module 500 is configured to analyze the two-circuit three-phase disconnection fault according to the disconnection voltage at the disconnection point and the normal phase current.
The apparatus for analyzing a three-phase disconnection fault of a two-circuit line on a same bar, four-circuit line in this embodiment is used to implement the method for analyzing a three-phase disconnection fault of a two-circuit line on a same bar, four-circuit line in the same bar, two-circuit line in the same bar, three-phase disconnection fault, and thus the specific implementation manner of the apparatus for analyzing a three-phase disconnection fault of a two-circuit line on a same bar, four-circuit line in the same bar, three-phase disconnection fault can be found in the embodiments of the method for analyzing a three-phase disconnection fault of a two-circuit line on a same bar, for example, the constraint determining module 100, the sequence diagram drawing module 200, the sequence voltage and current calculating module 300, the disconnection voltage and current calculating module 400, and the fault analyzing module 500 are respectively used to implement the steps S101, S102, S103, S104, and S105 in the method for analyzing a three-phase disconnection fault of a two-circuit line on a same bar, four-circuit line in a same bar, three-circuit line, three-phase disconnection fault, and therefore, the description of the specific implementation manner can refer to the description of each embodiment of the description of the corresponding embodiments of each section.
The embodiment of the present invention further provides a device for analyzing a three-phase disconnection fault of two lines on a same-pole four-line circuit, including: a memory for storing a computer program; and the processor is used for realizing the steps of the method for analyzing the three-phase disconnection fault of the two lines on the same-pole four-circuit line when executing the computer program.
The specific embodiment of the present invention further provides a computer readable storage medium, where a computer program is stored on the computer readable storage medium, and when the computer program is executed by a processor, the method for analyzing the three-phase disconnection fault of the two lines on the same four-line circuit on the same pole is implemented.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The method, the device, the equipment and the computer readable storage medium for analyzing the three-phase disconnection fault of the two circuits of the same-pole four-circuit line provided by the invention are described in detail above. The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.

Claims (10)

1. A method for analyzing three-phase disconnection faults of two circuits of a same-pole four-circuit line is characterized by comprising the following steps of:
determining voltage constraint and current constraint according to boundary conditions of two-loop three-phase disconnection faults in four loops;
drawing a composite sequence network diagram when the two-loop three-phase disconnection fault occurs according to the relation between the voltage constraint and the current constraint middle-sequence component;
determining each sequence voltage and each sequence current according to a composite sequence network diagram, the voltage constraint and the current constraint when the two-loop three-phase disconnection fault occurs;
calculating the line break voltage and the normal phase current at the line break position according to the relation among the voltage, the current and the voltage and the current at the line break position;
and analyzing the two-circuit three-phase disconnection fault according to the disconnection voltage at the disconnection position and the normal phase current.
2. The method of claim 1, wherein the boundary conditions for a two-loop three-phase disconnection fault in the four-loop line are:
Figure FDA0003259621980000011
wherein the content of the first and second substances,
Figure FDA0003259621980000012
is a return line A phase current at the broken line,
Figure FDA0003259621980000013
is a return line B phase current at the broken line,
Figure FDA0003259621980000014
is a return line C phase current at the broken line,
Figure FDA0003259621980000015
the phase A current of the two return wires at the broken wire position,
Figure FDA0003259621980000016
the B-phase current of the two return wires at the broken wire position,
Figure FDA0003259621980000017
the phase C current of the two return wires at the broken wire position,
Figure FDA0003259621980000018
the voltage drop of phase A of the three return lines at the broken line position,
Figure FDA0003259621980000019
the voltage drop of the phase B of the three return lines at the broken line position,
Figure FDA00032596219800000110
the voltage drop of the phase C of the three return lines at the broken line position,
Figure FDA00032596219800000111
for the phase A voltage drop of the four-circuit line at the broken line,
Figure FDA00032596219800000112
for the voltage drop of the phase B of the four-circuit line at the broken line,
Figure FDA00032596219800000113
the voltage drop of the phase C of the four-circuit line at the broken line is shown.
3. The method of claim 1, wherein said plotting a composite sequence net graph for said two-loop three-phase open-wire fault from a relationship of said voltage constraint and said current constraint neutral component comprises:
determining a relationship of the voltage constraint and a neutral component of the current constraint according to the voltage constraint and the current constraint;
analyzing the series-parallel connection relation among the sequences according to the relation between the voltage constraint and the current constraint intermediate-sequence component, and calculating the impedance relation among the sequences;
and drawing a composite sequence network diagram when the two-loop three-phase disconnection fails according to the series-parallel connection among the sequences and the impedance relation among the sequences.
4. The method of claim 1, wherein the voltage constraint and the current constraint have a relationship of a neutral-order component:
Figure FDA0003259621980000021
wherein the content of the first and second substances,
Figure FDA0003259621980000022
is the current of the sequence e0,
Figure FDA0003259621980000023
is the current of the sequence e1,
Figure FDA0003259621980000024
is the current of the sequence e2,
Figure FDA0003259621980000025
is the current of the sequence f0,
Figure FDA0003259621980000026
is f1 sequence electricityThe flow of the stream(s),
Figure FDA0003259621980000027
is the current of the sequence f2,
Figure FDA0003259621980000028
is the current of the sequence g0,
Figure FDA0003259621980000029
is the current of the sequence g1,
Figure FDA00032596219800000210
is the current of the sequence g2,
Figure FDA00032596219800000211
is the voltage of the sequence e0 and,
Figure FDA00032596219800000212
is the voltage of the sequence e1 and,
Figure FDA00032596219800000213
is the voltage of the sequence e2 and,
Figure FDA00032596219800000214
is the voltage of the sequence g0 and,
Figure FDA00032596219800000215
is the voltage of the sequence g1 and,
Figure FDA00032596219800000216
is the voltage of the sequence g2 and,
Figure FDA00032596219800000217
is the voltage of the sequence h0,
Figure FDA00032596219800000218
is the voltage of the sequence h1,
Figure FDA00032596219800000219
is h2 series voltage.
5. The method of claim 3, wherein the series-parallel relationship between the sequences is analyzed according to the relationship of the voltage constraint and the current constraint neutral component, and the impedance relationship between the sequences is calculated:
voltage in relation to the voltage constraint and the current constraint neutral component
Figure FDA00032596219800000220
Figure FDA00032596219800000221
And determining the e1 sequence and the g1 sequence as a parallel relation.
Current in a relationship according to the voltage constraint and the current constraint neutral component
Figure FDA00032596219800000222
Figure FDA00032596219800000223
Combining U with Z multiplied by I, calculating the impedance of the sequence g1 to be 4Zg1；
Wherein U is voltage, Z is impedance, I is current, and Z isg1Is a g1 series impedance.
6. The method of claim 1, wherein determining the sequence voltages and the sequence currents according to the composite sequence grid map at the time of the two-loop three-phase line break fault, the voltage constraints, and the current constraints comprises:
calculating e1 sequence voltage by using the composite sequence network diagram during the two-loop three-phase disconnection fault
Figure FDA0003259621980000031
Calculating sequence voltages of f1 sequence, g1 sequence and h1 sequence and the sequence currents according to the voltage constraint and the current constraint;
wherein Z isg1Is g1 order impedance, Ze1Is an e 1-sequence impedance,
Figure FDA0003259621980000032
the comprehensive electromotive force is seen into the system at the broken line.
7. The method of claim 1, wherein analyzing the two-loop, three-phase wire break fault based on the wire break voltage at the wire break and the normal phase current comprises:
identifying a loop with a broken line fault according to the broken line voltage and the normal phase current at the broken line position;
and judging the position of the broken line fault according to the change of the voltage in each sequence before and after the broken line.
8. The utility model provides a device of two return wire three-phase disconnection fault analysis of four return wires on same pole which characterized in that includes:
the determining and restraining module is used for calculating to obtain voltage restraint and current restraint according to boundary conditions given by two-loop three-phase disconnection faults in the four-loop;
the sequence network diagram drawing module is used for drawing a composite sequence network diagram when the two-loop three-phase disconnection fault occurs according to the relation between the voltage constraint and the current constraint sequence component;
the sequence voltage and current calculation module is used for calculating each sequence voltage and each sequence current through the composite sequence network diagram;
the line break voltage and current calculation module is used for calculating line break voltage and normal phase current between two line break points according to the voltage and the current of each sequence and by utilizing the relation between the voltage and the current of each sequence at the line break position;
and the fault analysis module is used for analyzing the two-circuit three-phase disconnection fault according to the disconnection voltage at the disconnection position and the normal phase current.
9. The utility model provides a two return wire three-phase disconnection fault analysis's of same pole four return wires equipment which characterized in that includes:
a memory for storing a computer program;
a processor for implementing the steps of a method for analyzing the same pole four-circuit two-circuit three-phase disconnection fault as claimed in any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of a method for analyzing three-phase disconnection fault in two lines on the same pole with four lines as claimed in any one of claims 1 to 7.
CN202111069613.7A 2021-09-13 2021-09-13 Method and device for analyzing three-phase disconnection fault of two lines of four-line circuit on same pole Pending CN114019295A (en)

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