CN114006520B - High-voltage integrated circuit and semiconductor circuit - Google Patents
High-voltage integrated circuit and semiconductor circuit Download PDFInfo
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- CN114006520B CN114006520B CN202111252744.9A CN202111252744A CN114006520B CN 114006520 B CN114006520 B CN 114006520B CN 202111252744 A CN202111252744 A CN 202111252744A CN 114006520 B CN114006520 B CN 114006520B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000006243 chemical reaction Methods 0.000 claims abstract description 15
- 230000000694 effects Effects 0.000 claims abstract description 8
- 238000001514 detection method Methods 0.000 claims description 53
- 239000000758 substrate Substances 0.000 claims description 22
- 230000005669 field effect Effects 0.000 claims description 9
- 238000001914 filtration Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 17
- 238000013461 design Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000000087 stabilizing effect Effects 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 208000033999 Device damage Diseases 0.000 description 1
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- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
- H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
- H02H7/1203—Circuits independent of the type of conversion
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to a high voltage integrated circuit comprising: the bootstrap circuit, the high-voltage conversion circuit and the high-voltage output driver are electrically connected in sequence, and the output end of the high-voltage output driver is connected with the output pin of the corresponding chip; a switching tube is arranged between the bootstrap circuit and the power supply end, the switching tube is configured to be in a normally open state, and when the latch effect of the circuit is detected, the switching tube is switched to be in a closed state; the filter conversion circuit, the dead zone interlocking circuit and the input circuit are electrically connected in sequence, the power end is electrically connected with the input end of the voltage strip protection circuit, the second output end of the voltage strip protection circuit is connected with the other end of the delay circuit through the low-voltage conversion circuit and the output pin of the corresponding chip, and the voltage strip protection circuit is provided with a switch port and the grid electrode of the switch tube. The invention also provides a semiconductor circuit, and the scheme can solve the problem that the VCC port is easy to fail when the semiconductor circuit is impacted by excessive high voltage, so that the use stability is improved.
Description
Technical Field
The invention relates to a high-voltage integrated circuit and a semiconductor circuit, belonging to the technical field of power semiconductor devices.
Background
The smart power module, IPM (Intelligent Power Module), is a power driven product that combines power electronics and integrated circuit technology. The intelligent power module integrates the power switch device and the high-voltage driving circuit and is internally provided with fault detection circuits such as overvoltage, overcurrent, overheat and the like. The intelligent power module receives the control signal of the MCU on one hand, drives the subsequent circuit to work, and sends the state detection signal of the system back to the MCU on the other hand.
Compared with the traditional discrete scheme, the intelligent power module gains larger and larger markets by virtue of the advantages of high integration level, high reliability and the like, is particularly suitable for a frequency converter of a driving motor and various inverter power supplies, and is an ideal power electronic device for frequency conversion speed regulation, metallurgical machinery, electric traction, servo driving and frequency conversion household appliances.
A high voltage integrated circuit, HVIC, is an integrated circuit product that converts MCU signals into drive IGBT signals. The HVIC integrates a P field effect transistor, an N field effect transistor, a triode, a diode, a voltage stabilizing tube, a resistor and a capacitor to form circuits such as a Schmidt circuit, a low voltage LEVELSHIFT circuit, a high voltage LEVELSHIFT circuit, a pulse generating circuit, a dead zone circuit, an interlocking circuit, a delay circuit, a filter circuit, an overcurrent protection circuit, an overheat protection circuit, an undervoltage detection circuit, a bootstrap circuit and the like. On one hand, the HVIC receives the control signal of the MCU to drive the subsequent IGBT or MOS to work, and on the other hand, the HVIC sends the state detection signal of the system back to the MCU. Is a critical chip inside the IPM.
The HVIC of the existing IPM has only VCC under-voltage protection function, has no over-voltage protection, and when surge voltage occurs, the clamping voltage of the internal voltage-stabilizing diode is higher, so that the protection function cannot be realized. External TVS tubes are needed, and the application cost of clients is increased. The surge voltage can cause the ESD tube to be opened and clamped, the latch-up phenomenon occurs when the VCC current cannot be normally closed, damage is caused to internal low-power devices, HVIC failure is caused, and IPM cannot normally work.
Disclosure of Invention
The technical problem to be solved by the invention is to solve the problem that the VCC port is easy to fail when the high-voltage integrated chip in the semiconductor circuit is impacted by the over-high voltage.
Specifically, the present invention discloses a high voltage integrated circuit comprising:
the output end of the high-voltage output drive is connected with the output pin of the corresponding chip; a switching tube is further arranged between the bootstrap circuit and the power supply end, the switching tube is configured to be in a normally open state, and when the latch effect of the circuit is detected, the switching tube is switched to be in a closed state;
The filter conversion circuit, the dead zone interlocking circuit and the input circuit are electrically connected in sequence, the input circuit is electrically connected with one end of the pulse circuit and one end of the delay circuit respectively, the power end is electrically connected with the input end of the voltage strip protection circuit, the first output end of the voltage strip protection circuit is electrically connected with one end of the pulse circuit, the other end of the pulse circuit is electrically connected with the high-voltage output drive through the high-voltage conversion circuit, the second output end of the voltage strip protection circuit is electrically connected with the other end of the delay circuit through the low-voltage conversion circuit and the corresponding chip output pins, and the voltage strip protection circuit is provided with a switch port and a grid electrode of the switch tube.
Optionally, the voltage band protection circuit comprises an undervoltage detection circuit, an overvoltage timing circuit and a logic control circuit; the overvoltage detection circuit is electrically connected with the overvoltage timing circuit, the power supply end is electrically connected with the input end of the logic control circuit through the undervoltage detection circuit, the overvoltage detection circuit and the overvoltage timing circuit respectively, and the output end of the logic control circuit comprises a first output end and a second output end.
Optionally, the under-voltage detection circuit includes a first bias circuit, a first comparator and a first logic circuit, the power end is electrically connected with the first logic circuit through the first bias circuit and the first comparator in sequence, and the output end of the first logic circuit is electrically connected with the input end of the logic control circuit.
Optionally, the overvoltage detection circuit includes a second bias circuit, a second comparator and a second logic circuit, the power end is electrically connected with the second logic circuit sequentially through the second bias circuit and the second comparator, and the output end of the second logic circuit is electrically connected with the input end of the logic control circuit and the input end of the overvoltage timing circuit respectively.
Optionally, the overvoltage timing circuit includes an input logic circuit, an RC delay circuit, a third comparator and an output logic circuit electrically connected in sequence, an output end of the second logic circuit is electrically connected with the input logic circuit, and the output logic circuit is electrically connected with an input end of the logic control circuit.
Optionally, the RC delay circuit is configured to any one of 10-20 ms.
Optionally, the logic control circuit includes a first not gate module, a second not gate module, a third not gate module, a fourth not gate module, a first not gate module and a second not gate module; the output end of the overvoltage detection circuit is electrically connected with the input end of the first NAND gate module, and the output end of the overvoltage timing circuit is electrically connected with the input end of the first NAND gate module through the first NAND gate module; the under-voltage detection module is electrically connected with the input end of the second NAND gate module through the second NAND gate module, the output end of the first NAND gate module is electrically connected with the input end of the second NAND gate module through the third NAND gate module, the output end of the second NAND gate module is electrically connected with the F0 end through the fourth NAND gate module, and the output end of the second NAND gate module is electrically connected with the corresponding EN-end, H end and L end.
Optionally, the switching tube is a field effect tube.
The invention also discloses a semiconductor circuit, which comprises a module frame, a high-voltage integrated chip and a transistor, wherein the high-voltage integrated chip comprises the high-voltage integrated circuit according to any one of the purposes of the invention, the high-voltage integrated chip comprises an input pin and an output pin, the module frame is provided with an input connection point and an output connection point, the high-voltage integrated chip and the transistor are both arranged at the module frame, the output pins of the high-voltage integrated chip are connected with the output connection point at the module frame through the corresponding transistors, and the input pin of the high-voltage integrated chip is connected with the input connection point at the module frame.
Optionally, the substrate architecture of the intelligent power chip adopts any one of an IMS substrate architecture, a DBC substrate architecture and a CIS substrate architecture.
The switching tube in the high-voltage integrated circuit is in a normally open state, and the voltage stabilizing diode can normally release surge voltage when the switching tube is conducted. However, when the latch-up occurs, the switching tube is closed, and when the switching tube is closed, the withstand voltage of the switching tube plus the withstand voltage of the zener diode is higher than 50V, so that almost all surge voltages can be blocked; and corresponding overvoltage protection and undervoltage protection functions are set by combining the voltage strip protection circuit, so that the stability of the high-voltage integrated circuit is improved, and the use stability of the intelligent power chip is further improved.
Drawings
Fig. 1 is a schematic diagram of a VCC terminal of a high voltage integrated chip according to an embodiment of the present invention being failed by impact;
FIG. 2 is a schematic circuit diagram of a high voltage integrated circuit according to an embodiment of the present invention;
FIG. 3 is a schematic block diagram of a voltage band protection circuit according to an embodiment of the present invention;
FIG. 4 is a schematic block diagram of a brown-out detection circuit according to an embodiment of the present invention;
FIG. 5 is a schematic block diagram of an overvoltage detection circuit according to an embodiment of the present invention;
FIG. 6 is a schematic block diagram of an overvoltage timing circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a logic control circuit according to an embodiment of the present invention;
fig. 8 is a diagram illustrating a package structure of an intelligent power chip according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a substrate structure of an intelligent power chip according to an embodiment of the present invention.
Detailed Description
In addition, in the case where the structure or the function is not conflicting, the embodiments of the present invention and the features in the embodiments may be combined with each other. The invention is described in detail below with reference to examples.
Example 1
The HVIC of the existing IPM has only VCC under-voltage protection function, has no over-voltage protection, and when surge voltage occurs, the clamping voltage of the internal voltage-stabilizing diode is higher, so that the protection function cannot be realized. The TVS tube is required to be externally connected, so that the problem of the application cost of the client is increased. And surge voltage can cause the ESD tube to be opened and clamped, the latch-up phenomenon occurs when VCC current cannot be normally closed, damage is caused to internal low-power devices, HVIC failure is caused, and IPM cannot normally work. Specifically, as shown in fig. 1, fig. 1 is a schematic diagram illustrating that a VCC terminal of a high voltage integrated chip provided in an embodiment of the present invention is failed by impact.
The invention provides a high-voltage integrated circuit. As shown in fig. 2, which discloses a high voltage integrated circuit, comprising:
The bootstrap circuit 10, the high-voltage conversion circuit 20 and the high-voltage output driver 30 are electrically connected in sequence, and the output end of the high-voltage output driver 30 is connected with the output pin of the corresponding chip; a switching tube 40 is further arranged between the bootstrap circuit 10 and the power supply end, the switching tube 40 is configured to be in a normally open state, and when the latch effect of the circuit is detected, the switching tube 40 is switched to be in a closed state;
The filter conversion circuit 50, the dead zone interlocking circuit 60 and the input circuit 70 which are electrically connected in sequence, wherein the input circuit 70 is electrically connected with one end of the pulse circuit 80 and one end of the delay circuit 90 respectively, a power end is electrically connected with the input end of the belt pressing protection circuit 100, a first output end of the belt pressing protection circuit 100 is electrically connected with one end of the pulse circuit 80, the other end of the pulse circuit 80 is electrically connected with the high-voltage output drive 30 through the high-voltage conversion circuit 20, a second output end of the belt pressing protection circuit 100 is electrically connected with the other end of the delay circuit 90 through the low-voltage conversion circuit, and the belt pressing protection circuit 100 is provided with a switch port and a grid electrode of the switch tube 40.
Latch-up is a parasitic effect specific to CMOS processes, which can seriously lead to failure of the circuit or even burn out the chip. The latch-up effect is generated by an N-P-N-P structure formed by an active region of an NMOS, a P substrate, an N well and an active region of a PMOS, and when one triode is positively biased, positive feedback is formed to form a latch-up. The method for avoiding latch-up is to reduce the parasitic resistance of the substrate and the N well so that the parasitic transistor is not in a forward bias state. Static electricity is an invisible destructive force that affects electronic components. ESD and related voltage transients both cause latch-up, one of the main causes of semiconductor device failure. If a strong electric field is applied to the oxide film in the device structure, the oxide film may be damaged by dielectric breakdown. Very thin metallized traces can be damaged by high currents and can create an open circuit due to overheating caused by surge currents. This is the so-called "latch-up". In the case of latch-up, the device forms a short circuit between the power supply and ground, causing large currents, EOS (electrical overload) and device damage. In order to protect the chip circuit, in the implementation, the switching tube 40 may be a triode or a field effect tube, which are both common electronic components, and the main function of the switching tube is to cut off and conduct the circuit, in the embodiment of the present invention, a field effect tube is more preferably used as the switching tube 40, and the field effect tube is a MOS tube, that is, a G1 shown in fig. 2, and in the implementation, a diode is connected in series with the drain electrode of the field effect tube, and the purpose of the diode is to protect the field effect tube. The specific working principle of setting the MOS tube is as follows: the VCC pull-down circuit is added with an MOS tube as a switch tube 40, the MOS tube is in a normally open state, and the voltage stabilizing diode can normally release surge voltage when the MOS tube is conducted. However, when the latch-up effect occurs, the MOS tube is closed, and when the MOS tube is closed, the MOS withstand voltage plus the zener diode withstand voltage is higher than 50V, so that almost all surge voltages can be blocked, and the protection of a chip circuit can be effectively realized.
The voltage band protection circuit 100 provided by the embodiment of the invention has the functions of under-voltage protection and over-voltage protection, and the voltage band protection has at least 6 ports such as VCC, EN-, FO, G1, H, L and the like. The input end of the belt pressing protection circuit 100 is a VCC end, the first output end of the belt pressing protection circuit 100 is an H end, the second output end of the belt pressing protection circuit 100 is an L end, the switch port of the belt pressing protection circuit 100 is a G1, the belt pressing protection circuit 100 is electrically connected with the switch tube 40 through the G1, and the enable end of the belt pressing protection circuit 100 is EN-. In the embodiment of the invention, the VCC port is connected to the VCC voltage of the HVIC for detecting whether the VCC voltage is too high or too low. EN-is that when under-voltage or over-voltage occurs, the circuit outputs a disable signal to the HVIC logic circuit, and when the HVIC does not have the enable signal, the internal logic circuit is closed to stop working. The FO signal is a valid signal which is input into the FO (fault reporting circuit) of the HVIC by the circuit when under-voltage or over-voltage occurs, so that the HVIC outputs FO (fault) information to the MCU, and the MCU stops working. G1 is a gate connected to the VCC pull-down MOS tube, when overvoltage occurs and a period of time is delayed, the voltage is abnormal, and possibly the VCC port is flowing a large current, at this time, the pull-down MOS is turned off by the voltage band protection circuit 100 through G1, so that the current is turned off, and the circuit is prevented from being burnt out continuously with a large current. H and L are signals controlling the high side logic and the low side logic, respectively, which are turned off when undervoltage and overvoltage occur. The high-side logic is connected before the pulse generator, and the low-side logic is connected before the output driving circuit. Through the use of the switching tube 40 in conjunction with the push belt protection circuit 100,
More preferably, fig. 3 is a schematic circuit block diagram of a voltage band protection circuit 100 according to an embodiment of the present invention, as shown in fig. 3, the voltage band protection circuit 100 includes an under-voltage detection circuit 110, an over-voltage detection circuit 120, an over-voltage timing circuit 130, and a logic control circuit 140; the overvoltage detection circuit 120 is electrically connected with the overvoltage timing circuit 130, the power supply terminal is electrically connected with the input terminal of the logic control circuit 140 through the undervoltage detection circuit 110, the overvoltage detection circuit 120 and the overvoltage timing circuit 130, and the output terminal of the logic control circuit 140 comprises a first output terminal and a second output terminal.
The voltage band protection circuit 100 in the embodiment of the present invention is composed of at least 4 parts: 1) An undervoltage detection circuit 110; 2) An overvoltage detection circuit 120; 3) An overvoltage timing circuit 130; 4) Logic control circuit 140. Specifically, the brown-out detection circuit 110 is consistent with a conventional brown-out detection circuit 110, and is configured to detect a VCC voltage, output a brown-out signal when detecting that the VCC voltage is too low, and process the brown-out signal by a logic circuit. The overvoltage detection circuit 120 is configured to detect a VCC voltage, output an overvoltage signal when detecting that the VCC voltage is too high, and send a timing signal to the timing circuit at the same time, and after the timing is completed, the timer returns a timing completion signal to the overvoltage detection circuit 120, and the overvoltage detection circuit 120 detects the VCC voltage again, if the VCC voltage is still overvoltage, it is determined as an abnormal condition, and then overvoltage protection is started. The overvoltage timing circuit 130 starts timing when receiving the overvoltage signal from the overvoltage detection circuit 120, and feeds back a timing completion signal to the overvoltage detection circuit 120 after timing is completed, and simultaneously sends the timing completion signal to the logic control circuit 140.
The logic control circuit 140 performs a comprehensive process on the undervoltage detection signal, the overvoltage detection signal, the second overvoltage detection signal after timing, the timing start signal and the completion signal, when the undervoltage detection signal or the overvoltage detection signal occurs, the logic control circuit 140 outputs a protection signal to turn off the HVIC, but the VCC pull-down MOS is not turned off at this time, and the surge can still be released. When the timing is finished, the overvoltage detection signal still appears, which indicates that the overvoltage time is too long and the latch is possible, so the logic control circuit 140 turns off the MOS transistor and cuts off the current to make the HVIC jump out of the latch state. Through the synthesis of the signals, the latch-up effect can be more effectively detected, and the effective use of the user chip can be ensured.
More preferably, fig. 4 is a schematic circuit block diagram of the undervoltage detection circuit according to the embodiment of the present invention, as shown in fig. 4, the undervoltage detection circuit 110 includes a first bias circuit, a first comparator, and a first logic circuit, a power supply terminal is electrically connected to the first logic circuit through the first bias circuit and the first comparator in sequence, and an output terminal of the first logic circuit is electrically connected to an input terminal of the logic control circuit 140.
The undervoltage detection circuit 110 provided by the embodiment of the invention is composed of a comparator, a BIAS circuit and a logic circuit, wherein the comparator is used for comparing the voltage obtained by dividing the VCC voltage resistance with a set voltage, and when the divided voltage is lower than the set voltage, the VCC is considered to have undervoltage. BIAS circuits are used to provide constant current to comparators and other circuits. The logic circuit is used for realizing the undervoltage point voltage VUV and the undervoltage recovery point voltage VRE to generate a delta V (hysteresis voltage). And transmits the detected brown-out signal to the logic control circuit 140 for processing.
More preferably, fig. 5 is a schematic circuit block diagram of an overvoltage detection circuit according to an embodiment of the present invention, as shown in fig. 5, the overvoltage detection circuit 120 includes a second bias circuit, a second comparator, and a second logic circuit, a power supply terminal is electrically connected to the second logic circuit through the second bias circuit and the second comparator in sequence, and an output terminal of the second logic circuit is electrically connected to an input terminal of the logic control circuit 140 and an input terminal of the overvoltage timer circuit 130, respectively.
The overvoltage detection circuit 120 provided by the embodiment of the invention is composed of a comparator, a BIAS circuit and a logic circuit, wherein the comparator is used for comparing the voltage obtained by dividing the VCC voltage resistance with the set voltage, and when the divided voltage is higher than the set voltage, the VCC is considered to generate overvoltage, and the output 1 outputs an overvoltage protection signal. BIAS circuits are used to provide constant current to comparators and other circuits. The logic circuit is used for sending a timing signal to the timing circuit, the timing circuit starts timing, the timing signal is received after the timing is finished, and the logic circuit receives a second overvoltage detection signal of the comparator. If the overvoltage disappears, the surge is released, and the VCC voltage is recovered to be normal. If an overpressure condition is present, indicating that a latch-up is likely, output 2 will output an overlength overpressure signal, and a latch-up is likely.
More preferably, fig. 6 is a schematic circuit block diagram of an overvoltage timing circuit 130 according to an embodiment of the present invention, as shown in fig. 6, the overvoltage timing circuit 130 includes an input logic circuit, an RC delay circuit, a third comparator, and an output logic circuit electrically connected in sequence, where an output end of the second logic circuit is electrically connected to the input logic circuit, and the output logic circuit is electrically connected to an input end of the logic control circuit 140.
The overvoltage timer circuit 130 provided in the embodiment of the present invention is composed of an RC delay circuit, and generally the RC constant is set to 10-20 ms, i.e. Δt is 10-20 ms. When the charging start signal is detected, the input logic circuit starts to charge the RC delay circuit, the time from 0V to V3 comparison voltage is delta t, when the capacitance voltage rises to be higher than the V3 voltage, the comparator CMP outputs a high level, and after the output logic circuit processes, a timing end signal is output; and transmits the timing end signal to the logic control circuit 140 for comprehensive judgment.
More preferably, fig. 7 is a logic schematic diagram of a logic control circuit 140 according to an embodiment of the present invention, as shown in fig. 7, where the logic control circuit 140 includes a first not gate module, a second not gate module, a third not gate module, a fourth not gate module, a first not gate module and a second not gate module; the output end of the overvoltage detection circuit 120 is electrically connected with the input end of the first nand gate module, and the output end of the overvoltage timer circuit 130 is electrically connected with the input end of the first nand gate module through the first nand gate module; the under-voltage detection module is electrically connected with the input end of the second NAND gate module through the second NAND gate module, the output end of the first NAND gate module is electrically connected with the input end of the second NAND gate module through the third NAND gate module, the output end of the second NAND gate module is electrically connected with the F0 end through the fourth NAND gate module, and the output end of the second NAND gate module is electrically connected with the corresponding EN-end, H end and L end.
The logic control circuit 140 of the embodiment of the present invention implements the following logic functions: in an under-voltage state or an over-voltage state, but the timing is not finished, and outputting a signal ①; in an overpressure state and still in an overpressure state after timing is finished, and outputting a signal ②; EN-outputs a signal to turn off the HVIC when it outputs ①; FO will output a signal to let HVIC report fault; h and L both output protection signals to turn off the high side and low side drives; but G1 will not open at this time. When the signal ② is output, G1 will not become low level, and the MOS tube under VCC is closed; a more efficient circuit protection is achieved. The invention can solve the problem that the IPM or HVIC fails because the VCC power supply surge is too large, the VCC current can not be normally closed, the latch phenomenon occurs, the damage is caused to the internal low-power device, and the IPM or HVIC is invalid.
The specific design scheme is as follows: when the design of the belt pressing protection circuit 100 is carried out, MATLAB is adopted for logic simulation; the undervoltage detection circuit 110, the overvoltage detection circuit 120, the overvoltage timer circuit 130, and the logic control circuit 140 are designed, the circuit design is performed by using CADENCE, and the specific circuit function simulation is performed by using SPECTRE. After the circuit function simulation is completed, the voltage strip protection circuit 100 may be integrated into the HVIC to perform the circuit function simulation of the complete circuit of the HVIC. The voltage band protection circuit 100 is designed, and the VIRTUOSO of CADENCE is adopted for layout design and MMSIM is adopted for DRC and LVS error checking. The voltage strip protection circuit 100 layout is integrated into an HVIC layout, wherein VCC is connected to VCC lines of the HVIC layout; the enabling signal is connected to an enabling signal line of the HVIC layout; the G1 line is connected to the grid electrode of the VCC pull-down MOS tube; the FO line is connected to the signal line of the FAULT circuit; h and L are connected to logic gates of the high-side and low-side signals, respectively.
The switching tube 40 in the high-voltage integrated circuit is in a normally open state, and the zener diode can normally release surge voltage when the switching tube 40 is conducted. However, when the latch-up occurs, the switching tube 40 is turned off, and when the switching tube 40 is turned off, the withstand voltage of the switching tube 40 plus the withstand voltage of the zener diode is higher than 50V, so that almost all surge voltages can be blocked; and the corresponding overvoltage protection and undervoltage protection functions are set by combining the voltage strip protection circuit 100, so that the stability of the high-voltage integrated circuit is improved, and the use stability of the intelligent power chip is further improved.
Example two
Fig. 8 is a schematic diagram of a package structure of an intelligent power chip 300 according to an embodiment of the present invention, and as shown in fig. 8, the present invention further discloses a semiconductor circuit, which includes a module frame, a high-voltage integrated chip and a transistor, where the high-voltage integrated chip includes a high-voltage integrated circuit according to any one of the first embodiment of the present invention, the high-voltage integrated chip includes an input pin and an output pin, the module frame is provided with an input connection point and an output connection point, the high-voltage integrated chip and the transistor are both disposed at the module frame, the output pins of the high-voltage integrated chip are all connected with the output connection point at the module frame through corresponding transistors, and the input pin of the high-voltage integrated chip is connected with the input connection point at the module frame.
Specifically, the IPM drives 6 paths of IGBTs or MOS transistors by a 6-channel HVIC, a voltage-band protection circuit is integrated in the 6-channel HVIC, and the voltage-band protection circuit is a protection circuit in the HVIC, and does not cause any influence on ports of the HVIC. That is, the IPM may follow the existing circuit structure design and the corresponding chip packaging structure, and the various connection ports are not changed, which mainly packages the high-voltage integrated circuit in the first embodiment into the intelligent power chip and achieves better functional effects, and the adopted 6-channel driving mode is consistent with the driving mode of the existing intelligent power chip.
More preferably, fig. 9 is a schematic diagram of a substrate architecture of an intelligent power chip according to an embodiment of the present invention, where the substrate architecture of the intelligent power chip adopts any one of an IMS substrate architecture, a DBC substrate architecture, and a CIS substrate architecture.
In the embodiment of the invention, the traditional IMS, DBC and CIS IPM packaging schemes are adopted to package the intelligent power chip; the IPM may be an IMS substrate, a DBC substrate, a CIS substrate, etc., and FIG. 9A is a cross-sectional view of an IMS substrate; fig. 9B is a cross-sectional view of the DBC substrate structure IPM, and fig. 9C is a cross-sectional view of the CIS substrate structure IPM.
The embodiment of the invention can solve the problems that the VCC current cannot be normally closed due to overlarge surge of the VCC power supply, the latch phenomenon occurs, the damage is caused to the internal low-power device, and the IPM is invalid.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (6)
1. A high voltage integrated circuit, comprising:
the output end of the high-voltage output drive is connected with the output pin of the corresponding chip; a switching tube is further arranged between the bootstrap circuit and the power supply end, the switching tube is configured to be in a normally open state, and when the latch effect of the circuit is detected, the switching tube is switched to be in a closed state;
The device comprises a filtering conversion circuit, a dead zone interlocking circuit and an input circuit which are electrically connected in sequence, wherein the input circuit is electrically connected with one end of a pulse circuit and one end of a delay circuit respectively, a power end is electrically connected with an input end of a voltage strip protection circuit, a first output end of the voltage strip protection circuit is electrically connected with one end of the pulse circuit, the other end of the pulse circuit is electrically connected with a high-voltage output drive through a high-voltage conversion circuit, a second output end of the voltage strip protection circuit and the other end of the delay circuit are both connected with corresponding chip output pins through a low-voltage conversion circuit, and the voltage strip protection circuit is provided with a switch port and a grid electrode of a switch tube;
The voltage band protection circuit comprises an undervoltage detection circuit, an overvoltage timing circuit and a logic control circuit; the overvoltage detection circuit is electrically connected with the overvoltage timing circuit, the power supply end is electrically connected with the input end of the logic control circuit through the undervoltage detection circuit, the overvoltage detection circuit and the overvoltage timing circuit respectively, and the output end of the logic control circuit comprises a first output end and a second output end;
The undervoltage detection circuit comprises a first bias circuit, a first comparator and a first logic circuit, wherein a power end is electrically connected with the first logic circuit through the first bias circuit and the first comparator in sequence, and an output end of the first logic circuit is electrically connected with an input end of the logic control circuit;
The overvoltage detection circuit comprises a second bias circuit, a second comparator and a second logic circuit, wherein the power end is electrically connected with the second logic circuit through the second bias circuit and the second comparator in sequence, and the output end of the second logic circuit is electrically connected with the input end of the logic control circuit and the input end of the overvoltage timing circuit respectively;
the overvoltage timing circuit comprises an input logic circuit, an RC delay circuit, a third comparator and an output logic circuit which are electrically connected in sequence, wherein the output end of the second logic circuit is electrically connected with the input logic circuit, and the output logic circuit is electrically connected with the input end of the logic control circuit.
2. The high voltage integrated circuit of claim 1, wherein the RC delay circuit is configured to any one of 10-20 ms.
3. The high voltage integrated circuit of claim 1, wherein the logic control circuit comprises a first NOT module, a second NOT module, a third NOT module, a fourth NOT module, a first NOT module, and a second NOT module; the output end of the overvoltage detection circuit is electrically connected with the input end of the first NAND gate module, and the output end of the overvoltage timing circuit is electrically connected with the input end of the first NAND gate module through the first NAND gate module; the under-voltage detection circuit is electrically connected with the input end of the second NAND gate module through the second NAND gate module, the output end of the first NAND gate module is electrically connected with the input end of the second NAND gate module through the third NAND gate module, the output end of the second NAND gate module is electrically connected with the F0 end through the fourth NAND gate module, and the output end of the second NAND gate module is electrically connected with the corresponding EN-end, H end and L end.
4. The high voltage integrated circuit of claim 1, wherein the switching tube is a field effect tube.
5. A semiconductor circuit, comprising a module frame, a high voltage integrated chip and a transistor, wherein the high voltage integrated chip comprises the high voltage integrated circuit as claimed in any one of claims 1-4, the high voltage integrated chip comprises an input pin and an output pin, the module frame is provided with an input connection point and an output connection point, the high voltage integrated chip and the transistor are both arranged at the module frame, the output pin of the high voltage integrated chip is connected with the output connection point at the module frame through the corresponding transistor, and the input pin of the high voltage integrated chip is connected with the input connection point at the module frame.
6. The semiconductor circuit of claim 5, wherein the substrate architecture of the high voltage integrated chip employs any one of an IMS substrate architecture, a DBC substrate architecture, and a CIS substrate architecture.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106507531A (en) * | 2016-09-23 | 2017-03-15 | 厦门矿通科技有限公司 | A kind of LED illumination power drives chip and drive circuit |
| CN110690692A (en) * | 2019-11-25 | 2020-01-14 | 广东美的制冷设备有限公司 | High-voltage integrated chip, intelligent power module and air conditioner |
| CN111463755A (en) * | 2020-03-30 | 2020-07-28 | 海信（山东）空调有限公司 | PFC overvoltage protection circuit and PFC circuit |
| CN212811583U (en) * | 2020-07-31 | 2021-03-26 | 广东汇芯半导体有限公司 | Intelligent power module of integrated switching power supply |
| CN214473596U (en) * | 2021-01-14 | 2021-10-22 | 深圳和而泰智能控制股份有限公司 | Voltage over-voltage and under-voltage detection circuit |
| CN217087498U (en) * | 2021-10-27 | 2022-07-29 | 广东汇芯半导体有限公司 | High-voltage integrated circuit and semiconductor circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102007006319B4 (en) * | 2007-02-08 | 2012-12-13 | Semikron Elektronik Gmbh & Co. Kg | Control circuit with TOP level shifter for transmitting an input signal and associated method |
| JP5360002B2 (en) * | 2010-06-28 | 2013-12-04 | 富士電機株式会社 | Semiconductor device driving apparatus |
-
2021
- 2021-10-27 CN CN202111252744.9A patent/CN114006520B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106507531A (en) * | 2016-09-23 | 2017-03-15 | 厦门矿通科技有限公司 | A kind of LED illumination power drives chip and drive circuit |
| CN110690692A (en) * | 2019-11-25 | 2020-01-14 | 广东美的制冷设备有限公司 | High-voltage integrated chip, intelligent power module and air conditioner |
| CN111463755A (en) * | 2020-03-30 | 2020-07-28 | 海信（山东）空调有限公司 | PFC overvoltage protection circuit and PFC circuit |
| CN212811583U (en) * | 2020-07-31 | 2021-03-26 | 广东汇芯半导体有限公司 | Intelligent power module of integrated switching power supply |
| CN214473596U (en) * | 2021-01-14 | 2021-10-22 | 深圳和而泰智能控制股份有限公司 | Voltage over-voltage and under-voltage detection circuit |
| CN217087498U (en) * | 2021-10-27 | 2022-07-29 | 广东汇芯半导体有限公司 | High-voltage integrated circuit and semiconductor circuit |
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