CN114002715A

CN114002715A - Miniaturized big dipper third generation double-frequency point down conversion integrated circuit board

Info

Publication number: CN114002715A
Application number: CN202110219909.6A
Authority: CN
Inventors: 燕官锋; 何赛男; 边立娴; 史剑锋; 杨帅; 邓亚男; 李柳军; 郭潇潇
Original assignee: HEBEI JINGHE ELECTRONIC TECHNOLOGY CO LTD
Current assignee: HEBEI JINGHE ELECTRONIC TECHNOLOGY CO LTD
Priority date: 2021-02-26
Filing date: 2021-02-26
Publication date: 2022-02-01

Abstract

The invention discloses a miniaturized Beidou third-generation double-frequency point down-conversion board card which comprises a double-frequency point down-conversion module, wherein the double-frequency point down-conversion module is arranged between a low-noise amplifier and a complete machine mainboard of a receiver, and comprises a feed circuit, an amplifying circuit, a power dividing circuit, a B3 filter circuit, a B1c filter circuit, a frequency conversion processing circuit and a power supply conversion circuit.

Description

Miniaturized big dipper third generation double-frequency point down conversion integrated circuit board

Technical Field

The invention relates to the field of Beidou satellite navigation systems, in particular to a miniaturized Beidou third-generation double-frequency-point down-conversion board card.

Background

Beidou satellite navigation system: the English language is called BeiDou Navigation satellite System, also called BDS. Is a global satellite system developed by China. The Beidou satellite navigation system consists of a space section, a ground section and a user section, can provide high-precision, high-reliability positioning, navigation and time service for various users all day long in the global range, has short message communication capacity, and initially has regional navigation, positioning and time service capacities, wherein the positioning precision is 10 meters, the speed measurement precision is 0.2m/s, and the time service precision is 10 ns.

The Beidou third generation satellite navigation system: in 2017, 11 and 5 months, the third generation navigation satellite in China smoothly ascends to the air, which marks that China formally starts to build a Beidou global satellite navigation system.

At present, the research and development of user receivers and other equipment at a user end of a Beidou third-generation global satellite navigation system are in a exploration stage, and medium-frequency points, sampling clocks, sampling modes and the like are urgently needed to be optimized through engineering exploration. The present invention provides a dual frequency point receiving module to solve this problem.

Disclosure of Invention

The invention provides a miniaturized Beidou third-generation double-frequency-point down-conversion board card which helps a complete machine system of a Beidou third-generation global satellite navigation positioning user receiver to realize information resolving such as quantization, coding, positioning, speed measurement and the like.

In order to solve the technical problems, the technical scheme adopted by the invention is as follows: a miniaturized Beidou third-generation double-frequency point down-conversion board card comprises a double-frequency point down-conversion module, wherein the double-frequency point down-conversion module is arranged between a low-noise amplifier and a complete machine mainboard of a receiver, the double-frequency point down-conversion module is arranged on the complete machine mainboard of the receiver in a manner of adopting semicircular stamp holes and fixedly arranged on the complete machine mainboard of the receiver, the semicircular stamp holes are 54 and are respectively numbered from pin 1 to pin 54, the pin 25 is a radio frequency input port, the radio frequency input port is used for respectively receiving a B1c frequency point satellite navigation signal and a B3 frequency point satellite navigation signal which are processed by space navigation signal electromagnetic waves through active antenna low-noise amplification and filtering and transmitting the signals to an amplifying circuit, the amplifying circuit synchronously amplifies the B1c frequency point satellite navigation signal and the B3 frequency point satellite navigation signal and transmits the signals to a power dividing circuit, the power dividing circuit transmits the B1c frequency point satellite navigation signal and the B3 frequency point satellite navigation signal to a B3 filtering circuit and a B1c filtering circuit respectively, the output ends of the B3 filter circuit and the B1c filter circuit are connected to a frequency conversion processing circuit, the frequency conversion processing circuit respectively and correspondingly down-converts the radio frequency of the B1c frequency point and the radio frequency of the B3 frequency point to the corresponding intermediate frequency of the B1c frequency point and the intermediate frequency of the B3 frequency point, thereby realizing the moving of frequency spectrum, the frequency conversion processing circuit converts the intermediate frequency of the frequency point B1c and the intermediate frequency of the frequency point B3 into digital intermediate frequency signals to be output, 10MHz reference signals are input into the frequency conversion processing circuit, the frequency conversion processing circuit outputs 80MHz sampling clock signals, one end of a feed circuit is connected with a direct current power VCC-5V input end, the other end outputs direct current to feed a low noise amplifier at the front end of the module, the input end of the direct current power VCC-5V is also connected with a power conversion circuit, the power supply conversion circuit converts a direct current power supply VCC-5V into a direct current power supply VCC-3.3V for output and respectively provides the output to the amplifying circuit and the frequency conversion processing circuit.

The technical scheme of the invention is further improved as follows: the feed circuit unit comprises a restorable fuse R1, a choke coil inductor L1, a power supply filter capacitor C1 and a power supply filter capacitor C2, wherein the input end of a direct current power supply VCC-5V enters the first end connected with the restorable fuse R1 through the 28 th pin and the 29 th pin of a semicircular stamp hole, the second end of the restorable fuse R1 is respectively connected with the first end, connected with the power supply filter capacitor C1 and the power supply filter capacitor C2 in parallel, of the restorable fuse R1, the second end, connected with the power supply filter capacitor C1 and the power supply filter capacitor C2 in parallel, of the restorable fuse R1 is grounded, and the second end of the choke coil inductor L1 outputs direct current through the 25 th pin of the semicircular stamp hole to feed the low noise amplifier at the front end of the module.

The technical scheme of the invention is further improved as follows: the amplifying circuit comprises a monolithic amplifier U3, a low noise amplifier at the front end of the module processes a radio frequency navigation signal RF-IN and inputs the radio frequency navigation signal RF-IN into the module through a 25 th pin of a semicircular stamp hole and is connected with a first end of a coupling capacitor C6, a second end of the coupling capacitor C6 is respectively connected with a first end of a resistor R9, a resistor R3 and a first end of a resistor R5, a second end of the resistor R9 is grounded, the resistor R3, a resistor R5 and a resistor R4 form a pi-type impedance matching network, a second end of a resistor R5 is respectively connected with a first end of a resistor R4 and a first end of a coupling capacitor C7, a second end of a resistor R3 and a second end of a resistor R4 are respectively grounded, a second end of the coupling capacitor C7 is connected with a pin 4 of a monolithic amplifier U3, a pin 0, a pin 2, a pin 3, a pin 5, a pin 6, a pin 7 and a pin 398 of the monolithic amplifier U4642 are respectively connected with a first end of an inductor L and a first end of a coupling capacitor C8, the second end of the inductor L2 is respectively connected with the first ends of an inductor C3, an inductor C4 and a resistor R2, the second ends of the inductor C3 and the inductor C4 are respectively grounded, the second end of the resistor R2 is connected with a direct current power supply VCC-3.3V, the second end of the coupling capacitor C8 is respectively connected with the first ends of a resistor R10, a resistor R7 and a resistor R6, the second end of the resistor R6 is connected with the first end of the resistor R8 and RF-IN-1, and the second ends of the resistor R10, the resistor R7 and the resistor R8 are respectively grounded.

The technical scheme of the invention is further improved as follows: the power dividing circuit comprises a power divider U2, wherein an RF-IN-1 is connected with a pin 2 of a power divider U2, the pin 1, the pin 3, the pin 4, the pin 5, the pin 6, the pin 8, the pin 10, the pin 11 and the pin 12 of the power divider U2 are respectively grounded, the pin 9 of the power divider U2 is connected with a first end of a capacitor C5, a second end of the capacitor C5 is RF-B3-OUT, the pin 7 of the power divider U2 is connected with a first end of the capacitor C10, and a second end of the capacitor C10 is RF-B1C-OUT.

The technical scheme of the invention is further improved as follows: the B3 filter circuit comprises a frequency point filter U8, wherein an RF-B3-OUT is respectively connected with a first end of a resistor R26 and a first end of a resistor R29, a second end of the resistor R26 is respectively connected with a first end of a resistor R30 and a pin 2 of a frequency point filter U8, a second end of the resistor R29 and a second end of a resistor R30 are respectively grounded, a pin 1, a pin 3, a pin 4 and a pin 6 of the frequency point filter U8 are respectively grounded, a pin 5 of the B3 frequency point filter U8 is respectively connected with a first end of a resistor R27 and a first end of a resistor R31, a second end of the resistor R27 is respectively connected with a first end of a resistor R32 and a first end of a capacitor C37, a second end of the resistor R31 and a second end of a resistor R32 are respectively grounded, and a second end of the capacitor C37 is an RF-B3-OUT 1.

The technical scheme of the invention is further improved as follows: the B1C filter circuit comprises a dielectric filter U10, wherein an RF-B1C-OUT is respectively connected with a first end of a resistor R42 and a first end of a resistor R44, a second end of the resistor R42 is respectively connected with a first end of a resistor R45 and a pin 1 of a frequency point filter U8, a second end of the resistor R44 and a second end of a resistor R45 are respectively grounded, a pin 3, a pin 4, a pin 5, a pin 6 and a pin 7 of the frequency point filter U10 are respectively grounded, a pin 2 of the frequency point filter U10 is respectively connected with a first end of the resistor R43 and a first end of a resistor R46, a second end of the resistor R43 is respectively connected with a first end of a resistor R47 and a first end of a capacitor C43, a second end of the resistor R46 and a second end of a resistor R47 are respectively grounded, and a second end of the capacitor C43 is an RF-B1C-OUT 1.

The technical scheme of the invention is further improved as follows: the power conversion circuit comprises a power chip U4, an external direct current power VCC-5V of the double-frequency point down-conversion module is respectively connected with the first end of a capacitor C12, the first end of a capacitor C13, a pin 1 and a pin 7 of a power chip U4 after entering through a pin 28 and a pin 29 of a semicircular stamp hole, the pin 0, the pin 4 and the pin 6 of the power chip U4 are respectively grounded, the pin 8 of the power chip U4 is connected with the first end of the resistor R11, the first end of the resistor R12 and the capacitor C11 which are connected in parallel is respectively connected with the pin 2 of the power chip U4 and the second end of the resistor R11, the second end ground after resistance R12 and electric capacity C11 connect in parallel, power chip U4's pin 3 and pin 5 are the chip output pin and connect power filter electric capacity C14's first end and DC power supply VCC-3.3V respectively, power filter electric capacity C14's second end ground.

The technical scheme of the invention is further improved as follows: the frequency conversion processing circuit comprises an integrated circuit U7, an RF-B3-OUT1 is connected with a first end of an inductor L7, a second end of the inductor L7 is connected with a pin 9 of an integrated circuit U7 after being connected with a capacitor C36, an RF-B1C-OUT1 is connected with a pin 15 of an integrated circuit U7 after being connected with a capacitor C44 and an inductor L10 in sequence, a pin 2 of the integrated circuit U7 is connected with first ends of a resistor R22 and a resistor R23 respectively, a second end of the resistor R23 is grounded, a second end of the resistor R22 is connected with a power supply VCC-3.3V-2202, a pin 5 of the integrated circuit U7 is connected with a power supply VCC-3.3V-2202 and a grounded power supply filter capacitor C29 respectively, a pin 6 of the integrated circuit U7 is connected with first ends of a resistor R24 and a capacitor C32 respectively, a second end of the resistor R32 is connected with a first end of a capacitor C32, pin 7 of the integrated circuit U7 is connected to VCC-3.3V-2202 and a grounded power supply filter capacitor C34 respectively, pin 8 of the integrated circuit U7 is connected to a resistor R25 and then grounded, pin 11 of the integrated circuit U7 is connected to VCC-3.3V-2202 and a grounded power supply filter capacitor C40 respectively, pin 12 of the integrated circuit U7 is connected to a resistor R33 and then grounded, pin 13 of the integrated circuit U7 is connected to VCC-3.3V-2202 and a grounded power supply filter capacitor C42 respectively, pin 17 of the integrated circuit U7 is connected to resistor R48 and then to VCC-3.3V-2202, pin 18 of the integrated circuit U7 is connected to VCC-3.3V-2202 and a grounded power supply filter capacitor C48 respectively, pin 19 of the integrated circuit U7 is connected to resistor R53 and a first end of a capacitor C45 respectively, a second end of the resistor R53 is connected to a second end of the capacitor C54, the second end of the capacitor C45 is connected with the second end of the capacitor C54 and then grounded, the pin 20 of the integrated circuit U7 is connected with the capacitor C49 and then grounded, the pin 22 and the pin 23 of the integrated circuit U7 are respectively connected with the power VCC-3.3V-2202 and the grounded power filter capacitor C50, the pin 26 of the integrated circuit U7 is respectively connected with the power VCC-3.3V-2202 and the grounded power filter capacitor C46, the pin 27 of the integrated circuit U7 is connected with the capacitor C47 and then grounded, the pin 29 of the integrated circuit U7 is connected with the resistor R49 and then connected with the B1C frequency point output intermediate frequency output IF-B1C-D3 and output through the pin 44 of the semicircular stamp hole, the pin 30 of the integrated circuit U7 is connected with the resistor R50 and then connected with the B1C output intermediate frequency output-B1C-D2 and output through the pin 45 of the semicircular stamp hole, the pin 31B 31 of the integrated circuit U2 is connected with the pin R56 and then connected with the intermediate frequency output IF output frequency point IF C-IF output-IF C and 8653 D1 is output through a pin 46 of a semicircular stamp hole, a pin 32 of an integrated circuit U7 is connected with a resistor R52 and then connected with a B1c frequency point output intermediate frequency output IF-B1c-D0 and output through a pin 47 of the semicircular stamp hole, a pin 35 of the integrated circuit U7 is connected with a resistor R39 and then connected with a B3 frequency point output intermediate frequency output IF-B3-D3 and output through a pin 39 of the semicircular stamp hole, a pin 36 of the integrated circuit U7 is connected with a resistor R37 and then connected with a B3 frequency point output intermediate frequency output IF-B3-D2 and output through a pin 40 of the semicircular stamp hole, a pin 37 of the integrated circuit U7 is connected with a resistor R36 and then connected with a B3 frequency point output IF-B3-D1 and output through a pin 41 of the semicircular stamp hole, a pin 38 of the integrated circuit U7 is connected with a resistor R7 and then connected with an intermediate frequency output IF-B7 and output through the semicircular stamp hole 7 and output pin 42, pin 47 of the integrated circuit U7 is connected to VCC-3.3V-2202 and a grounded power supply filter capacitor C35 respectively, pin 48 of the integrated circuit U7 is connected to a capacitor C33 and then connected to a B1C frequency point analog-to-digital signal output terminal IF-B1C-a, pin 51 of the integrated circuit U7 is connected to a capacitor C31 and then connected to a B3 frequency point analog-to-digital signal output terminal IF-B3-a, pin 54 of the integrated circuit U7 is connected to a power supply-3.3V-2202 and a grounded power supply filter capacitor C24 respectively, pin 55 of the integrated circuit U7 is connected to a capacitor C23 and then grounded, pin 59 of the integrated circuit U7 is connected to VCC-3V-VCC and a grounded power supply filter capacitor C22 respectively, pin 60 of the integrated circuit U7 is connected to a resistor R21 and then connected to an SPI control point SPI-CS, pin 61 of the integrated circuit U7 is connected to a resistor R20 and then to an SPI-CS, pin 62 of the integrated circuit U7 is connected with resistor R19 and then connected with SPI control point SPI-MOSI, pin 63 of the integrated circuit U7 is connected with resistor R18 and then connected with SPI control point SPI-MISO, pin 64 of the integrated circuit U7 is connected with capacitor C27 and then connected with 10MHz reference signal input port 10MHZ-IC-IN, pin 65 of the integrated circuit U7 is respectively connected with power VCC-3.3V-2202 and grounded power filter capacitor C26, pin 67 of the integrated circuit U7 is respectively connected with power VCC-3.3V-2202 and grounded power filter capacitor C25, and pin 69 of the integrated circuit U7 is grounded;

the frequency conversion processing circuit further comprises a dual-frequency point down-conversion module, wherein a direct-current power supply VCC-3.3V inside the dual-frequency point down-conversion module is respectively connected with first ends of a magnetic bead L13, a capacitor C55 and a capacitor C56, a second end of the magnetic bead L13 is connected with a power supply VCC-3.3V-2202 of an integrated circuit U7, and second ends of the capacitor C55 and a capacitor C56 are respectively grounded;

the frequency conversion processing circuit further comprises an integrated circuit U7, a reference signal 10MHZ-IN is connected with a resistor R13 and then is respectively connected with a first end of an inductor L13 and a first end of a capacitor C15, a second end of the inductor L13 is respectively connected with a first end of an inductor L14 and a first end of a capacitor C16, a second end of the inductor L14 is respectively connected with a first end of a capacitor C17 and a 10MHZ-IC-IN, and the capacitor C15, the capacitor C16 and the capacitor C17 are respectively grounded;

the frequency conversion processing circuit also comprises a NOT gate chip U5, a 80MHZ sampling clock signal is sequentially connected with a capacitor C20 and a resistor R15 and then respectively connected with a first end of a resistor R17, a first end of the resistor R14 and a pin 1 and a pin 2 of a NOT gate chip U5, the pin 3 of the NOT gate chip U5 is connected with the second end of the resistor R17 and then grounded, the second end of the resistor R14 is respectively connected with the pin 5 of the NOT gate chip U5, the first end of the capacitor C18, the first end of the capacitor C19 and the first end of the inductor L5, the second end of the capacitor C18 and the second end of the capacitor C19 are grounded respectively, the second end of the inductor L5 is connected with a direct current power supply VCC-3.3V, a pin 4 of the NOT gate chip U5 is sequentially connected with a capacitor C21 and a resistor R6 and then outputs 80MHZ-CLK-OUT, and the output is output to a later-stage baseband circuit through a 37 th pin of the semicircular stamp hole to provide an 80MHz sampling clock signal for the baseband circuit;

the frequency conversion processing circuit further comprises an operational amplifier U9, wherein a B1C frequency point analog intermediate frequency signal IF-B1C-OUT is output through a 6 th pin of a semicircular stamp hole and is respectively connected with a first end of a capacitor C38 and a first end of an inductor L8, a second end of the capacitor C38 is grounded, a second end of the inductor L8 is sequentially connected with a resistor R28 and the capacitor C41 and then is connected with a pin 1 of an operational amplifier U9, a pin 2 and a pin 4 of the operational amplifier U9 are grounded, a pin 5 of the operational amplifier U9 is respectively connected with a first end of the resistor R38, a first end of the inductor L9 and a first end of the capacitor C39, a second end of the capacitor C39 is grounded, a second end of the inductor L9 is connected with a direct current power supply VCC-3.3V, a B1C analog intermediate frequency point signal IF-B1C-A of an integrated circuit U7 is respectively connected with a first end of the resistor R40 and a first end of the resistor R34, and a second end of the resistor R40 is grounded, the pin 3 of the operational amplifier U9 is respectively connected with the second end of the resistor R34, the second end of the resistor R38 and the first end of the resistor R41, and the second end of the resistor R41 is grounded;

the frequency conversion processing circuit further comprises an operational amplifier U11, wherein a B3 frequency point analog intermediate frequency signal IF-B3-OUT is output through a 11 th pin of a semicircular stamp hole and is respectively connected with a first end of a capacitor C51 and a first end of an inductor L11, a second end of the capacitor C51 is grounded, a second end of an inductor L11 is sequentially connected with a resistor R54 and the capacitor C53 and then is connected with a pin 1 of an operational amplifier U11, a pin 2 and a pin 4 of the operational amplifier U11 are grounded, a pin 5 of the operational amplifier U11 is respectively connected with a first end of a resistor R56, a first end of an inductor L12 and a first end of a capacitor C52, a second end of the capacitor C52 is grounded, a second end of the inductor L12 is connected with a direct current power supply VCC-3.3V, a B3 analog intermediate frequency signal IF-B3-A of an integrated circuit U7 is respectively connected with a first end of a resistor R57 and a first end of a resistor R55, and a second end of the resistor R57 is grounded, the pin 3 of the operational amplifier U11 is respectively connected with the second end of the resistor R55, the second end of the resistor R56 and the first end of the resistor R58, and the second end of the resistor R58 is grounded.

The technical scheme of the invention is further improved as follows: the frequency point of the B3 frequency point satellite navigation signal is 1268.52 +/-10.23 MHz, the intermediate frequency point output from the 39 th pin to the 42 th pin is 15.48 +/-10.23 MHz, and the local oscillation frequency point is 1284 MHz; the frequency point of the B1c frequency point satellite navigation signal is 1575.42 +/-16.368 MHz, the intermediate frequency point output from the 44 th pin to the 47 th pin is 20.58 +/-16.368 MHz, and the local oscillation frequency point is 1596 MHz.

Due to the adoption of the technical scheme, the invention has the technical progress that:

1. according to the Beidou third-generation global satellite navigation system, the two frequency points B3 and B1c are down-converted to the intermediate frequency band communication signal, a band-pass sampling mode is adopted, the conversion from analog to digital is realized, and the band-pass sampling mode has obvious advantages, such as reduction of sampling frequency, improvement of sampling rate, effective suppression of intermediate frequency harmonic waves and the like;

2. according to the invention, B3 in the Beidou third-grade global satellite navigation system receives a radio frequency point 1268.52 +/-10.23 MHz, and the frequency is down converted to 15.48 +/-10.23 MHz. Receiving a radio frequency point 1575.42 +/-16.368 MHz by B1c in a Beidou third-grade global satellite navigation system, performing down-conversion to 20.58 +/-16.368 MHz, and providing an 80MHz sampling clock for a digital baseband processing system;

3. the double-frequency-point down-conversion module has small size, the whole size is 57mm multiplied by 23mm multiplied by 10mm, a surface mounting structure is adopted, and semicircular stamp holes are welded, so that the whole machine miniaturization design and the integration design of a user receiver are facilitated;

4. the invention can feed for the active antenna, which is beneficial to realizing the optimization of the integration level of the whole communication link;

5. the module of the invention has low power consumption, and is convenient for the complete machine of the user receiver to realize low power consumption design.

Drawings

FIG. 1 is a schematic block diagram of a dual frequency point down conversion module circuit of the present invention;

FIG. 2 is a diagram of the dual frequency point down conversion module of the present invention;

FIG. 3 is a schematic block diagram of a dual frequency point down conversion module feed circuit of the present invention;

FIG. 4 is a schematic diagram of a dual frequency point down conversion module amplification circuit of the present invention;

FIG. 5 is a schematic block diagram of a power dividing circuit of the dual-band point down conversion module according to the present invention;

FIG. 6 is a schematic diagram of a filtering circuit of the dual frequency point down conversion module B3 according to the present invention;

FIG. 7 is a schematic diagram of the filtering circuit of the dual frequency down-conversion module B1c of the present invention;

FIG. 8 is a schematic diagram of a dual frequency point down conversion module power conversion circuit of the present invention;

fig. 9 is a schematic diagram of a frequency conversion processing circuit of the dual-frequency-point down conversion module according to the present invention.

Detailed Description

The present invention will be described in further detail with reference to the following examples:

the utility model provides a miniaturized big dipper third generation double frequency point down conversion integrated circuit board, includes the double frequency point down conversion module, the double frequency point down conversion module sets up between the complete machine mainboard of low noise amplifier and receiver, and the double frequency point down conversion module adopts semi-circular stamp hole setting and fixed the setting on the complete machine mainboard of receiver, 54 semi-circular stamp holes altogether, serial number is pin 1 ~ 54 pin respectively, and wherein the interface definition of each pin is as follows:

during welding, attention needs to be paid to ensure that the module grounding pin can be grounded in a large area as much as possible, the radio frequency input port is prevented from being short-circuited to the ground, and the electrostatic protection is paid attention to.

The 25 th pin is a radio frequency input port, as shown in fig. 2: the radio frequency input port receives a B1c frequency point satellite navigation signal and a B3 frequency point satellite navigation signal which are processed by low-noise amplification and filtering of space navigation signal electromagnetic waves through an active antenna respectively and transmits the signals to an amplifying circuit, the frequency point of the B3 frequency point satellite navigation signal is 1268.52 +/-10.23 MHz, the intermediate frequency point output from a 39 th pin to a 42 th pin is 15.48 +/-10.23 MHz, and the local oscillation frequency point is 1284 MHz; the frequency point of the B1c frequency point satellite navigation signal is 1575.42 +/-16.368 MHz, the intermediate frequency point output from the 44 th pin to the 47 th pin is 20.58 +/-16.368 MHz, and the local oscillation frequency point is 1596 MHz. The input impedance and the output impedance of the double-frequency-point down-conversion module are both in 50 ohm standard, the noise coefficient of the whole variable frequency link is less than 15dB, and the AGC range is more than 35 dB.

The amplifying circuit synchronously amplifies navigation electromagnetic wave signals to transmit B1c frequency point satellite navigation signals and B3 frequency point satellite navigation signals to the power dividing circuit, the power dividing circuit respectively transmits the B1c frequency point satellite navigation signals and the B3 frequency point satellite navigation signals to the B3 filter circuit and the B1c filter circuit, the output ends of the B3 filter circuit and the B1c filter circuit are connected to the frequency conversion processing circuit, the frequency conversion processing circuit respectively down-converts the radio frequency of the B1c frequency point and the radio frequency of the B3 frequency point to the intermediate frequency of the corresponding B1c frequency point and the intermediate frequency of the B3 frequency point to realize the moving of frequency spectrum, the frequency conversion processing circuit converts the intermediate frequency of the B1c frequency point and the intermediate frequency of the B3 frequency point into digital intermediate frequency signals to be output, 10MHz reference signals are input to the frequency conversion processing circuit, the frequency processing circuit outputs 80MHz sampling clock signals, and one end of the feeder circuit is connected with a direct current power supply VCC-5V input end, The other end outputs direct current to feed a low-noise amplifier at the front end of the module, the input end of the direct current power supply VCC-5V is also connected with a power supply conversion circuit, and the power supply conversion circuit converts the direct current power supply VCC-5V into the direct current power supply VCC-3.3V to be output and respectively provided for an amplifying circuit and a frequency conversion processing circuit.

As shown in fig. 3: the feed circuit unit comprises a restorable fuse R1, a choke coil inductor L1, a power supply filter capacitor C1 and a power supply filter capacitor C2, wherein the input end of a direct current power supply VCC-5V enters the first end connected with the restorable fuse R1 through the 28 th pin and the 29 th pin of a semicircular stamp hole, the second end of the restorable fuse R1 is respectively connected with the first end, connected with the power supply filter capacitor C1 and the power supply filter capacitor C2 in parallel, of the restorable fuse R1, the second end, connected with the power supply filter capacitor C1 and the power supply filter capacitor C2 in parallel, of the restorable fuse R1 is grounded, and the second end of the choke coil inductor L1 outputs direct current through the 25 th pin of the semicircular stamp hole to feed the low noise amplifier at the front end of the module.

As shown in fig. 4: the amplifying circuit comprises a monolithic amplifier U3, a low noise amplifier at the front end of the module processes a radio frequency navigation signal RF-IN and inputs the radio frequency navigation signal RF-IN into the module through a 25 th pin of a semicircular stamp hole and is connected with a first end of a coupling capacitor C6, a second end of the coupling capacitor C6 is respectively connected with a first end of a resistor R9, a resistor R3 and a first end of a resistor R5, a second end of the resistor R9 is grounded, the resistor R3, a resistor R5 and a resistor R4 form a pi-type impedance matching network, a second end of a resistor R5 is respectively connected with a first end of a resistor R4 and a first end of a coupling capacitor C7, a second end of a resistor R3 and a second end of a resistor R4 are respectively grounded, a second end of the coupling capacitor C7 is connected with a pin 4 of a monolithic amplifier U3, a pin 0, a pin 2, a pin 3, a pin 5, a pin 6, a pin 7 and a pin 398 of the monolithic amplifier U4642 are respectively connected with a first end of an inductor L and a first end of a coupling capacitor C8, the second end of the inductor L2 is respectively connected with the first ends of an inductor C3, an inductor C4 and a resistor R2, the second ends of the inductor C3 and the inductor C4 are respectively grounded, the second end of the resistor R2 is connected with a direct current power supply VCC-3.3V, the second end of the coupling capacitor C8 is respectively connected with the first ends of a resistor R10, a resistor R7 and a resistor R6, the second end of the resistor R6 is connected with the first end of the resistor R8 and RF-IN-1, and the second ends of the resistor R10, the resistor R7 and the resistor R8 are respectively grounded.

As shown in fig. 5: the power dividing circuit comprises a power divider U2, wherein an RF-IN-1 is connected with a pin 2 of a power divider U2, the pin 1, the pin 3, the pin 4, the pin 5, the pin 6, the pin 8, the pin 10, the pin 11 and the pin 12 of the power divider U2 are respectively grounded, the pin 9 of the power divider U2 is connected with a first end of a capacitor C5, a second end of the capacitor C5 is RF-B3-OUT, the pin 7 of the power divider U2 is connected with a first end of the capacitor C10, and a second end of the capacitor C10 is RF-B1C-OUT.

As shown in fig. 6: the B3 filter circuit comprises a frequency point filter U8, wherein the RF-B3-OUT is respectively connected with a first end of a resistor R26 and a first end of a resistor R29, a second end of the resistor R26 is respectively connected with a first end of a resistor R30 and a pin 2 of a frequency point filter U8, a second end of the resistor R29 and a second end of a resistor R30 are respectively grounded, a pin 1, a pin 3, a pin 4 and a pin 6 of the B3 frequency point filter U8 are respectively grounded, a pin 5 of the frequency point filter U8 is respectively connected with a first end of a resistor R27 and a first end of a resistor R31, a second end of the resistor R27 is respectively connected with a first end of a resistor R32 and a first end of a capacitor C37, a second end of the resistor R31 and a second end of a resistor R32 are respectively grounded, and a second end of the capacitor C37 is RF-B3-OUT 1.

As shown in fig. 7: the B1C filter circuit comprises a dielectric filter U10, wherein an RF-B1C-OUT is respectively connected with a first end of a resistor R42 and a first end of a resistor R44, a second end of the resistor R42 is respectively connected with a first end of a resistor R45 and a pin 1 of a frequency point filter U8, a second end of the resistor R44 and a second end of a resistor R45 are respectively grounded, a pin 3, a pin 4, a pin 5, a pin 6 and a pin 7 of the frequency point filter U10 are respectively grounded, a pin 2 of the frequency point filter U10 is respectively connected with a first end of the resistor R43 and a first end of a resistor R46, a second end of the resistor R43 is respectively connected with a first end of a resistor R47 and a first end of a capacitor C43, a second end of the resistor R46 and a second end of a resistor R47 are respectively grounded, and a second end of the capacitor C43 is an RF-B1C-OUT 1.

As shown in fig. 8: the power conversion circuit comprises a power chip U4, an external direct current power VCC-5V of the double-frequency point down-conversion module is respectively connected with the first end of a capacitor C12, the first end of a capacitor C13, a pin 1 and a pin 7 of a power chip U4 after entering through a pin 28 and a pin 29 of a semicircular stamp hole, the pin 0, the pin 4 and the pin 6 of the power chip U4 are respectively grounded, the pin 8 of the power chip U4 is connected with the first end of the resistor R11, the first end of the resistor R12 and the capacitor C11 which are connected in parallel is respectively connected with the pin 2 of the power chip U4 and the second end of the resistor R11, the second end ground after resistance R12 and electric capacity C11 connect in parallel, power chip U4's pin 3 and pin 5 are the chip output pin and connect power filter electric capacity C14's first end and DC power supply VCC-3.3V respectively, power filter electric capacity C14's second end ground.

As shown in fig. 9: the frequency conversion processing circuit comprises an integrated circuit U7, an RF-B3-OUT1 is connected with a first end of an inductor L7, a second end of the inductor L7 is connected with a pin 9 of an integrated circuit U7 after being connected with a capacitor C36, an RF-B1C-OUT1 is connected with a pin 15 of an integrated circuit U7 after being connected with a capacitor C44 and an inductor L10 in sequence, a pin 2 of the integrated circuit U7 is connected with first ends of a resistor R22 and a resistor R23 respectively, a second end of the resistor R23 is grounded, a second end of the resistor R22 is connected with a power supply VCC-3.3V-2202, a pin 5 of the integrated circuit U7 is connected with a power supply VCC-3.3V-2202 and a grounded power supply filter capacitor C29 respectively, a pin 6 of the integrated circuit U7 is connected with first ends of a resistor R24 and a capacitor C32 respectively, a second end of the resistor R32 is connected with a first end of a capacitor C32, pin 7 of the integrated circuit U7 is connected to VCC-3.3V-2202 and a grounded power supply filter capacitor C34 respectively, pin 8 of the integrated circuit U7 is connected to a resistor R25 and then grounded, pin 11 of the integrated circuit U7 is connected to VCC-3.3V-2202 and a grounded power supply filter capacitor C40 respectively, pin 12 of the integrated circuit U7 is connected to a resistor R33 and then grounded, pin 13 of the integrated circuit U7 is connected to VCC-3.3V-2202 and a grounded power supply filter capacitor C42 respectively, pin 17 of the integrated circuit U7 is connected to resistor R48 and then to VCC-3.3V-2202, pin 18 of the integrated circuit U7 is connected to VCC-3.3V-2202 and a grounded power supply filter capacitor C48 respectively, pin 19 of the integrated circuit U7 is connected to resistor R53 and a first end of a capacitor C45 respectively, a second end of the resistor R53 is connected to a second end of the capacitor C54, the second end of the capacitor C45 is connected with the second end of the capacitor C54 and then grounded, the pin 20 of the integrated circuit U7 is connected with the capacitor C49 and then grounded, the pin 22 and the pin 23 of the integrated circuit U7 are respectively connected with the power VCC-3.3V-2202 and the grounded power filter capacitor C50, the pin 26 of the integrated circuit U7 is respectively connected with the power VCC-3.3V-2202 and the grounded power filter capacitor C46, the pin 27 of the integrated circuit U7 is connected with the capacitor C47 and then grounded, the pin 29 of the integrated circuit U7 is connected with the resistor R49 and then connected with the B1C frequency point output intermediate frequency output IF-B1C-D3 and output through the pin 44 of the semicircular stamp hole, the pin 30 of the integrated circuit U7 is connected with the resistor R50 and then connected with the B1C output intermediate frequency output-B1C-D2 and output through the pin 45 of the semicircular stamp hole, the pin 31B 31 of the integrated circuit U2 is connected with the pin R56 and then connected with the intermediate frequency output IF output frequency point IF C-IF output-IF C and 8653 D1 is output through a pin 46 of a semicircular stamp hole, a pin 32 of an integrated circuit U7 is connected with a resistor R52 and then connected with a B1c frequency point output intermediate frequency output IF-B1c-D0 and output through a pin 47 of the semicircular stamp hole, a pin 35 of the integrated circuit U7 is connected with a resistor R39 and then connected with a B3 frequency point output intermediate frequency output IF-B3-D3 and output through a pin 39 of the semicircular stamp hole, a pin 36 of the integrated circuit U7 is connected with a resistor R37 and then connected with a B3 frequency point output intermediate frequency output IF-B3-D2 and output through a pin 40 of the semicircular stamp hole, a pin 37 of the integrated circuit U7 is connected with a resistor R36 and then connected with a B3 frequency point output IF-B3-D1 and output through a pin 41 of the semicircular stamp hole, a pin 38 of the integrated circuit U7 is connected with a resistor R7 and then connected with an intermediate frequency output IF-B7 and output through the semicircular stamp hole 7 and output pin 42, pin 47 of the integrated circuit U7 is connected to VCC-3.3V-2202 and a grounded power supply filter capacitor C35 respectively, pin 48 of the integrated circuit U7 is connected to a capacitor C33 and then connected to a B1C frequency point analog-to-digital signal output terminal IF-B1C-a, pin 51 of the integrated circuit U7 is connected to a capacitor C31 and then connected to a B3 frequency point analog-to-digital signal output terminal IF-B3-a, pin 54 of the integrated circuit U7 is connected to a power supply-3.3V-2202 and a grounded power supply filter capacitor C24 respectively, pin 55 of the integrated circuit U7 is connected to a capacitor C23 and then grounded, pin 59 of the integrated circuit U7 is connected to VCC-3V-VCC and a grounded power supply filter capacitor C22 respectively, pin 60 of the integrated circuit U7 is connected to a resistor R21 and then connected to an SPI control point SPI-CS, pin 61 of the integrated circuit U7 is connected to a resistor R20 and then to an SPI-CS, pin 62 of the integrated circuit U7 is connected with resistor R19 and then connected with SPI control point SPI-MOSI, pin 63 of the integrated circuit U7 is connected with resistor R18 and then connected with SPI control point SPI-MISO, pin 64 of the integrated circuit U7 is connected with capacitor C27 and then connected with 10MHz reference signal input port 10MHZ-IC-IN, pin 65 of the integrated circuit U7 is respectively connected with power VCC-3.3V-2202 and grounded power filter capacitor C26, pin 67 of the integrated circuit U7 is respectively connected with power VCC-3.3V-2202 and grounded power filter capacitor C25, and pin 69 of the integrated circuit U7 is grounded;

the frequency conversion processing circuit further comprises an operational amplifier U11, wherein a B3 frequency point analog intermediate frequency signal IF-B3-OUT is output through a 11 th pin of a semicircular stamp hole and is respectively connected with a first end of a capacitor C51 and a first end of an inductor L11, a second end of the capacitor C51 is grounded, a second end of an inductor L11 is sequentially connected with a resistor R54 and a capacitor C53 and then is connected with a pin 1 of an operational amplifier U11, a pin 2 and a pin 4 of the operational amplifier U11 are grounded, a pin 5 of the operational amplifier U11 is respectively connected with a first end of a resistor R56, a first end of an inductor L12 and a first end of a capacitor C52, a second end of the capacitor C52 is grounded, a second end of the inductor L12 is connected with a direct current power supply VCC-3.3V, a B3 frequency point analog intermediate frequency signal IF-B3-A of an integrated circuit is respectively connected with a first end of a resistor R57 and a first end of a resistor R55, and a second end of the resistor R57 is grounded, the pin 3 of the operational amplifier U11 is respectively connected with the second end of the resistor R55, the second end of the resistor R56 and the first end of the resistor R58, and the second end of the resistor R58 is grounded.

The invention mainly realizes the frequency conversion part of the satellite navigation receiving link, and digitally separates the module region complete machine of the invention to the greatest extent when in use, thereby ensuring good electromagnetic compatibility characteristic.

In conclusion, the invention realizes the down-conversion function of the double-frequency point signal in the Beidou third-generation navigation signal, outputs the band-pass signal, can realize navigation PVT resolving by matching with the sampling clock, and provides a good simulation solution for the complete machine system of the Beidou third-generation navigation positioning user machine.

Claims

1. The utility model provides a miniaturized big dipper third generation dual-frenquency point down conversion integrated circuit board which characterized in that: the dual-frequency point down-conversion module is arranged between a low noise amplifier and a complete machine mainboard of a receiver, the dual-frequency point down-conversion module is arranged on the complete machine mainboard of the receiver by adopting semicircular stamp holes and is fixedly arranged on the complete machine mainboard of the receiver, the number of the semicircular stamp holes is 54, the semicircular stamp holes are respectively numbered as pins 1 to 54, the pin 25 is a radio frequency input port, the radio frequency input port respectively receives a B1c frequency point satellite navigation signal and a B3 frequency point satellite navigation signal which are processed by space navigation signal electromagnetic waves through active antenna low noise amplification and filtering and transmits the signals to an amplifying circuit, the amplifying circuit synchronously amplifies the B1c frequency point satellite navigation signal and the B3 frequency point satellite navigation signal and transmits the signals to a power dividing circuit, the power dividing circuit respectively transmits the B1c frequency point satellite navigation signal and the B3 frequency point satellite navigation signal to a B3 filter circuit and a B1c filter circuit, the output ends of the B3 filter circuit and the B1c filter circuit are connected to a frequency conversion processing circuit, the frequency conversion processing circuit respectively and correspondingly down-converts the radio frequency of the B1c frequency point and the radio frequency of the B3 frequency point to the corresponding intermediate frequency of the B1c frequency point and the intermediate frequency of the B3 frequency point, thereby realizing the moving of frequency spectrum, the frequency conversion processing circuit converts the intermediate frequency of the frequency point B1c and the intermediate frequency of the frequency point B3 into digital intermediate frequency signals to be output, 10MHz reference signals are input into the frequency conversion processing circuit, the frequency conversion processing circuit outputs 80MHz sampling clock signals, one end of a feed circuit is connected with a direct current power VCC-5V input end, the other end outputs direct current to feed a low noise amplifier at the front end of the module, the input end of the direct current power VCC-5V is also connected with a power conversion circuit, the power supply conversion circuit converts a direct current power supply VCC-5V into a direct current power supply VCC-3.3V for output and respectively provides the output to the amplifying circuit and the frequency conversion processing circuit.

2. The miniaturized three-generation Beidou satellite two-frequency point down-conversion board card according to claim 1, characterized in that: the feed circuit unit comprises a restorable fuse R1, a choke coil inductor L1, a power supply filter capacitor C1 and a power supply filter capacitor C2, wherein the input end of a direct current power supply VCC-5V enters the first end connected with the restorable fuse R1 through the 28 th pin and the 29 th pin of a semicircular stamp hole, the second end of the restorable fuse R1 is respectively connected with the first end, connected with the power supply filter capacitor C1 and the power supply filter capacitor C2 in parallel, of the restorable fuse R1, the second end, connected with the power supply filter capacitor C1 and the power supply filter capacitor C2 in parallel, of the restorable fuse R1 is grounded, and the second end of the choke coil inductor L1 outputs direct current through the 25 th pin of the semicircular stamp hole to feed the low noise amplifier at the front end of the module.

3. The miniaturized three-generation Beidou satellite dual-frequency point down-conversion board card according to claim 2, characterized in that: the amplifying circuit comprises a monolithic amplifier U3, a low noise amplifier at the front end of the module processes a radio frequency navigation signal RF-IN and inputs the radio frequency navigation signal RF-IN into the module through a 25 th pin of a semicircular stamp hole and is connected with a first end of a coupling capacitor C6, a second end of the coupling capacitor C6 is respectively connected with a first end of a resistor R9, a resistor R3 and a first end of a resistor R5, a second end of the resistor R9 is grounded, the resistor R3, a resistor R5 and a resistor R4 form a pi-type impedance matching network, a second end of a resistor R5 is respectively connected with a first end of a resistor R4 and a first end of a coupling capacitor C7, a second end of a resistor R3 and a second end of a resistor R4 are respectively grounded, a second end of the coupling capacitor C7 is connected with a pin 4 of a monolithic amplifier U3, a pin 0, a pin 2, a pin 3, a pin 5, a pin 6, a pin 7 and a pin 398 of the monolithic amplifier U4642 are respectively connected with a first end of an inductor L and a first end of a coupling capacitor C8, the second end of the inductor L2 is respectively connected with the first ends of an inductor C3, an inductor C4 and a resistor R2, the second ends of the inductor C3 and the inductor C4 are respectively grounded, the second end of the resistor R2 is connected with a direct current power supply VCC-3.3V, the second end of the coupling capacitor C8 is respectively connected with the first ends of a resistor R10, a resistor R7 and a resistor R6, the second end of the resistor R6 is connected with the first end of the resistor R8 and RF-IN-1, and the second ends of the resistor R10, the resistor R7 and the resistor R8 are respectively grounded.

4. The miniaturized three-generation Beidou satellite dual-frequency point down-conversion board card according to claim 3, characterized in that: the power dividing circuit comprises a power divider U2, wherein an RF-IN-1 is connected with a pin 2 of a power divider U2, the pin 1, the pin 3, the pin 4, the pin 5, the pin 6, the pin 8, the pin 10, the pin 11 and the pin 12 of the power divider U2 are respectively grounded, the pin 9 of the power divider U2 is connected with a first end of a capacitor C5, a second end of the capacitor C5 is RF-B3-OUT, the pin 7 of the power divider U2 is connected with a first end of the capacitor C10, and a second end of the capacitor C10 is RF-B1C-OUT.

5. The miniaturized three-generation Beidou satellite two-frequency point down-conversion board card according to claim 4, characterized in that: the B3 filter circuit comprises a frequency point filter U8, wherein an RF-B3-OUT is respectively connected with a first end of a resistor R26 and a first end of a resistor R29, a second end of the resistor R26 is respectively connected with a first end of a resistor R30 and a pin 2 of a frequency point filter U8, a second end of the resistor R29 and a second end of a resistor R30 are respectively grounded, a pin 1, a pin 3, a pin 4 and a pin 6 of the frequency point filter U8 are respectively grounded, a pin 5 of the B3 frequency point filter U8 is respectively connected with a first end of a resistor R27 and a first end of a resistor R31, a second end of the resistor R27 is respectively connected with a first end of a resistor R32 and a first end of a capacitor C37, a second end of the resistor R31 and a second end of a resistor R32 are respectively grounded, and a second end of the capacitor C37 is an RF-B3-OUT 1.

6. The miniaturized three-generation Beidou satellite two-frequency point down-conversion board card according to claim 5, characterized in that: the B1C filter circuit comprises a dielectric filter U10, wherein an RF-B1C-OUT is respectively connected with a first end of a resistor R42 and a first end of a resistor R44, a second end of the resistor R42 is respectively connected with a first end of a resistor R45 and a pin 1 of a frequency point filter U8, a second end of the resistor R44 and a second end of a resistor R45 are respectively grounded, a pin 3, a pin 4, a pin 5, a pin 6 and a pin 7 of the frequency point filter U10 are respectively grounded, a pin 2 of the frequency point filter U10 is respectively connected with a first end of the resistor R43 and a first end of a resistor R46, a second end of the resistor R43 is respectively connected with a first end of a resistor R47 and a first end of a capacitor C43, a second end of the resistor R46 and a second end of a resistor R47 are respectively grounded, and a second end of the capacitor C43 is an RF-B1C-OUT 1.

7. The miniaturized three-generation Beidou satellite two-frequency point down-conversion board card according to claim 6, characterized in that: the power conversion circuit comprises a power chip U4, an external direct current power VCC-5V of the double-frequency point down-conversion module is respectively connected with the first end of a capacitor C12, the first end of a capacitor C13, a pin 1 and a pin 7 of a power chip U4 after entering through a pin 28 and a pin 29 of a semicircular stamp hole, the pin 0, the pin 4 and the pin 6 of the power chip U4 are respectively grounded, the pin 8 of the power chip U4 is connected with the first end of the resistor R11, the first end of the resistor R12 and the capacitor C11 which are connected in parallel is respectively connected with the pin 2 of the power chip U4 and the second end of the resistor R11, the second end ground after resistance R12 and electric capacity C11 connect in parallel, power chip U4's pin 3 and pin 5 are the chip output pin and connect power filter electric capacity C14's first end and DC power supply VCC-3.3V respectively, power filter electric capacity C14's second end ground.

8. The miniaturized three-generation Beidou satellite two-frequency point down-conversion board card according to claim 7, characterized in that: the frequency conversion processing circuit comprises an integrated circuit U7, an RF-B3-OUT1 is connected with a first end of an inductor L7, a second end of the inductor L7 is connected with a pin 9 of an integrated circuit U7 after being connected with a capacitor C36, an RF-B1C-OUT1 is connected with a pin 15 of an integrated circuit U7 after being connected with a capacitor C44 and an inductor L10 in sequence, a pin 2 of the integrated circuit U7 is connected with first ends of a resistor R22 and a resistor R23 respectively, a second end of the resistor R23 is grounded, a second end of the resistor R22 is connected with a power supply VCC-3.3V-2202, a pin 5 of the integrated circuit U7 is connected with a power supply VCC-3.3V-2202 and a grounded power supply filter capacitor C29 respectively, a pin 6 of the integrated circuit U7 is connected with first ends of a resistor R24 and a capacitor C32 respectively, a second end of the resistor R32 is connected with a first end of a capacitor C32, pin 7 of the integrated circuit U7 is connected to VCC-3.3V-2202 and a grounded power supply filter capacitor C34 respectively, pin 8 of the integrated circuit U7 is connected to a resistor R25 and then grounded, pin 11 of the integrated circuit U7 is connected to VCC-3.3V-2202 and a grounded power supply filter capacitor C40 respectively, pin 12 of the integrated circuit U7 is connected to a resistor R33 and then grounded, pin 13 of the integrated circuit U7 is connected to VCC-3.3V-2202 and a grounded power supply filter capacitor C42 respectively, pin 17 of the integrated circuit U7 is connected to resistor R48 and then to VCC-3.3V-2202, pin 18 of the integrated circuit U7 is connected to VCC-3.3V-2202 and a grounded power supply filter capacitor C48 respectively, pin 19 of the integrated circuit U7 is connected to resistor R53 and a first end of a capacitor C45 respectively, a second end of the resistor R53 is connected to a second end of the capacitor C54, the second end of the capacitor C45 is connected with the second end of the capacitor C54 and then grounded, the pin 20 of the integrated circuit U7 is connected with the capacitor C49 and then grounded, the pin 22 and the pin 23 of the integrated circuit U7 are respectively connected with the power VCC-3.3V-2202 and the grounded power filter capacitor C50, the pin 26 of the integrated circuit U7 is respectively connected with the power VCC-3.3V-2202 and the grounded power filter capacitor C46, the pin 27 of the integrated circuit U7 is connected with the capacitor C47 and then grounded, the pin 29 of the integrated circuit U7 is connected with the resistor R49 and then connected with the B1C frequency point output intermediate frequency output IF-B1C-D3 and output through the pin 44 of the semicircular stamp hole, the pin 30 of the integrated circuit U7 is connected with the resistor R50 and then connected with the B1C output intermediate frequency output-B1C-D2 and output through the pin 45 of the semicircular stamp hole, the pin 31B 31 of the integrated circuit U2 is connected with the pin R56 and then connected with the intermediate frequency output IF output frequency point IF C-IF output-IF C and 8653 D1 is output through a pin 46 of a semicircular stamp hole, a pin 32 of an integrated circuit U7 is connected with a resistor R52 and then connected with a B1c frequency point output intermediate frequency output IF-B1c-D0 and output through a pin 47 of the semicircular stamp hole, a pin 35 of the integrated circuit U7 is connected with a resistor R39 and then connected with a B3 frequency point output intermediate frequency output IF-B3-D3 and output through a pin 39 of the semicircular stamp hole, a pin 36 of the integrated circuit U7 is connected with a resistor R37 and then connected with a B3 frequency point output intermediate frequency output IF-B3-D2 and output through a pin 40 of the semicircular stamp hole, a pin 37 of the integrated circuit U7 is connected with a resistor R36 and then connected with a B3 frequency point output IF-B3-D1 and output through a pin 41 of the semicircular stamp hole, a pin 38 of the integrated circuit U7 is connected with a resistor R7 and then connected with an intermediate frequency output IF-B7 and output through the semicircular stamp hole 7 and output pin 42, pin 47 of the integrated circuit U7 is connected to VCC-3.3V-2202 and a grounded power supply filter capacitor C35 respectively, pin 48 of the integrated circuit U7 is connected to a capacitor C33 and then connected to a B1C frequency point analog-to-digital signal output terminal IF-B1C-a, pin 51 of the integrated circuit U7 is connected to a capacitor C31 and then connected to a B3 frequency point analog-to-digital signal output terminal IF-B3-a, pin 54 of the integrated circuit U7 is connected to a power supply-3.3V-2202 and a grounded power supply filter capacitor C24 respectively, pin 55 of the integrated circuit U7 is connected to a capacitor C23 and then grounded, pin 59 of the integrated circuit U7 is connected to VCC-3V-VCC and a grounded power supply filter capacitor C22 respectively, pin 60 of the integrated circuit U7 is connected to a resistor R21 and then connected to an SPI control point SPI-CS, pin 61 of the integrated circuit U7 is connected to a resistor R20 and then to an SPI-CS, pin 62 of the integrated circuit U7 is connected with resistor R19 and then connected with SPI control point SPI-MOSI, pin 63 of the integrated circuit U7 is connected with resistor R18 and then connected with SPI control point SPI-MISO, pin 64 of the integrated circuit U7 is connected with capacitor C27 and then connected with 10MHz reference signal input port 10MHZ-IC-IN, pin 65 of the integrated circuit U7 is respectively connected with power VCC-3.3V-2202 and grounded power filter capacitor C26, pin 67 of the integrated circuit U7 is respectively connected with power VCC-3.3V-2202 and grounded power filter capacitor C25, and pin 69 of the integrated circuit U7 is grounded;

9. The miniaturized three-generation Beidou satellite two-frequency point down-conversion board card according to claim 1, characterized in that: the frequency point of the B3 frequency point satellite navigation signal is 1268.52 +/-10.23 MHz, the intermediate frequency point output from the 39 th pin to the 42 th pin is 15.48 +/-10.23 MHz, and the local oscillation frequency point is 1284 MHz; the frequency point of the B1c frequency point satellite navigation signal is 1575.42 +/-16.368 MHz, the intermediate frequency point output from the 44 th pin to the 47 th pin is 20.58 +/-16.368 MHz, and the local oscillation frequency point is 1596 MHz.