CN113992239B - Device and method for detecting high-speed differential signal - Google Patents
Device and method for detecting high-speed differential signal Download PDFInfo
- Publication number
- CN113992239B CN113992239B CN202111597790.2A CN202111597790A CN113992239B CN 113992239 B CN113992239 B CN 113992239B CN 202111597790 A CN202111597790 A CN 202111597790A CN 113992239 B CN113992239 B CN 113992239B
- Authority
- CN
- China
- Prior art keywords
- speed differential
- differential signal
- dimensional
- signal
- eye pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/46—Monitoring; Testing
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
Abstract
The present disclosure relates to an apparatus for detecting a high-speed differential signal and a method thereof. The device includes: a signal generator; a signal receiver; the error code calculation unit is used for comparing the high-speed differential signal sent by the signal generator with the high-speed differential signal received by the signal receiver so as to obtain an error code in the high-speed differential signal received by the signal receiver; determining whether the P/N ends of the high-speed differential signals are all in an open circuit or short circuit state according to the error codes in the high-speed differential signals received by the signal receiver; the eye pattern calculation unit is used for generating a two-dimensional eye pattern according to the high-speed differential signal received by the signal receiver; counting first error rates of corresponding areas in the two-dimensional eye diagram; and determining whether only one path of the P/N end of the high-speed differential signal is in an open circuit or short circuit state according to the statistical result. By using the scheme disclosed by the invention, the short circuit or open circuit condition of the high-speed differential signal can be effectively detected so as to accurately judge the quality problem of the cable.
Description
Technical Field
The present disclosure relates generally to the field of cabling technology. More particularly, the present disclosure relates to an apparatus, method, and transmission cable apparatus and computer-readable storage medium for detecting high-speed differential signals.
Background
Differential transmission is a signal transmission technology, which is different from the traditional transmission mode of one signal wire and one ground wire. The differential transmission is to transmit signals on the two wires, the signals transmitted on the two wires are differential signals, and the amplitudes of the differential signals are the same, and the phases of the differential signals are opposite. In an application scenario, the signal receiving end compares the difference of the differential signal voltages to determine the logic state sent by the transmitting end. It will be appreciated that the differential signal can control the "reference" voltage, so that small signals can be readily identified that are highly immune to external Electromagnetic Interference ("EMI"). Since one source of interference affects each end of a differential signal pair to approximately the same degree, differential signals generate less EMI than single-ended signals, in addition to being less sensitive to interference, when ignoring any identical interference present on both conductors. Therefore, differential signals are widely applied to high-speed transmission cables such as HDMI, DP, USB, PCIE, and the like.
In an actual production process, a cable high-speed signal wire in a high-speed copper wire transmission cable such as HDMI, DP, USB, PCIE and the like is generally connected to a connector by soldering to transmit a differential signal. However, this is likely to cause disconnection and short-circuiting of the signal wire by soldering or disconnection and short-circuiting of the signal wire itself. Similarly, for AOC cables or ACC cables, soldering high-speed ETX differential signal lines to a high-speed IC chip may cause short circuits, open circuits, and the like, thereby making it impossible to transmit differential signals.
In the use process, the quality problems of differential signals such as open circuit, short circuit and the like can have serious consequences.
For the problem of differential signal quality, currently, test modes such as a measurement device test (for example, a BERT code tester or an oscilloscope) and a functional device are generally adopted, but these modes are only suitable for research and development in a laboratory, and have the problems of high price, high operation difficulty, high device replacement rate and the like, so that the methods are not suitable for mass production test. Therefore, how to effectively detect the high-speed differential signal becomes a technical problem to be solved.
Disclosure of Invention
To at least partially solve the technical problems mentioned in the background, the solution of the present disclosure provides a solution for detecting a high-speed differential signal. By using the scheme disclosed by the invention, whether the high-speed differential signal has short circuit or open circuit or not can be effectively detected. To this end, the present disclosure provides solutions in a number of aspects as follows.
In one aspect, the present disclosure provides an apparatus for detecting a high speed differential signal, wherein the high speed differential signal is transmitted via a transmission cable, and the apparatus comprises: a signal generator for connecting with one end of the transmission cable, for transmitting the high-speed differential signal; the signal receiver is used for being connected with the other end of the transmission cable and receiving the high-speed differential signal; an error code calculation unit connected to the signal generator and the signal receiver and configured to: comparing the high-speed differential signal sent by the signal generator with the high-speed differential signal received by the signal receiver to obtain an error code in the high-speed differential signal received by the signal receiver; determining whether the P/N ends of the high-speed differential signals are all in an open circuit or short circuit state according to the error codes in the high-speed differential signals received by the signal receiver; an eye diagram calculation unit connected with the signal generator and the signal receiver and configured to: generating a two-dimensional eye pattern according to the high-speed differential signal received by the signal receiver; counting a first error rate of a preset area in the two-dimensional eye diagram; and determining whether only one path of the P/N ends of the high-speed differential signals is in an open circuit or short circuit state according to the statistical result.
In one embodiment, in determining whether the P/N terminals of the high-speed differential signal are both open-circuited or short-circuited according to the bit errors in the high-speed differential signal received by the signal receiver, the bit error calculation unit is further configured to: and determining that the P/N ends of the high-speed differential signals are in an open circuit or short circuit state in response to the fact that the error codes in the high-speed differential signals received by the signal receiver are larger than a preset error code value.
In another embodiment, wherein in generating the two-dimensional eye pattern from the high-speed differential signal received by the signal receiver, the eye pattern calculation unit is further configured to: comparing the data of each point in the two-dimensional matrix area corresponding to the high-speed differential signal received by the signal receiver with the data of the central point of the two-dimensional matrix area to determine whether the data of each point in the corresponding two-dimensional matrix area is consistent with the data of the central point of the two-dimensional matrix area; and generating a two-dimensional eye diagram according to the comparison result.
In yet another embodiment, wherein in generating a two-dimensional eye diagram according to the alignment result, the eye diagram calculation unit is further configured to: calculating a first error rate of each point in the corresponding two-dimensional matrix area according to the number of times that the data of each point in the corresponding two-dimensional matrix area is inconsistent with the data of the central point of the point; and generating a two-dimensional eye diagram based on the first bit error rate of each point within the corresponding two-dimensional matrix region.
In yet another embodiment, the predetermined area in the two-dimensional eye pattern comprises an edge area of the two-dimensional eye pattern, a center area of the two-dimensional eye pattern and an entire area of the two-dimensional eye pattern, wherein the edge area of the two-dimensional eye pattern and the center area of the two-dimensional eye pattern are determined via a size of the two-dimensional eye pattern.
In yet another embodiment, in the counting the first error rate of the preset area in the two-dimensional eye pattern, the eye pattern calculation unit is further configured to: and respectively counting points in the edge area of the two-dimensional eye pattern, points in the central area of the two-dimensional eye pattern and first error rates corresponding to all points in the whole area of the two-dimensional eye pattern to obtain corresponding statistical results.
In yet another embodiment, in counting the first error rates of the points in the edge region of the two-dimensional eye pattern, the points in the center region of the two-dimensional eye pattern, and all the point correspondences in the entire region of the two-dimensional eye pattern to obtain corresponding statistical results, the eye pattern calculation unit is further configured to: counting the number of first error rates corresponding to the point in the edge area of the two-dimensional eye pattern, which are larger than a preset threshold value, so as to obtain a first statistical result; counting the number of the point corresponding to the central area of the two-dimensional eye pattern, wherein the first error rate is nonzero, so as to obtain a second statistical result; and counting the sum of the first error rates corresponding to all points in the whole area of the two-dimensional eye pattern to obtain a third statistical result.
In yet another embodiment, in determining whether only one of the P/N terminals of the high-speed differential signal is open or short-circuited according to the statistical result, the eye diagram calculating unit is further configured to: responding to at least one statistical result of the first statistical result, the second statistical result and the third statistical result which is larger than a corresponding threshold value, and determining that only one path of the P/N end of the high-speed differential signal is in an open circuit or short circuit state; or determining that the high-speed differential signal P/N end has no open circuit or short circuit state in response to the first, second and third statistical results being smaller than the corresponding threshold values.
In another aspect, the present disclosure also provides a method for detecting a high speed differential signal, comprising: comparing the high-speed differential signal sent by the signal generator with the high-speed differential signal received by the signal receiver to obtain an error code in the high-speed differential signal received by the signal receiver; determining whether the P/N ends of the high-speed differential signals are all in an open circuit or short circuit state according to the error codes in the high-speed differential signals received by the signal receiver; generating a two-dimensional eye pattern according to the high-speed differential signal received by the signal receiver; counting a first error rate of a preset area in the two-dimensional eye diagram; and determining whether only one path of the P/N ends of the high-speed differential signals is in an open circuit or short circuit state according to the statistical result.
In yet another aspect, the present disclosure also provides a computer readable storage medium having stored thereon computer readable instructions of program instructions for detecting high speed differential signals, which when executed by one or more processors, implement various embodiments as previously described.
According to the scheme, the error codes calculated by the error code calculating unit and the statistical result of the eye pattern calculating unit for counting the first error rate of the preset area in the two-dimensional eye pattern can effectively and accurately determine whether the high-speed differential signal has a short circuit or an open circuit, so that the equipment is prevented from being damaged due to the quality problem of the high-speed differential signal. Further, this disclosed embodiment need not to carry on the plug of cable again and increases the tester, has improved production efficiency to guarantee the production and delivery of high quality cable.
Drawings
The above and other objects, features and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. In the drawings, several embodiments of the disclosure are illustrated by way of example and not by way of limitation, and like or corresponding reference numerals indicate like or corresponding parts and in which:
FIG. 1 is an exemplary diagram illustrating a DP cable transmitting differential signals;
fig. 2 illustrates an exemplary block diagram of an apparatus for detecting high-speed differential signals according to an embodiment of the present disclosure;
FIG. 3 illustrates an exemplary schematic diagram of an apparatus for detecting high speed differential signals according to an embodiment of the disclosure;
FIG. 4 illustrates an exemplary schematic diagram of a two-dimensional eye diagram setting a high-speed differential signal in a normal state according to an embodiment of the disclosure;
fig. 5 illustrates an exemplary schematic diagram of a two-dimensional eye diagram for setting a high-speed differential signal at a single-ended break according to an embodiment of the disclosure;
fig. 6 illustrates an exemplary schematic diagram of a two-dimensional eye diagram setting a high-speed differential signal at a single-ended short circuit according to an embodiment of the disclosure; and
fig. 7 illustrates an exemplary flow diagram of a method for detecting high speed differential signals according to an embodiment of the present disclosure.
Detailed Description
The principles and spirit of the present disclosure will be described with reference to a number of exemplary embodiments. It is understood that these embodiments are given solely for the purpose of enabling those skilled in the art to better understand and to practice the present disclosure, and are not intended to limit the scope of the present disclosure in any way. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Fig. 1 is an exemplary schematic diagram illustrating a DP cable transmitting differential signals. As shown in fig. 1, the display interface ("DP") cable 100 may include two connectors 101 with electronics (not shown) disposed within each connector 101. Further, the two connectors 101 are connected by a copper wire or an optical cable to enable transmission of data signals (e.g., audio signals, video signals) between, for example, the signal source 102 and the display 103. In an application scenario, the DP cable may include a plurality of transmission channels, such as the transmission channels lane0-lane1 and the transmission channel AUX shown in the figure, through which the high-speed differential signals (e.g., lane0+ and lane 0-) may be transmitted.
As is known from the above description of the background art, in an actual production process, a cable high-speed signal wire in, for example, a high-speed copper wire transmission cable is usually connected to a connector by soldering to transmit a high-speed differential signal. This can lead to short circuits or open circuits causing quality problems with serious consequences. For example, when the high-speed signal line and the power line are short-circuited to the device, the device may be burned. When the high-speed signal line is disconnected or the single end is disconnected, the high-speed signal transmission fails on a part of equipment, so that the equipment cannot be normally used. At present, differential signals are generally measured by using a high-speed BERT error detector or an oscilloscope, but the methods are only suitable for being used in laboratory research and development, and the test equipment is expensive and difficult to operate, so that the method is not suitable for production line mass production test.
In addition, production tests can also be performed using functional devices, such as purchasing Source and lighting devices for HDMI cable production tests. However, the method also has the problems that the cost of the test equipment is high, the test equipment is easily burnt by cables with quality problems, the test equipment is quickly damaged by mass plugging operation in production and test, and the like. For functional test equipment with better compatibility, when the condition that only a single end of a high-speed signal is broken or short-circuited is detected, although only the single-end signal is received at a receiving end, the information carried by the signal can still be analyzed, so that a defective product cannot be effectively screened out. For the functional test equipment with poor compatibility, the problem of functional failure can occur.
In view of the above, in order to overcome the defects of one or more aspects, in the embodiments of the present disclosure, a scheme for detecting a high-speed differential signal is provided, which can accurately determine a high-speed differential signal transmission open circuit or short circuit state by combining the results of an error calculation unit and an eye diagram calculation unit, so as to accurately screen out a high-quality cable.
The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the embodiments described in this specification are only some of the embodiments of the present disclosure provided to facilitate a clear understanding of the aspects and to comply with legal requirements, and not all embodiments of the present disclosure may be implemented. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed in the specification without making any creative effort, shall fall within the protection scope of the present disclosure.
Fig. 2 illustrates an exemplary block diagram of an apparatus 200 for detecting high-speed differential signals according to an embodiment of the disclosure. As shown in fig. 2, the apparatus 200 may include a signal generator 201, a signal receiver 202, an error code calculation unit 203, and an eye diagram calculation unit 204. The foregoing signal generator 201, signal receiver 202, error code calculation unit 203, and eye diagram calculation unit 204 will be described in detail below.
As previously described, high-speed differential signals may be transmitted via transmission cables. In one embodiment, the signal generator 201 may be connected to one end of a transmission cable. For an active transmission cable, it may be connected with a connector at one end of the transmission cable. In one implementation scenario, the signal generator 201 may be configured to transmit a high-speed differential signal whose data representation is, for example, a number of bits. In one embodiment, the signal receiver 202 may be connected to the other end of the transmission cable. Similarly, for an active transmission cable, it may be connected with a connector at the other end of the transmission cable. Corresponding to the aforementioned signal generator 201, the signal receiver 202 may be used to receive a high-speed differential signal, and the received high-speed differential signal data representation is also a number of bits.
In an embodiment, the error calculation unit 203 may be connected to the signal transmitter and the signal receiver, and configured to compare the high-speed differential signal transmitted by the signal generator with the high-speed differential signal received by the signal receiver to obtain an error in the high-speed differential signal received by the signal receiver. Further, whether the P/N ends of the high-speed differential signals are all in an open circuit or short circuit state is determined according to the error codes in the high-speed differential signals received by the signal receiver. Specifically, the error code calculation unit compares the number of bits of the high-speed signal data transmitted by the signal generator (or the transmitting end of the transmission cable) with the number of bits of the high-speed signal data received by the signal receiver (or the receiving end of the transmission cable), and records the number of times that the corresponding number of bits of the high-speed signal data does not coincide with the corresponding number of bits of the high-speed signal data, so as to obtain an error code (bit error rate) in the high-speed differential signal received by the signal receiver. And then, comparing the error codes in the high-speed differential signals received by the signal receiver with the preset error code value to determine whether the P/N ends of the high-speed differential signals are all in an open circuit or short circuit state. For example, when the error code in the high-speed differential signal received by the signal receiver is greater than the preset error code value, it may be determined that the P/N end (i.e., both ends) of the high-speed differential signal is in an open circuit or short circuit state.
In an embodiment, the eye diagram calculation unit 204 may also be connected to the signal transmitter and the signal receiver, and configured to generate a two-dimensional eye diagram according to the high-speed differential signal received by the signal receiver, and then count a first error rate of a preset area in the two-dimensional eye diagram. Further, whether only one path of the P/N ends of the high-speed differential signals is in an open circuit or short circuit state is determined according to a statistical result. In an implementation scenario, the eye diagram calculation unit first compares data of each point in a two-dimensional matrix area corresponding to a high-speed differential signal received by the signal receiver with data of a central point of the two-dimensional matrix area to determine whether the data of each point in the corresponding two-dimensional matrix area is consistent with the data of the central point, and then generates a two-dimensional eye diagram according to a comparison result. Specifically, the first error rate of each point in the corresponding two-dimensional matrix area is calculated according to the number of times that the data of each point in the corresponding two-dimensional matrix area is inconsistent with the data of the center point of the point. Then, a two-dimensional eye diagram is generated based on the first error rate of each point within the corresponding two-dimensional matrix region.
It is understood that the data of each point in the two-dimensional matrix area corresponding to the high-speed differential signal is formed by the overlapping of each symbol waveform in the high-speed differential signal. In the aforementioned two-dimensional matrix region, the horizontal axis represents time and the vertical axis represents density, which can reflect the overall characteristics of the high-speed differential signal. In an exemplary scenario, assuming that the size of the two-dimensional matrix region is M × N, M × N points in the two-dimensional matrix region are sequentially traversed and compared with data in the center of the two-dimensional matrix region. After multiple comparisons, the number of times that each point is inconsistent is recorded, and a first error rate corresponding to each point can be obtained, wherein the first error rate corresponding to each point forms a two-dimensional eye diagram with the size of M x N.
When a short circuit or an open circuit occurs in the high-speed differential signal, the data of the corresponding (eye pattern) may increase in the edge area, and the zero bit error area in the middle area may shrink or disappear. Therefore, the embodiment of the present disclosure respectively counts the points in the edge region, the points in the center region, and the first error rates corresponding to all the points of the two-dimensional eye pattern, so as to obtain the statistical result. That is, the preset region of the two-dimensional eye pattern may include a border region of the two-dimensional eye pattern, a center region of the two-dimensional eye pattern, and an entire region of the two-dimensional eye pattern. More specifically, the eye diagram calculation unit counts the number of points corresponding to the edge region of the two-dimensional eye diagram, where the first error rate is greater than a preset threshold, so as to obtain a first statistical result; counting the number of the point corresponding to the central area of the two-dimensional eye pattern, wherein the first error rate is nonzero, so as to obtain a second statistical result; and counting the sum of the first error rates corresponding to all points in the whole area of the two-dimensional eye diagram to obtain a third statistical result. Wherein the edge regions of the two-dimensional eye diagram and the central region of the two-dimensional eye diagram are determined via the size of the two-dimensional eye diagram, for example according to M and N.
Further, whether only one path of the P/N end of the high-speed differential signal is in an open circuit or short circuit state is determined according to the statistical result. For example, when at least one of the first, second, and third statistical results is greater than the corresponding threshold, it is determined that only one path (i.e., single end) of the P/N end of the high-speed differential signal is open or short-circuited. And when the first, second and third statistical results are all smaller than the corresponding threshold values, determining that the P/N ends of the high-speed differential signals are in a non-open circuit or short circuit state.
As can be seen from the above description, according to the embodiments of the present disclosure, through the error code calculated by the error code calculating unit and the statistical result of the first error rate of the preset region in the two-dimensional eye diagram by the eye diagram calculating unit, whether the high-speed differential signal is in a normal state, and whether both ends of the high-speed differential signal are short-circuited or open-circuited or single-ended short-circuited or open-circuited can be accurately determined, so that the cable with a quality problem can be accurately screened out. Further, this disclosed embodiment need not to carry out the plug of cable or increase the tester, has improved production efficiency to guarantee the production and delivery of high quality cable, make and be applicable to production line batch production and detect.
Fig. 3 illustrates an exemplary schematic diagram of an apparatus for detecting high speed differential signals according to an embodiment of the disclosure. It is to be understood that the apparatus of fig. 3 is an embodiment of the apparatus 200 of fig. 2 described above, and therefore the description made above with respect to fig. 2 applies equally to fig. 3.
As shown in fig. 3, the apparatus of the embodiment of the present disclosure may include a signal transmitter 201 and a signal receiver 202, the signal transmitter 201 and the signal receiver 202 being connected to one end and the other end of a transmission cable 301, respectively. As described above, in the case of the active transmission cable, the aforementioned signal transmitter and signal receiver may be connected to connectors at both ends of the transmission cable, respectively. Among them, the signal transmitter 201 may transmit a high-speed differential signal, which is transmitted to the signal receiver 202 via the transmission cable 301 and received by the signal receiver 202. Further, an error code calculation unit 203 and an eye diagram calculation unit 204 may be connected between the signal transmitter 201 and the signal receiver 202. The error code calculating unit 203 is configured to compare the high-speed differential signal sent by the signal generator with the high-speed differential signal received by the signal receiver, and obtain an error code in the high-speed differential signal received by the signal receiver according to the number of times of inconsistency of the comparison. And then, comparing the error code with a preset error code value, and determining that the P/N ends of the high-speed differential signals are in an open circuit or short circuit state when the error code is larger than the preset error code value. Taking the error code preset value as 30% as an example, when the error code is greater than 30%, it is determined that the P/N ends of the high-speed differential signal are both in an open circuit or short circuit state.
The eye diagram calculating unit 204 is first configured to compare data of each point in the two-dimensional matrix region corresponding to the high-speed differential signal received by the signal receiver with data of the central point of the two-dimensional matrix region, calculate a first error rate of each point in the corresponding two-dimensional matrix region according to the number of times that the data of each point in the corresponding two-dimensional matrix region is inconsistent with the data of the central point, and further form a two-dimensional eye diagram according to the first error rate corresponding to each point. And then, counting the first error rate of a preset area in the two-dimensional eye diagram, and determining whether only one path of the P/N end of the high-speed differential signal is in an open circuit or short circuit state according to the counting result. For example, the number of first error rates corresponding to the point in the edge region of the two-dimensional eye pattern, which are larger than a preset threshold, is counted, the number of first error rates corresponding to the point in the center region of the two-dimensional eye pattern, which are non-zero, is counted, and the sum of the first error rates corresponding to all the points in the whole region of the two-dimensional eye pattern is counted to obtain corresponding first, second and third statistical results. And comparing the first, second and third statistical results with the corresponding threshold values to determine the open circuit or short circuit state of the high-speed differential signal. Specifically, when at least one of the first, second and third statistical results is greater than the corresponding threshold, it is determined that only one path of the P/N end of the high-speed differential signal is in an open circuit or short circuit state. And when the first, second and third statistical results are all smaller than the corresponding threshold values, determining that the P/N ends of the high-speed differential signals are in a non-open circuit or short circuit state. Reference is made to the above description of fig. 2, and the disclosure is not repeated herein.
Based on the above description, the edge region and the center region of the two-dimensional eye pattern may be determined according to the size M × N of the two-dimensional eye pattern. In general, in the M >12, N >12 scenario, the edge region thereof may be defined as a region from the 1 st row to the 2 nd row, the (M-1) th row to the M th row, and the 1 st column to the 2 nd column, and the (N-1) th column to the N th column of the two-dimensional eye diagram. The aforementioned central region may define a region that merges from the (M/2-4) th row to the (M/2 + 4) th row and the (N/2-4) th column to the (N/2 + 4) th row of the two-dimensional eye diagram. According to the determined region, counting the points of the edge region, the points of the center region and the first error rates corresponding to all the points of the two-dimensional eye pattern through an eye pattern calculation unit to obtain corresponding first, second and third statistical results.
In an embodiment, the eye diagram calculation unit may count the number of the point correspondences in the edge region of the two-dimensional eye diagram, where the first error rate is greater than a preset threshold, to obtain a first statistical result. The first statistical result 2DEye edge is expressed by the following equation:
wherein d2eyeij is the value of the two-dimensional eye diagram at the (i, j) th point, namely the first error rate corresponding to the (i, j) th point,
indicating the result of the determination. For example when d2eyeij is greater than a preset threshold,
is 1, and vice versa
Is 0. The first statistical result can be obtained by adding the judgment results of the points along the edge area. In the disclosed embodiment, the preset threshold may be obtained from an empirical value, and may be 0.2, for example.
In one embodiment, the eye diagram calculation unit may count the number of non-zero first bit error rates corresponding to the point in the central region of the two-dimensional eye diagram to obtain the second statistical result. The second statistical result 2DEye center can be expressed as follows:
2DEye center =
（2）
Wherein d2eyeij is the value of the two-dimensional eye diagram at the (i, j) th point, namely the first error rate corresponding to the (i, j) th point,
indicating the result of the determination. For example when d2eyeij is not zero,
is 1, and vice versa
Is 0. The second statistical result can be obtained by adding the judgment results of the points of the central area.
In an embodiment, the eye diagram calculation unit may further perform statistics on a sum of the first error rates of all the point correspondences of the two-dimensional eye diagram to obtain a third statistical result. The third statistical result 2DEyeTotal can be expressed as follows:
2DEyeTotal=
（3）
wherein d2eyeij is a numerical value of the two-dimensional eye diagram at the (i, j) th point, that is, the first error rate corresponding to the (i, j) th point. And adding the first error rates corresponding to all the points to obtain a third statistical result.
After the eye diagram calculation unit obtains the first, second, and third statistical results, the first, second, and third statistical results may be compared with corresponding threshold pre-values, respectively, and then it is determined whether only one path of the P/N end of the high-speed differential signal is open or short based on the comparison result. In one implementation scenario, the high-speed differential signals may be set to be in a normal state, a single-ended short circuit, and a single-ended open circuit, and the corresponding first, second, and third statistical results may be calculated in the three scenarios, respectively. Further, the threshold pre-value corresponding to each region is determined through the corresponding first, second and third statistical results. How to determine the threshold pre-value will be described in detail below with reference to fig. 4-6.
Fig. 4 illustrates an exemplary schematic diagram of a two-dimensional eye diagram setting a high-speed differential signal in a normal state according to an embodiment of the present disclosure. Fig. 4 shows a 16 × 16 two-dimensional eye diagram, in which each point represents the bit error rate of the high-speed differential signal at the cable transmitting end and the cable transmitting end. By using the above formula (1) to formula (3), the first statistical result 2 deep edge (normal) of the high-speed differential signal in the normal state is 36, the second statistical result 2 deep edge (normal) is 0, and the third statistical result is calculated to obtain that 2 deep total (normal) is 13.59621776.
Fig. 5 illustrates an exemplary schematic diagram of a two-dimensional eye diagram for setting high-speed differential signals at single-ended opens according to an embodiment of the disclosure. Fig. 5 shows a 16 × 16 two-dimensional eye diagram, where each point represents the bit error rate of the high-speed differential signal at the cable transmitting end and the cable transmitting end. Similarly, the second statistical result 2 deep edge (single-ended open circuit) of the high-speed differential signal with single-ended open circuit is 58, the second statistical result 2 deep edge (single-ended open circuit) is 15, and the second statistical result is calculated to obtain that 2 deep total (single-ended open circuit) is 26.19154353 by using the above equations (1) to (3).
Fig. 6 illustrates an exemplary schematic diagram of a two-dimensional eye diagram setting a high-speed differential signal at a single-ended short circuit according to an embodiment of the disclosure. Fig. 6 shows a 16 × 16 two-dimensional eye diagram, in which each point represents the bit error rate of the high-speed differential signal at the cable transmitting end and the cable transmitting end. Similarly, the third statistical result 2 deep edge (single-ended short circuit) of the single-ended short-circuited high-speed differential signal is 56, the second statistical result 2 deep edge (single-ended short circuit) is 18, and the second statistical result is calculated to obtain that 2 deep total (single-ended short circuit) is 23.9967154 by using the above formula (1) -formula (3).
And determining a threshold preset value according to the corresponding first, second and third statistical results of the high-speed differential signal in a normal state, a single-ended short circuit and a single-ended open circuit. In an exemplary scenario, the threshold pre-value corresponding to the edge region may be, for example, 2DEye edge (normal)/3 + (2DEye edge (single-ended open) +2DEye edge (single-ended short))/2) × 2/3. The threshold pre-value corresponding to the center region may be, for example, 2DEye center (normal)/3 + (2DEye center (single-ended open) +2DEye center (single-ended short))/2) × 2/3. The threshold pre-value corresponding to all regions may be, for example, (2DEyeTotal (normal) + (2DEyeTotal (single-ended open) +2DEyeTotal (single-ended short))/2). Based on this, the threshold pre-value corresponding to the edge area is 50, the threshold pre-value corresponding to the central area is 11, and the threshold pre-values corresponding to all the areas are 19.5. It should be understood that the calculation formula of the threshold advance values corresponding to the foregoing respective regions in the embodiments of the present disclosure is merely exemplary and not limiting, and the numerical value (e.g., 2, 2/3, 3) in each calculation formula may be set according to an actual scenario. Based on the corresponding threshold value, whether only one path of the P/N end of the high-speed differential signal is in an open circuit or short circuit state can be determined. For example, when the first statistical result is less than 50, the second statistical result is less than 11, and the third statistical result is less than 19.5, it can be determined that none of the P/N terminals of the high-speed differential signal is open or short-circuited. When the first statistical result is greater than 50, or the second statistical result is greater than 11, or the third statistical result is greater than 19.5, that is, at least one statistical result is greater than the corresponding threshold, it may be determined that only one path of the P/N end of the high-speed differential signal is open or short-circuited.
Fig. 7 illustrates an exemplary flow diagram of a method 700 for detecting high speed differential signals according to an embodiment of the disclosure. As shown in fig. 7, at step S702, the high-speed differential signal sent by the signal generator and the high-speed differential signal received by the signal receiver are compared to obtain an error code in the high-speed differential signal received by the signal receiver. In one embodiment, the high speed differential signal may be transmitted by a signal generator and received by a signal receiver. From the foregoing, the data form of the high-speed differential signal may be the number of bits. In one embodiment, the bit number of the high-speed differential signal sent by the signal generator is compared with the bit number of the high-speed differential signal received by the signal receiver, and the bit error in the high-speed differential signal received by the signal receiver is obtained according to the number of times of inconsistency of the comparison. Based on the obtained bit errors, at step S704, it is determined whether an open circuit or a short circuit occurs at both P/N ends of the high-speed differential signal according to the bit errors in the high-speed differential signal received by the signal receiver. Specifically, when the error code in the high-speed differential signal received by the signal receiver is greater than a preset error code value (for example, 30%), it is determined that the P/N ends of the high-speed differential signal are both in an open circuit or short circuit state.
Further, at step S706, a two-dimensional eye diagram is generated from the high-speed differential signal received by the signal receiver. In one embodiment, the data of each point in the two-dimensional matrix area corresponding to the high-speed differential signal received by the signal receiver may be compared with the data of the central point thereof, and the first error rate of each point in the two-dimensional matrix area may be calculated according to the number of times that the data of each point in the two-dimensional matrix area is inconsistent with the data of the central point thereof. The first error rate of each point in the two-dimensional matrix area forms a two-dimensional eye diagram. After obtaining the two-dimensional eye pattern, at step S708, statistics are performed on a first error rate of a preset region in the two-dimensional eye pattern. In some embodiments, the preset area may include an edge area of the two-dimensional eye pattern, a center area of the two-dimensional eye pattern, and an entire area of the two-dimensional eye pattern. Specifically, the above formulas (1) to (3) are used to respectively count the number of the first error rates corresponding to the point pairs in the edge region of the two-dimensional eye diagram, which are greater than a preset threshold, count the number of the first error rates corresponding to the point pairs in the center region of the two-dimensional eye diagram, which are non-zero, and count the sum of the first error rates corresponding to all the point pairs in all the regions of the two-dimensional eye diagram, so as to obtain corresponding first, second and third statistical results.
Finally, in step S710, it is determined whether only one path of the P/N terminals of the high-speed differential signal is open or short-circuited according to the statistical result. For example, when the first, second and third statistical results are all smaller than the corresponding threshold values, it is determined that the P/N terminals of the high-speed differential signal are all in an open circuit or short circuit state. And when at least one statistical result of the first statistical result, the second statistical result and the third statistical result is larger than the corresponding threshold value, determining that only one path of the P/N end of the high-speed differential signal is in an open circuit or short circuit state. The threshold value corresponding to each region may refer to the content described in fig. 4 to fig. 5, and is not described herein again.
From the above description in conjunction with the accompanying drawings, those skilled in the art will also appreciate that embodiments of the present disclosure may also be implemented by software programs. The present disclosure thus also provides a computer program product. The computer program product may be used to implement the method for detecting high speed differential signals described in conjunction with fig. 7 of the present disclosure.
It should be noted that while the operations of the disclosed methods are depicted in the drawings in a particular order, this does not require or imply that these operations must be performed in this particular order, or that all of the illustrated operations must be performed, to achieve desirable results. Rather, the steps depicted in the flowcharts may change the order of execution. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions.
It should be understood that when the claims of the present disclosure, and when the terms first, second, third, fourth, etc. are used in the specification and drawings, they are used only to distinguish one object from another, and not to describe a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the disclosure. As used in the specification and claims of this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this disclosure refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.
Although the embodiments of the present disclosure are described above, the descriptions are only examples for facilitating understanding of the present disclosure, and are not intended to limit the scope and application scenarios of the present disclosure. It will be understood by those skilled in the art of the present disclosure that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the disclosure is to be limited only by the appended claims.
Claims (10)
1. An apparatus for detecting a high-speed differential signal, wherein the high-speed differential signal is transmitted via a transmission cable, and the apparatus comprises:
a signal generator for connecting with one end of the transmission cable, for transmitting the high-speed differential signal;
the signal receiver is used for being connected with the other end of the transmission cable and receiving the high-speed differential signal;
an error code calculation unit connected to the signal generator and the signal receiver and configured to:
comparing the high-speed differential signal sent by the signal generator with the high-speed differential signal received by the signal receiver to obtain an error code in the high-speed differential signal received by the signal receiver;
determining whether the P/N ends of the high-speed differential signals are all in an open circuit or short circuit state according to the error codes in the high-speed differential signals received by the signal receiver;
an eye diagram calculation unit connected with the signal generator and the signal receiver and configured to:
generating a two-dimensional eye pattern according to the high-speed differential signal received by the signal receiver;
counting a first error rate of a preset area in the two-dimensional eye diagram; and
and determining whether only one path of the P/N ends of the high-speed differential signals is in an open circuit or short circuit state according to the statistical result.
2. The apparatus of claim 1, wherein in determining whether the P/N ends of the high-speed differential signal are both open or short according to the bit error in the high-speed differential signal received by the signal receiver, the bit error calculation unit is further configured to:
and determining that the P/N ends of the high-speed differential signals are in an open circuit or short circuit state in response to the fact that the error codes in the high-speed differential signals received by the signal receiver are larger than a preset error code value.
3. The apparatus of claim 1, wherein in generating a two-dimensional eye diagram from a high-speed differential signal received by the signal receiver, the eye diagram computation unit is further to:
comparing the data of each point in the two-dimensional matrix area corresponding to the high-speed differential signal received by the signal receiver with the data of the central point of the two-dimensional matrix area to determine whether the data of each point in the corresponding two-dimensional matrix area is consistent with the data of the central point of the two-dimensional matrix area;
and generating a two-dimensional eye diagram according to the comparison result.
4. The apparatus of claim 3, wherein in generating a two-dimensional eye diagram according to the alignment result, the eye diagram calculation unit is further configured to:
calculating a first error rate of each point in the corresponding two-dimensional matrix area according to the number of times that the data of each point in the corresponding two-dimensional matrix area is inconsistent with the data of the central point of the point; and
a two-dimensional eye diagram is generated based on the first bit error rate for each point within the corresponding two-dimensional matrix region.
5. The device of claim 1, wherein the preset areas in the two-dimensional eye pattern comprise a border area of the two-dimensional eye pattern, a center area of the two-dimensional eye pattern, and an entirety of the two-dimensional eye pattern, wherein the border area of the two-dimensional eye pattern and the center area of the two-dimensional eye pattern are determined via a size of the two-dimensional eye pattern.
6. The apparatus of claim 5, wherein in counting the first error rate of a preset region in the two-dimensional eye diagram, the eye diagram calculation unit is further configured to:
and respectively counting points in the edge area of the two-dimensional eye pattern, points in the central area of the two-dimensional eye pattern and first error rates corresponding to all points in the whole area of the two-dimensional eye pattern to obtain corresponding statistical results.
7. The apparatus of claim 6, wherein in respectively counting the first error rates of all corresponding points in the edge region of the two-dimensional eye pattern, the center region of the two-dimensional eye pattern, and the entire region of the two-dimensional eye pattern to obtain corresponding statistical results, the eye pattern calculation unit is further configured to:
counting the number of first error rates corresponding to the point in the edge area of the two-dimensional eye pattern, which are larger than a preset threshold value, so as to obtain a first statistical result;
counting the number of the point corresponding to the central area of the two-dimensional eye pattern, wherein the first error rate is nonzero, so as to obtain a second statistical result; and
and counting the sum of the first error rates corresponding to all points in the whole area of the two-dimensional eye pattern to obtain a third statistical result.
8. The apparatus of claim 7, wherein in determining whether only one of the P/N terminals of the high-speed differential signal is open or short according to the statistical result, the eye diagram calculating unit is further configured to:
responding to at least one statistical result of the first statistical result, the second statistical result and the third statistical result which is larger than a corresponding threshold value, and determining that only one path of the P/N end of the high-speed differential signal is in an open circuit or short circuit state; or
And determining that the high-speed differential signal P/N end has no open circuit or short circuit state in response to the first, second and third statistical results being smaller than the corresponding threshold values.
9. A method for detecting high speed differential signals, comprising:
comparing the high-speed differential signal sent by the signal generator with the high-speed differential signal received by the signal receiver to obtain an error code in the high-speed differential signal received by the signal receiver;
determining whether the P/N ends of the high-speed differential signals are all in an open circuit or short circuit state according to the error codes in the high-speed differential signals received by the signal receiver;
generating a two-dimensional eye pattern according to the high-speed differential signal received by the signal receiver;
counting a first error rate of a preset area in the two-dimensional eye diagram; and
and determining whether only one path of the P/N ends of the high-speed differential signals is in an open circuit or short circuit state according to the statistical result.
10. A computer readable storage medium comprising program instructions for detecting high speed differential signals, which when executed by one or more processors, cause the method of claim 9 to be implemented.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111597790.2A CN113992239B (en) | 2021-12-24 | 2021-12-24 | Device and method for detecting high-speed differential signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111597790.2A CN113992239B (en) | 2021-12-24 | 2021-12-24 | Device and method for detecting high-speed differential signal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113992239A CN113992239A (en) | 2022-01-28 |
| CN113992239B true CN113992239B (en) | 2022-03-18 |
Family
ID=79734279
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111597790.2A Active CN113992239B (en) | 2021-12-24 | 2021-12-24 | Device and method for detecting high-speed differential signal |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113992239B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115542136B (en) * | 2022-09-29 | 2024-09-10 | 苏州工业园区慧鱼科技有限公司 | FPGA-based cable testing method and device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106843349A (en) * | 2015-10-05 | 2017-06-13 | 恩智浦有限公司 | Differential driver circuit and the method for controlling differential driver circuit |
| CN107729280A (en) * | 2017-11-15 | 2018-02-23 | 无锡军安电子科技有限公司 | A kind of high-speed differential signal port Impedance and transmission line impedance uniformity control method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6307980B2 (en) * | 2014-03-31 | 2018-04-11 | 株式会社ソシオネクスト | Differential amplifier circuit and semiconductor integrated circuit |
-
2021
- 2021-12-24 CN CN202111597790.2A patent/CN113992239B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106843349A (en) * | 2015-10-05 | 2017-06-13 | 恩智浦有限公司 | Differential driver circuit and the method for controlling differential driver circuit |
| CN107729280A (en) * | 2017-11-15 | 2018-02-23 | 无锡军安电子科技有限公司 | A kind of high-speed differential signal port Impedance and transmission line impedance uniformity control method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113992239A (en) | 2022-01-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11946970B2 (en) | Systems, methods and devices for high-speed input/output margin testing | |
| TWI809570B (en) | Systems, methods, and devices for high-speed input/output margin testing | |
| US20130317796A1 (en) | Simulating the Transmission and Simultaneous Switching Output Noise of Signals in a Computer System | |
| CN113992239B (en) | Device and method for detecting high-speed differential signal | |
| US11940483B2 (en) | Systems, methods and devices for high-speed input/output margin testing | |
| CN113014339B (en) | Quality test method, device and equipment for PCIe external plug-in card receiving channel | |
| US6373262B1 (en) | Method and apparatus for testing a signal line | |
| JP2019096960A (en) | Transmission equipment and transmission method | |
| CN113986785A (en) | USB data transmission based method | |
| TW201337295A (en) | Chip and priented circuit board having receiver testing function | |
| CN212031622U (en) | HDMI cable testing arrangement | |
| US9960886B2 (en) | Noise detection device | |
| US8725925B2 (en) | Interface adapter between PCI express interface and HDMI interface and adapting method thereof | |
| CN114706718A (en) | PCIe signal integrity verification method, device, equipment and medium | |
| CN115291075A (en) | High-speed signal quality testing method and testing device | |
| CN113268390A (en) | Testing jig, system and method for mSATA interface | |
| CN114047460A (en) | Device and method for detecting high-speed differential signal | |
| US6925588B2 (en) | Methods and apparatus for testing data lines | |
| CN112485729A (en) | Method for detecting connection state of electric connector | |
| Zhou et al. | High-speed SFP+ signal integrity simulation and measurement | |
| US11953549B1 (en) | Detection system for SlimSAS slot and method thereof | |
| CN102299458B (en) | Peripheral component interconnection express (PCI Express) signal transmission structure and method thereof | |
| CN110704006A (en) | Multi-screen image display method and device, terminal equipment and storage medium | |
| US20130059464A1 (en) | Audio test cable | |
| US20180034568A1 (en) | Method and associated apparatus for performing cable diagnostics in a network system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |