CN113990830A

CN113990830A - Package structure and method for manufacturing package structure

Info

Publication number: CN113990830A
Application number: CN202111626246.6A
Authority: CN
Inventors: 刘召军; 吴涛; 张珂
Original assignee: Shenzhen Stan Technology Co Ltd
Current assignee: Shenzhen Stan Technology Co Ltd
Priority date: 2021-12-29
Filing date: 2021-12-29
Publication date: 2022-01-28
Anticipated expiration: 2041-12-29
Also published as: CN113990830B

Abstract

Embodiments of the present disclosure provide a package structure and a method for manufacturing the same. The packaging structure comprises: a first flip chip and a second flip chip. The first flip chip includes a plurality of first bond sites and at least one bump disposed on a first surface of the first flip chip. The second flip chip includes a plurality of second bond sites and at least one recess disposed on a second surface of the second flip chip. Wherein the at least one bump of the first flip-chip is jogged into the at least one recess of the second flip-chip, and the at least one of the first plurality of bond sites is bonded to the at least one of the second plurality of bond sites. The at least one first bond site and the at least one second bond site are both bumps.

Description

Package structure and method for manufacturing package structure

Technical Field

Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a package structure and a method for manufacturing the package structure.

Background

In the semiconductor field, there are generally three common ways to mount a chip on a circuit board or substrate to achieve a proper output of chip performance. One common approach is wire bonding: and the chip pins and the circuit are connected by adopting metal wires with good conductivity. Another common method is a pin bonding technique, also known as a Tape Automated Bonding (TAB) technique: and the copper foil is used for replacing a metal wire to be attached to the salient point of the chip pin. Yet another common approach is the flip-chip technique: instead of pins, a plurality of conductive metal bumps are arranged on the chip, connecting these metal bumps with the metal of the planar structure. This technique is called flip-chip technique because the bumps of the chip are connected face down during the connection process. And a chip to which the flip-chip technology is applied may be referred to as a flip chip.

Flip chip technology has many significant advantages over wire bonding and pin bonding technologies, such as superior electrical and thermal performance, high I/O pin count, reduced package size, etc. Therefore, the flip-chip technique is increasingly widely used.

Disclosure of Invention

Embodiments described herein provide a package structure and a method for manufacturing the package structure. In addition, the embodiment of the disclosure also provides a first flip chip, a second flip chip, a method for manufacturing the first flip chip and a method for manufacturing the second flip chip.

According to a first aspect of the present disclosure, a package structure is provided. The packaging structure comprises: a first flip chip and a second flip chip. The first flip chip includes a plurality of first bond sites disposed on a first surface of the first flip chip. The second flip chip includes a plurality of second bond sites disposed on a second surface of the second flip chip. Wherein at least one of the first plurality of bond sites is bonded to at least one of the second plurality of bond sites. The at least one first bond site and the at least one second bond site are both bumps.

In some embodiments of the present disclosure, the shape of the bump includes one or more of: spherical, columnar, or tapered in a direction away from the surface on which the bumps are located.

In some embodiments of the present disclosure, the first surface of the first flip chip is further provided with at least one bump. The second surface of the second flip chip is also provided with at least one groove. The at least one bump of the first flip chip is jogged into the at least one recess of the second flip chip.

In some embodiments of the present disclosure, the at least one bump of the first flip chip is configured to: such that the bump can be jogged into the at least one recess of the second flip chip and such that the at least one first bond site can contact the at least one second bond site.

In some embodiments of the present disclosure, a height of the at least one bump of the first flip chip is greater than a sum of a height of the first bond site and a height of the second bond site, and is less than or equal to a sum of a height of the first bond site and a height of the second bond site and a depth of the recess of the second flip chip.

In some embodiments of the present disclosure, the number of bumps of the first flip chip is less than or equal to the number of grooves of the second flip chip.

In some embodiments of the present disclosure, the at least one bump of the first flip chip is disposed at an edge region of the first flip chip. And a corresponding groove is arranged at the position corresponding to the at least one bulge on the second flip chip.

In some embodiments of the present disclosure, the first surface of the first flip chip is provided with one or more bumps on a periphery thereof, respectively. And corresponding grooves are arranged on the second surface of the second flip chip at positions corresponding to the one or more bulges.

In some embodiments of the present disclosure, a filler material is disposed between the first flip chip and the second flip chip.

According to a second aspect of the present disclosure, a method for manufacturing a package structure is provided. In the method, a plurality of first bond sites are formed on a first surface of a first flip-chip and a plurality of second bond sites are formed on a second surface of a second flip-chip. At least one of the first plurality of bond sites is then bonded to at least one of the second plurality of bond sites. Wherein the at least one first bond site and the at least one second bond site are both bumps.

In some embodiments of the disclosure, the method further comprises: forming at least one bump on a first surface of the first flip chip; forming at least one groove on the second surface of the second flip chip; and jogging the at least one bump of the first flip chip into the at least one groove of the second flip chip.

In some embodiments of the present disclosure, forming the at least one bump on the first surface of the first flip-chip comprises: forming the at least one bump of the first flip chip such that the bump can be jogged into the at least one recess of the second flip chip and such that the at least one first bond site can contact the at least one second bond site.

In some embodiments of the present disclosure, forming the at least one bump on the first surface of the first flip-chip comprises: the at least one bump is formed at an edge region of the first flip chip. Forming the at least one recess on the second surface of the second flip chip includes: a corresponding recess is formed in the second flip chip at a position corresponding to the at least one protrusion.

In some embodiments of the present disclosure, forming the at least one bump on the first surface of the first flip-chip comprises: one or more bumps are respectively formed on the periphery of the first surface of the first flip chip. Forming the at least one recess on the second surface of the second flip chip includes: corresponding recesses are formed in the second flip chip at positions corresponding to the one or more bumps.

In some embodiments of the present disclosure, forming a plurality of first bond sites on the first surface of the first flip-chip comprises: depositing a first dielectric layer on the first surface of the first flip chip; patterning the first dielectric layer to form at least one opening over the metal portion of the first surface; depositing a first metal layer within the at least one opening; and forming the first metal layer into at least one metal ball as a first bonding point by adopting a reflow process.

In some embodiments of the present disclosure, patterning the first dielectric layer further comprises: at least one protrusion is formed on the first surface.

In some embodiments of the present disclosure, forming a plurality of second bond sites on the second surface of the second flip-chip includes: depositing a second dielectric layer on the second surface of the second flip chip; patterning the second dielectric layer to form at least one opening over the metal portion of the second surface; depositing a second metal layer within the at least one opening; and forming the second metal layer into at least one metal ball as a second bonding point by adopting a reflow process.

In some embodiments of the present disclosure, patterning the second dielectric layer further comprises: at least one groove is formed on the second surface.

In some embodiments of the disclosure, the method further comprises: and injecting a filling material between the first flip chip and the second flip chip.

According to a third aspect of the present disclosure, there is provided a first flip chip for bonding with a second flip chip. The first flip chip includes: a plurality of first bond sites disposed on the first surface of the first flip-chip. Wherein at least one of the first plurality of bond sites is adapted to bond with at least one of the second plurality of bond sites disposed on the second surface of the second flip-chip. The at least one first bond site and the at least one second bond site are both bumps.

In some embodiments of the present disclosure, the first surface of the first flip chip is further provided with at least one bump. The at least one protrusion is for snapping into the at least one groove on the second surface of the second flip chip.

In some embodiments of the present disclosure, the at least one bump of the first flip chip is disposed at an edge region of the first flip chip.

In some embodiments of the present disclosure, the first surface of the first flip chip is provided with one or more bumps on a periphery thereof, respectively.

According to a fourth aspect of the present disclosure, a second flip chip is provided for bonding with a first flip chip. This second flip-chip includes: and a plurality of second bonding points disposed on the second surface of the second flip chip. Wherein at least one of the second plurality of bond sites is for bonding with at least one of the first plurality of bond sites disposed on the first surface of the first flip-chip. The at least one first bond site and the at least one second bond site are both bumps.

In some embodiments of the present disclosure, the second surface of the second flip chip is further provided with at least one groove. The at least one recess is for jogging to at least one bump on the first surface of the first flip chip.

In some embodiments of the present disclosure, the at least one recess of the second flip chip is disposed at an edge region of the second flip chip.

In some embodiments of the present disclosure, one or more grooves are respectively disposed on the periphery of the second surface of the second flip chip.

According to a fifth aspect of the present disclosure, a method for manufacturing a first flip chip is provided. The first flip chip is used for bonding with the second flip chip. In the method, a plurality of first bond sites is formed on a first surface of a first flip chip. Wherein at least one of the first plurality of bond sites is adapted to bond with at least one of the second plurality of bond sites disposed on the second surface of the second flip-chip. The at least one first bond site and the at least one second bond site are both bumps.

In some embodiments of the disclosure, the method further comprises: at least one bump is formed on the first surface of the first flip chip. The at least one protrusion is for snapping into the at least one groove on the second surface of the second flip chip.

In some embodiments of the present disclosure, forming at least one bump on the first surface of the first flip-chip comprises: at least one bump is formed at an edge region of the first flip chip.

In some embodiments of the present disclosure, forming at least one bump on the first surface of the first flip-chip comprises: one or more bumps are respectively formed on the periphery of the first surface of the first flip chip.

In some embodiments of the present disclosure, forming a plurality of first bond sites on the first surface of the first flip-chip and forming at least one bump on the first surface of the first flip-chip comprises: depositing a first dielectric layer on the first surface of the first flip chip; patterning the first dielectric layer to form at least one protrusion on the first surface and at least one opening over the metal portion of the first surface; depositing a first metal layer within the at least one opening; and forming the first metal layer into at least one metal ball as a first bonding point by adopting a reflow process.

According to a sixth aspect of the present disclosure, a method for manufacturing a second flip chip is provided. The second flip chip is for bonding with the first flip chip. In the method, a plurality of second bond sites are formed on a second surface of a second flip chip. Wherein at least one of the second plurality of bond sites is for bonding with at least one of the first plurality of bond sites disposed on the first surface of the first flip-chip. The at least one first bond site and the at least one second bond site are both bumps.

In some embodiments of the disclosure, the method further comprises: at least one recess is formed on the second surface of the second flip chip. The at least one recess is for jogging to at least one bump on the first surface of the first flip chip.

In some embodiments of the present disclosure, forming at least one groove on the second surface of the second flip chip comprises: at least one groove is formed in an edge region of the second flip chip.

In some embodiments of the present disclosure, forming at least one groove on the second surface of the second flip chip comprises: one or more grooves are respectively formed on the periphery of the second surface of the second flip chip.

In some embodiments of the present disclosure, forming a plurality of second bond sites on the second surface of the second flip-chip and forming at least one recess on the second surface of the second flip-chip comprises: depositing a second dielectric layer on the second surface of the second flip chip; patterning the second dielectric layer to form at least one recess on the second surface and at least one opening over the metal portion of the second surface; depositing a second metal layer within the at least one opening; and forming the second metal layer into at least one metal ball as a second bonding point by adopting a reflow process.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, it being understood that the drawings described below relate only to some embodiments of the present disclosure, and not to limit the present disclosure, wherein:

FIG. 1 is a cross-sectional view of a package structure including two flip chips;

FIG. 2 is a cross-sectional view of a package structure including two flip chips according to an embodiment of the present disclosure;

FIG. 3 is a cross-sectional view of a package structure including two flip chips according to yet another embodiment of the present disclosure;

FIG. 4 is a cross-sectional view of a package structure including two flip chips according to yet another embodiment of the present disclosure;

fig. 5 is a schematic diagram of a flip chip according to an embodiment of the present disclosure;

fig. 6 is a schematic diagram of an IC driving chip having a bump structure according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a photonic chip with a groove structure according to an embodiment of the present disclosure; and

fig. 8 is a flow chart of a method for manufacturing the package structure shown in fig. 2 according to an embodiment of the present disclosure.

In the drawings, the same reference numerals in the last two digits may correspond to the same elements. It should be noted that the elements in the figures are schematic and not drawn to scale.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below in detail and completely with reference to the accompanying drawings. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are also within the scope of protection of the disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate components.

Spatially relative terms, such as "upper," "lower," "left," "right," "top," "bottom," and the like, may be used herein for ease of description to describe one element or element's spatial relationship to another element or element as illustrated in the figures. For example, the terms "on … …," "over … …," "over … …," "on … …," "above," "positioned on … …," or "positioned on top of … …," etc., mean that a first element, such as a first structure, is present on a second element, such as a second structure, where there may or may not be intermediate elements between the first and second elements. The term "contact" means connecting a first element, such as a first structure, and a second element, such as a second structure, with or without the other element at the interface of the two elements. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above … …" can include both an orientation of "above … …" and "below … …". The device may also be oriented 90 degrees or at other orientations and the spatially relative descriptors used herein interpreted accordingly.

The current common flip-chip process is to combine a spherical metal or a cylindrical metal with a metal of a planar structure, which are bonded (also referred to as soldering, bonding, etc.) through certain bonding conditions (such as temperature, pressure, time, etc.). Fig. 1 shows a schematic view of two

flip chips

101 and 111 being bonded together. The first flip chip 101 and the second flip chip 111 form a package structure as shown in fig. 1. The first flip-chip 101 has a plurality of bump-shaped (metal ball) bonding sites 102 (also referred to as bonding pads) on the first surface 103, and the second flip-chip 111 has a plurality of planar (metal in a planar structure) bonding sites 112 on the second surface 113. The bonding sites 102 of the first flip-chip 101 and the bonding sites 112 of the second flip-chip 111 are correspondingly bonded together according to functional requirements.

In the package structure shown in fig. 1, if the height of the metal balls on the first flip chip is not high enough, the bonding force of the bonding is not enough, and a cold joint is formed. However, as the size of the flip chip becomes smaller and smaller with the development of semiconductor technology, it becomes more difficult to fabricate higher metal balls. To reduce the probability of cold joint, it may be considered to increase the bonding pressure, but this brings another problem: increasing the bonding pressure results in a reduction in the height of the metal ball; since the height h of the space between the first flip chip 101 and the second flip chip 111 becomes smaller due to the reduction of the height of the metal balls, it may be difficult to fill glue between the first flip chip 101 and the second flip chip 111 for protection.

Accordingly, the present disclosure proposes a package structure as shown in fig. 2. In this embodiment, the first flip chip 201 and the second flip chip 211 form a package structure as shown in fig. 2. Wherein the first flip-chip 201 has a plurality of bump-like (metal ball-like) first bond sites 202 on the first surface 203 and the second flip-chip 211 has a plurality of bump-like (metal ball-like) second bond sites 212 on the second surface 213. The first bonding sites 202 of the first flip chip 201 and the second bonding sites 212 of the second flip chip 211 are correspondingly bonded together according to functional requirements. In one example, one first bond site 202 of the first flip-chip 201 and one second bond site 212 of the second flip-chip 211 are bonded together. In another example, the plurality of first bond sites 202 of the first flip-chip 201 and the plurality of second bond sites 212 of the second flip-chip 211 are correspondingly bonded together.

The shape of the bump may be one of: spherical, columnar, or gradually converging in a direction away from the surface on which the bumps are located. For example, in the example of fig. 2, the shape of the first bond site 202 may be a shape that gradually converges in a direction away from the first surface 203 (e.g., downward). The shape of the second bond site 212 may be a shape that gradually converges in a direction away from the second surface 213 (e.g., upward). In some embodiments of the present disclosure, the shape of the first bond site 202 may be the same as the shape of the second bond site 212. For example, the first bond site 202 and the second bond site 212 are both ball-shaped. In other embodiments of the present disclosure, the shape of the first bond site 202 may be different from the shape of the second bond site 212. For example, the first bond site 202 is ball-shaped, and the second bond site 212 is post-shaped.

In an embodiment of the present disclosure, the material of the bump may be a metal material, such as indium, tin, or an alloy.

In the package structure shown in fig. 2, the height h of the space between the first flip chip 201 and the second flip chip 211 is significantly larger than that in the example shown in fig. 1, so that it is beneficial to fill glue between the first flip chip 201 and the second flip chip 211 for protection.

Since the first flip chip 201 and the second flip chip 211 both use bump-like bonding points, the requirement for the degree of alignment between the first flip chip 201 and the second flip chip 211 becomes high during bonding. It may be desirable for the most protruding point on the first bond site 202 to be aligned with the corresponding most protruding point on the second bond site 212. In this regard, embodiments of the present disclosure also provide a package structure as shown in fig. 3. In the embodiment shown in fig. 3, the first flip-chip 301 is further provided with at least one bump 304 on the first surface 303 and at least one recess 314 on the second surface 313 of the second flip-chip 311. The bumps 304 of the first flip-chip 301 may be jogged into the recesses 314 of the second flip-chip 311. By arranging the position of the bump 304 on the first surface 303 and the position of the recess 314 on the second surface 313, the relative positions of the first flip chip 301 and the second flip chip 311 can be controlled such that the most protruding point on the first bond site 302 is aligned with the corresponding most protruding point on the second bond site 312. In case the most protruding point on the first bond site 302 is aligned with the corresponding most protruding point on the second bond site 312, the height h of the space between the first flip chip 301 and the second flip chip 311 can be made as high as possible, thereby facilitating the filling of glue between the two

flip chips

301 and 311.

Although only one bump 304 and one recess 314 are shown in fig. 3, it will be understood by those skilled in the art that two or more bumps 304 may be disposed on the first surface 303 of the first flip-chip 301 and two or more recesses 314 may be disposed on the second surface 313 of the second flip-chip 311. For example, fig. 4 shows a case where two bumps 304 are provided on the first surface 303 of the first flip chip 301 and two grooves 314 are provided on the second surface 313 of the second flip chip 311.

In some embodiments, the bumps 304 of the first flip-chip 301 are arranged to: so that the bumps 304 can be jogged into the grooves 314 of the second flip chip 311. The shape of the protrusion 304 should fit or match the recess 314. For example, the diameter or width of the protrusion 304 should be less than or equal to the diameter or width of the recess 314. The diameter or width of the bumps 304 should not be excessively smaller than the diameter or width of the recesses 314 so that the bumps 304 cannot control the relative displacement between the first flip-chip 301 and the second flip-chip 311 when placed into the recesses 314. In addition, the height of the protrusion 304 should be high enough to extend into the recess 314. However, the height of the bump 304 should not be so high that the first bond site 302 does not contact the second bond site 312. Because the first bond site 302 and the second bond site 312 may not be able to be bonded together if the first bond site 302 does not contact the second bond site 312. In addition, when determining the height of the bump 304, the deformation of the first bonding point and the second bonding point after flip-chip bonding should be considered.

In some embodiments, the height H of the bumps 304 of the first flip-chip 301 is greater than the sum of the height H1 of the first bond sites 302 and the height H2 of the second bond sites 312 and is less than or equal to the sum of the height H1 of the first bond sites 302 and the height H2 of the second bond sites 312 and the depth d of the recess 314 of the second flip-chip 311. Namely, (H1+ H2) < H < (H1+ H2+ d). In one example, if the depth d of the recess 314 of the second flip chip 311 is equal to 2 μm and the height H1 of the first bond site 302 and the height H2 of the second bond site 312 are both 1 μm, the height H of the bump 304 of the first flip chip 301 is greater than 2 μm and less than 4 μm.

In one example, the sum of the height h1 of the first bond site 302 and the height h2 of the second bond site 312 is at least greater than 1 μm. In this way, the flow of glue between the first flip chip 301 and the second flip chip 311 is facilitated, thereby facilitating the filling of glue in the space between the first flip chip 301 and the second flip chip 311.

In some embodiments, the number of bumps 304 of the first flip-chip 301 may be less than or equal to the number of recesses 314 of the second flip-chip 311. As long as the bumps 304 of the first flip-chip 301 can be jogged into the recesses 314 of the second flip-chip 311. If the number of bumps 304 of the first flip-chip 301 is larger than the number of recesses 314 of the second flip-chip 311, one or more bumps 304 of the first flip-chip 301 will not be jogged into the recesses 314 of the second flip-chip 311, resulting in a height h of the space between the first flip-chip 301 and the second flip-chip 311 that is too large for the first bond site 302 to contact the second bond site 312.

In some embodiments, the bumps 304 of the first flip-chip 301 may be disposed at an edge region of the first surface 303 of the first flip-chip 301, and the second flip-chip 311 may be provided with corresponding grooves 314 at positions corresponding to the bumps 304. In this context, since the first bond site 302 is generally located in a central region of the first surface 303, an edge region of the first surface 303 may include a region of the first surface 303 other than a region where the first bond site 302 is located. In one example, the size of the first surface 303 of the first flip chip 301 is the same as the size of the second surface 313 of the second flip chip 311, the bumps 304 of the first flip chip 301 may be disposed at an edge region of the first surface 303 of the first flip chip 301, and the grooves 314 of the second flip chip 311 may be disposed at an edge region of the second flip chip 311. In another example, the first surface 303 of the first flip chip 301 is smaller than the second surface 313 of the second flip chip 311, the bumps 304 of the first flip chip 301 may be disposed at an edge region of the first surface 303 of the first flip chip 301, and the corresponding grooves 314 may be disposed at positions on the second flip chip 311 corresponding to the bumps 304. In this case, the recess 314 may be disposed at a middle region of the second flip chip 311.

However, if the first surface 303 of the first flip chip 301 is larger than the second surface 313 of the second flip chip 311, the bumps 304 of the first flip chip 301 may not be disposed at the edge region of the first surface 303 of the first flip chip 301. In this case, a groove 314 may be provided at an edge region of the second flip chip 311, and a corresponding bump 304 may be provided on the first flip chip 301 at a position corresponding to the groove 314.

In some embodiments, one or more bumps 304 may be disposed on each side of the first surface 303 of the first flip-chip 301, and corresponding grooves 314 may be disposed on the second surface 313 of the second flip-chip 311 at positions corresponding to the bumps 304. Fig. 5 shows a schematic view of the first flip-chip 301 having three bumps 304 provided on each side of the first surface 303.

Since the bumps 304 of the first flip-chip 301 are jogged into the grooves of the second flip-chip 311, the relative positions of the first flip-chip 301 and the second flip-chip 311 are fixed, and the relative displacement of the first flip-chip 301 and the second flip-chip 311 can be prevented.

Further, a filling material, such as a filling glue, may be filled between the first flip chip 301 and the second flip chip 311. So that the first flip chip 301 and the second flip chip 311 can be more stably bonded together.

In some embodiments, the first flip chip 301 may be an IC driver chip and the second flip chip 311 may be an optical chip.

Fig. 6 is a schematic diagram of an IC driving chip having a bump structure. In the example of fig. 6, the IC driving chip includes: a driver circuit layer 631, a metal electrode layer 632, a dielectric layer (e.g., insulating layer, passivation layer) 633, and metal balls 635. Wherein bumps 604 are formed in dielectric layer 633.

FIG. 7 is a schematic diagram of a photonic chip with a groove structure. In the example of fig. 7, the optical chip includes: a substrate 741, an N-type semiconductor layer (e.g., N GaN) 742, a metal layer 743, a dielectric layer (e.g., insulating layer, passivation layer) 744, a quantum well 745, a P-type semiconductor layer (e.g., P GaN) 746, a current diffusion layer 747, a metal electrode layer 748, and metal balls 749. Wherein recess 714 is formed in dielectric layer 744.

Fig. 8 illustrates a flow chart of a method for manufacturing the package structure as shown in fig. 2, according to an embodiment of the present disclosure.

At block S802 of fig. 8, a plurality of first bond sites 202 are formed on the first surface 203 of the first flip-chip 201. The first surface 203 of the first flip chip 201 may have a plurality of metal portions separated from each other as input/output terminals of the first flip chip. The plurality of first bond sites 202 are formed over the plurality of metal portions of the first surface 203.

In one example, the first bond site 202 may be formed using the following steps: depositing a first dielectric layer on the first surface of the first flip chip; patterning the first dielectric layer to form at least one opening over the metal portion of the first surface; depositing a first metal layer within the at least one opening; and forming the first metal layer into at least one metal ball as a first bonding point by adopting a reflow process.

At block S804, a plurality of second bond sites 212 is formed on the second surface 213 of the second flip chip 211. The second surface 213 of the second flip chip 211 may have a plurality of metal portions separated from each other as input/output terminals of the second flip chip. The plurality of second bond sites 212 is formed over the plurality of metal portions of the second surface 213.

In one example, the following steps may be taken to form second bond site 212: depositing a second dielectric layer on the second surface of the second flip chip; patterning the second dielectric layer to form at least one opening over the metal portion of the second surface; depositing a second metal layer within the at least one opening; and forming the second metal layer into at least one metal ball as a second bonding point by adopting a reflow process.

Those skilled in the art will appreciate that the operations performed at blocks S802 and S804 may be performed in parallel, or the operations at block S804 may be performed first, followed by the operations at block S802.

At block S806, at least one first bond site of the first plurality of bond sites is bonded to at least one second bond site of the second plurality of bond sites. Wherein the at least one first bond site and the at least one second bond site are both bumps. As described above, the shape of the bump may be one of: spherical, columnar, or gradually converging in a direction away from the surface on which the bumps are located. In this context, the bumps may be referred to as "metal balls," but the shape of the "metal balls" is not necessarily an idealized sphere.

As described above, in the example shown in fig. 3 or 4, the first surface 303 of the first flip chip 301 may be further provided with at least one bump 304, and the second surface 313 of the second flip chip 311 may be further provided with at least one groove 314. The following illustrates how a plurality of first bond sites and at least one bump are formed on the first surface of the first flip-chip and how a plurality of second bond sites and at least one recess are formed on the second surface of the second flip-chip.

In some embodiments, the following steps may be employed to form a plurality of first bond sites and at least one bump on the first surface of the first flip-chip: depositing a first dielectric layer on the first surface of the first flip chip; patterning the first dielectric layer to form at least one protrusion on the first surface and at least one opening over the metal portion of the first surface; depositing a first metal layer within the at least one opening; and forming the first metal layer into at least one metal ball as a first bonding point by adopting a reflow process.

In some embodiments, the following steps may be employed to form a plurality of second bond sites and at least one recess on the second surface of the second flip chip: depositing a second dielectric layer on the second surface of the second flip chip; patterning the second dielectric layer to form at least one recess on the second surface and at least one opening over the metal portion of the second surface; depositing a second metal layer within the at least one opening; and forming the second metal layer into at least one metal ball as a second bonding point by adopting a reflow process.

How the plurality of first bond sites and the at least one bump are formed on the first surface of the first flip-chip is further described below with reference to fig. 6. As described above, in the example of fig. 6, the first flip chip may be an IC driver chip. In some embodiments, a thick dielectric layer 633 (e.g., an insulating layer, a passivation layer) can be deposited on the driving circuit layer 631 and the metal electrode layer 632 of the IC driving chip (e.g., a metal pad of the IC driving chip). Here, the IC driving chip may be a wafer on which tape-out has been normally completed. Then, the metal electrode layer 632 is exposed by photolithography and etching to form an opening, and a protrusion structure is prepared. The protruding structures may be located around the IC driving chip. The shape, size and number of the protruding structures are matched with those of the groove structures of the second flip chip. And then, photoetching is carried out on the IC driving chip so as to deposit a metal layer on the metal bonding pad. The role of this metal layer is to form metal balls 635 after reflow to enable bonding with the metal balls on the second flip chip when flipped.

The thickness of the metal layer is typically in the order of μm. The material of the metal layer is typically a low melting point metal, including but not limited to: indium and tin or alloys to facilitate reflow into balls at lower temperatures. By controlling the temperature, the metal becomes liquid after melting. Since liquids have surface tension, the tension affects the liquid, changing the general tendency of the liquid shape to the smallest surface area, while in all shapes with the same volume, the surface area of the sphere is the smallest, and the metal layer becomes the metal sphere 635.

How the plurality of second bonding sites and the at least one recess are formed on the second surface of the second flip chip is further described below with reference to fig. 7. As described above, in the example of fig. 7, the second flip chip may be an optical chip. The optical chip may be, for example, an LED epitaxial wafer. The LED epitaxial wafer may include a substrate (e.g., a sapphire substrate, a silicon substrate, or a silicon carbide substrate) 741, an N-type semiconductor layer (e.g., N GaN) 742, a quantum well 745, a P-type semiconductor layer (e.g., P GaN).

An etch mask layer may be deposited on the surface of the epitaxial wafer. The etch mask layer includes but is not limited to: resist materials such as photoresist, metal, insulating layer, etc., or combinations thereof.

Then, the N-GaN layer 742 is etched to form a mesa. The shape of the table top can be square, round and other different shapes.

Then, a passivation layer is deposited on the surface of the structure, and an opening is formed on the passivation layer to reach the surface of the N-GaN layer 742. The protective layer includes, but is not limited to: and a protective film layer of silicon oxide, silicon nitride or aluminum oxide.

Thereafter, a current diffusion layer 747 is formed on the mesa by a photolithography lift-off method. In this step, the current spreading may be formed by photolithographic evaporation of multiple layers of metal or semiconductor oxides. The material of the metal may be one or more metals of titanium, aluminum, gold, chromium, nickel, platinum, and the like. The semiconducting oxide may include, but is not limited to, ITO, ZnO, and the like.

Then, a metal electrode layer 748 is formed on the current spreading layer 747 by a photolithography lift-off method. The material of the metal electrode layer 748 may be one or more metals of titanium, aluminum, gold, chromium, nickel, platinum, and the like.

Then, a dielectric layer (e.g., passivation layer, insulating layer) is deposited to protect the metal electrode from the external air. The dielectric layers include, but are not limited to: an insulating film layer of silicon oxide, silicon nitride, aluminum oxide, or the like.

The metal electrode layer 748 is exposed by opening holes by etching and the groove structure 714 is prepared at the same time. The groove structures 714 may be located around the periphery of the optical chip. The shape, size and number of the grooves can be matched with the protruding structures of the IC driving chip. The depth of the groove can be determined according to the size of the metal ball after reflow and the deformation size of the metal ball after flip-chip bonding, and meanwhile, the flowability of glue filling is also considered.

Thereafter, a metal layer is photolithographically deposited over the metal electrode layer 748. The thickness of the metal layer is typically in the order of μm. The material of the metal layer is typically a low melting point metal, including but not limited to: indium and tin or alloys to facilitate reflow into balls at lower temperatures.

By controlling the temperature, the metal layer reflows to form metal balls 749.

According to the embodiment of the disclosure, the bump-shaped bonding points are prepared on the two flip chips to improve the space gap between the two flip chips, so that the poor bonding after flip bonding and the filling protection effect of glue can be improved. In addition, the convex-concave structures on the two flip chips are beneficial to reducing the relative offset when the two flip chips are bonded, so that the alignment precision of flip bonding is improved, and the reliability of flip bonding is integrally enhanced.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus and methods according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when reference is made to the singular, it is generally intended to include the plural of the corresponding term. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "include" and "or" should be construed as inclusive unless such an interpretation is explicitly prohibited herein. Where the term "example" is used herein, particularly when it comes after a set of terms, it is merely exemplary and illustrative and should not be considered exclusive or extensive.

Further aspects and ranges of adaptability will become apparent from the description provided herein. It should be understood that various aspects of the present application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

Several embodiments of the present disclosure have been described in detail above, but it is apparent that various modifications and variations can be made to the embodiments of the present disclosure by those skilled in the art without departing from the spirit and scope of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A package structure, comprising:

a first flip-chip comprising a plurality of first bond sites and at least one bump disposed on a first surface of the first flip-chip; and

a second flip-chip comprising a plurality of second bond sites and at least one recess disposed on a second surface of the second flip-chip;

wherein the at least one bump of the first flip-chip is jogged into the at least one recess of the second flip-chip, at least one of the first plurality of bond sites is bonded to at least one of the second plurality of bond sites, and both the at least one first bond site and the at least one second bond site are bumps.

2. The package structure of claim 1, wherein the shape of the bump comprises one or more of: spherical, columnar, or gradually converging in a direction away from the surface on which the bumps are located.

3. The package structure of claim 1, wherein the at least one bump of the first flip chip is configured to: enabling the bump to be jogged into the at least one recess of the second flip chip and enabling the at least one first bond site to contact the at least one second bond site.

4. The package structure of claim 1, wherein a height of the at least one bump of the first flip chip is greater than a sum of a height of the first bond site and a height of the second bond site and less than or equal to a sum of a height of the first bond site and a height of the second bond site and a depth of the recess of the second flip chip.

5. The package structure of claim 1, wherein the number of bumps of the first flip chip is less than or equal to the number of recesses of the second flip chip.

6. The package structure of claim 1, wherein the at least one bump of the first flip chip is disposed at an edge region of the first flip chip, and a corresponding recess is disposed on the second flip chip at a location corresponding to the at least one bump.

7. The package structure of claim 1, wherein one or more bumps are disposed on a periphery of the first surface of the first flip chip, and corresponding grooves are disposed on the second surface of the second flip chip at positions corresponding to the one or more bumps.

8. The package structure of any one of claims 1 to 7, wherein a filler material is disposed between the first flip chip and the second flip chip.

9. A method for fabricating a package structure, comprising:

forming a plurality of first bond sites and at least one bump on a first surface of a first flip chip;

forming a plurality of second bonding points and at least one groove on a second surface of the second flip chip;

jogging the at least one bump of the first flip-chip into the at least one recess of the second flip-chip; and

bonding at least one of the first plurality of bond sites to at least one of the second plurality of bond sites;

wherein the at least one first bond site and the at least one second bond site are both bumps.

10. The method according to claim 9, wherein the method is further used for manufacturing a package structure according to any of claims 2 to 7.

11. The method of claim 9 or 10, wherein forming the plurality of first bond sites and the at least one bump on the first surface of the first flip-chip comprises:

depositing a first dielectric layer on the first surface of the first flip chip;

patterning the first dielectric layer to form at least one opening over a metal portion of the first surface and to form the at least one protrusion on the first surface;

depositing a first metal layer within the at least one opening; and

and forming the first metal layer into at least one metal ball serving as the first bonding point by adopting a reflow process.

12. The method of claim 9 or 10, wherein forming the plurality of second bond sites and the at least one recess on the second surface of the second flip-chip comprises:

depositing a second dielectric layer on the second surface of the second flip chip;

patterning the second dielectric layer to form at least one opening over the metal portion of the second surface and to form the at least one recess on the second surface;

depositing a second metal layer within the at least one opening; and

and forming the second metal layer into at least one metal ball serving as the second bonding point by adopting a reflow process.

13. The method of claim 9 or 10, further comprising:

and injecting a filling material between the first flip chip and the second flip chip.

14. A first flip chip for bonding with a second flip chip, the first flip chip comprising:

a plurality of first bond sites and at least one bump disposed on a first surface of the first flip-chip;

wherein the at least one protrusion is adapted to be jogged into at least one groove on the second surface of the second flip-chip, at least one of the first plurality of bond pads is adapted to be bonded with at least one of a second plurality of bond pads disposed on the second surface of the second flip-chip, and both the at least one first bond pad and the at least one second bond pad are bumps.

15. The first flip-chip of claim 14, wherein the at least one bump of the first flip-chip is disposed at an edge region of the first flip-chip; or

One or more bumps are disposed on a periphery of the first surface of the first flip chip.

16. A second flip chip for bonding with a first flip chip, the second flip chip comprising:

a plurality of second bond sites and at least one recess disposed on a second surface of the second flip chip;

wherein the at least one recess is adapted to be jogged to at least one bump on the first surface of the first flip chip, at least one of the second plurality of bond sites is adapted to be bonded to at least one of the first plurality of bond sites disposed on the first surface of the first flip chip, and both the at least one first bond site and the at least one second bond site are bumps.

17. The second flip-chip of claim 16, wherein the at least one recess of the second flip-chip is disposed at an edge region of the second flip-chip; or

One or more grooves are arranged on the periphery of the second surface of the second flip chip.