CN113990253A

CN113990253A - Driving method of display panel

Info

Publication number: CN113990253A
Application number: CN202111411005.XA
Authority: CN
Inventors: 李慧慧; 毛健; 尹朋飞
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2021-11-25
Filing date: 2021-11-25
Publication date: 2022-01-28
Anticipated expiration: 2041-11-25
Also published as: CN113990253B

Abstract

The disclosure relates to a driving method of a display panel, and relates to the technical field of display. The driving method includes: selecting a pixel circuit as a target pixel circuit, and determining the correction quantity of each row of pixel circuits according to the voltage change of a reset line caused by the voltage change of a data line connected with the target pixel circuit, wherein the correction quantity of the ith row of pixel circuits is the ith correction quantity; in the display stage of the nth frame, inputting a data voltage to the pixel circuit through the data line, and inputting a reference voltage to the pixel circuit through the reset line; the data voltage of any pixel circuit in the ith row of pixel circuits is the sum of the reference data voltage and the ith correction quantity, and the correction quantity is smaller than the reference data voltage; in the black insertion stage of the nth frame, the data voltage of the pixel circuit is set to be zero through the data line; n is a positive integer greater than 1 and not greater than N, i is a positive integer not greater than N, and N is the number of rows in the pixel circuit.

Description

Driving method of display panel

Technical Field

The disclosure relates to the technical field of display, and particularly relates to a driving method of a display panel.

Background

At present, a display panel has become an essential component in electronic devices such as mobile phones, computers, televisions, and the like, wherein an organic electroluminescent display panel has been widely used due to its advantages such as high brightness and contrast, but when displaying a picture, an image sticking is likely to occur in the existing organic electroluminescent display panel, and the picture stability needs to be improved.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present disclosure is directed to overcome the above-mentioned deficiencies in the prior art, and to provide a driving method of a display panel, which can improve the display effect.

According to an aspect of the present disclosure, there is provided a driving method of a display panel including a plurality of pixel circuits, a data line, and a reset line distributed in an array; the pixel circuit includes a driving transistor; the data lines and the reset lines extend along the column direction and are distributed at intervals along the row direction; any one of the pixel circuits is connected with one of the data lines through a control end of a driving transistor of the pixel circuit, and is connected with the reset line through a second end of the driving transistor; the pixel circuits in the same column are connected with the same data line and the same reset line;

the driving method includes:

selecting one pixel circuit as a target pixel circuit, and determining the correction quantity of the pixel circuit of each row according to the voltage change of a reset wire caused by the voltage change of a data wire connected with the target pixel circuit, wherein the correction quantity of the pixel circuit of the ith row is the ith correction quantity;

inputting a data voltage to the pixel circuit through the data line and inputting a reference voltage to the pixel circuit through the reset line in a display stage of an nth frame; a data voltage of any one of the pixel circuits in an ith row of the pixel circuits is a sum of a reference data voltage and the ith correction amount, the correction amount being smaller than the reference data voltage;

in the black insertion stage of the nth frame, setting the data voltage of the pixel circuit to be zero through the data line;

n is a positive integer greater than 1 and not greater than N, i is a positive integer not greater than N, and N is the number of rows of the pixel circuit.

In an exemplary embodiment of the present disclosure, a correction amount of the pixel circuit is determined for each row according to a voltage change of a reset line caused by a voltage change of a data line to which the target pixel circuit is connected; the method comprises the following steps:

inputting a detection data voltage to a data line connected to the target pixel circuit, and inputting a detection reference voltage to the reset line;

detecting a variation of a detection reference voltage of the reset line when the detection data voltage is set to zero;

and determining the correction amount of the pixel circuit in each row according to the variation.

In an exemplary embodiment of the present disclosure, the correction amount of the pixel circuit is equal for each row.

In an exemplary embodiment of the present disclosure, the correction amount and the change amount satisfy the following relationship:

VT＝KΔV；

VT is the correction amount, Δ V is the variation, and K is a positive real number.

In an exemplary embodiment of the present disclosure, the correction amounts of the pixel circuits of different rows are different.

In an exemplary embodiment of the present disclosure, the i-1 th correction amount is larger than the i-th correction amount.

In an exemplary embodiment of the present disclosure, the nth correction amount is zero.

In an exemplary embodiment of the present disclosure, the j-th correction amount and the change amount satisfy the following relationship:

VT1＝KΔV；

VTj＝(K(N-j)/N)ΔV；

VT1 is a first correction amount, VTj is a jth correction amount, Δ V is the variation, j is a positive integer greater than 1 and not greater than N, and K is a positive real number.

In an exemplary embodiment of the present disclosure, the j-th correction amount and the 1 st correction amount satisfy the following relationship:

VT1＝KΔV+b；

VTj＝(K(N-j)/N)ΔV+b；

VT1 is a first correction amount, VTj is a jth correction amount, Δ V is the variation, j is a positive integer greater than 1 and not greater than N, K is a positive real number, and b is a constant.

In an exemplary embodiment of the present disclosure, in a display phase of an nth frame, a data voltage is input to the pixel circuit through the data line, and a reference voltage is input to the pixel circuit through the reset line; the method comprises the following steps:

scanning each row of the pixel circuits row by row, and respectively inputting a data voltage to each pixel circuit in the ith row through each data line when the pixel circuits in the ith row are scanned; and a reference voltage is input to each of the i-th row of pixel circuits to the reset lines, respectively.

In an exemplary embodiment of the present disclosure, the pixel circuit includes:

a storage capacitor having a first pole and a second pole, the second pole for connection to a light emitting device;

the control end of the driving transistor is connected with the first pole of the storage capacitor, the first end of the driving transistor is used for receiving a first power supply signal, and the second end of the driving transistor is connected with the second pole of the storage capacitor;

the control end of the first transistor is used for receiving scanning signals, the first end of the first transistor is connected with a data line, and the second end of the first transistor is connected with the control end of the driving transistor;

a control end of the second transistor is used for receiving a scanning signal, a first end of the second transistor is connected with a reset wire, and a second end of the second transistor is connected with a second end of the driving transistor;

scanning each row of the pixel circuits line by line; the method comprises the following steps: .

The scanning signal is input to the first transistor and the second transistor of the pixel circuit for each row.

According to the driving method, a display stage and a black insertion stage can be divided from one frame of picture, the data voltage and the reference voltage are transmitted through the data line and the reset line in the display stage to realize image display, and the data voltage is set to be zero in the black insertion stage, so that the black insertion function is realized, the display time length is shortened, and the ghost phenomenon caused by visual persistence is weakened. Meanwhile, through the detection of the voltage change of the data wire and the voltage change of the reset wire, the variable quantity reflecting the influence of the coupling action of the data wire and the reset wire on the voltage of the reset wire is determined, and the correction quantity of each row of pixel circuits is determined based on the variable quantity; the coupling action of the data line and the reset line can cause the reference voltage to be suddenly pulled high, the reference voltage is caused to shake, the voltage difference between the data voltage and the reference voltage is different from the design value, and the data voltage of the nth frame is the sum of the reference data voltage and the correction quantity, namely the correction quantity is superposed in the data voltage, so that the deviation of the voltage difference between the data voltage and the reference voltage caused by the reference voltage and the design value can be reduced, and the display effect is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 is a schematic diagram of a pixel circuit according to an embodiment of a driving method of the disclosure.

Fig. 2 is a schematic diagram of an embodiment of the driving method of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and are not limiting on the number of their objects.

A transistor is an element including at least three terminals, i.e., a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. The channel region is a region through which current mainly flows.

The first terminal may be a drain electrode and the second terminal may be a source electrode, or the first terminal may be a source electrode and the second terminal may be a drain electrode. In the case of using transistors of opposite polarities, or in the case of changing the direction of current flow during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged with each other.

The row direction and the column direction in this document refer to two mutually intersecting directions, for example: the row direction may be the lateral direction in the drawing, and the column direction may be the longitudinal direction in the drawing, which are perpendicular to each other. However, this should not be seen as a limitation of the row direction and the column direction, the row direction not necessarily referring to the horizontal direction, nor the column direction necessarily referring to the vertical direction. It will be appreciated by those skilled in the art that the actual orientation of the row and column directions may change if the display panel changes position, such as by rotation.

The embodiment of the present disclosure provides a driving method of a display panel, as shown in fig. 1 and 2, the display panel may include a plurality of pixel circuits, a data line DAL and a reset line REL distributed in an array; the pixel circuit includes a driving transistor DT; the data lines DAL and the reset lines REL extend in the column direction and are spaced apart in the row direction; any pixel circuit is connected with a data line DAL through the control terminal of the driving transistor DT thereof, and is connected with the reset line REL through the second terminal of the driving transistor DT and is connected with a light emitting device OLED; the same column of pixel circuits are connected with the same data line DAL and the same reset line REL;

as shown in fig. 2, the driving method includes steps S110 to S130, in which:

step S110, selecting one pixel circuit as a target pixel circuit, and determining a correction amount of the pixel circuit in each row according to a voltage change of a reset line caused by a voltage change of a data line connected to the target pixel circuit, where the correction amount of the pixel circuit in an ith row is an ith correction amount;

step S120, in a display stage nL of the nth frame, inputting a data voltage to the pixel circuit through the data line, and inputting a reference voltage to the pixel circuit through the reset line; a data voltage of any one of the pixel circuits in an ith row of the pixel circuits is a sum of a reference data voltage and the ith correction amount, the correction amount being smaller than the reference data voltage;

step S130, setting the data voltage of the pixel circuit to zero through the data line in the black insertion phase nB of the nth frame;

The driving method according to the embodiment of the present disclosure may divide a display stage L and a black insertion stage B in a frame, where the display stage L transmits a data voltage Vdata and a reference voltage Vref through a data line DAL and a reset line REL to realize image display, and the black insertion stage B sets the data voltage Vdata to zero to realize a black insertion function and shorten a display time, thereby weakening an afterimage phenomenon caused by persistence of vision. Meanwhile, by detecting the voltage change of the data line DAL and the voltage change of the reset line REL, a variation reflecting the influence of the coupling effect of the data line DAL and the reset line REL on the voltage of the reset line REL is determined, and the correction amount of the pixel circuit of each row is determined based on the variation; the coupling action of the data line DAL and the reset line REL may cause the reference voltage to be suddenly pulled high, resulting in a jitter of the reference voltage, such that a voltage difference between the data voltage Vdata and the reference voltage Vref is different from a design value, and since the nth frame data voltage is a sum of the reference data voltage and the correction amount VT, i.e., the correction amount VT is superimposed on the data voltage Vdata, a deviation of the voltage difference between the data voltage Vdata and the reference voltage Vref due to the reference voltage Vref and the design value may be reduced, thereby improving a display effect.

The display panel according to the embodiment of the present disclosure is explained in detail below:

the display panel can include a driving back plate and a light emitting layer, the driving back plate has a driving circuit, the light emitting layer includes a plurality of light emitting devices OLED, each light emitting device OLED can be driven to emit light by the driving circuit, wherein:

the driving backplate may comprise a substrate and a driving layer, wherein:

the substrate may be a flat, load-bearing plate, which may be rectangular or other shape. The driving layer can be directly laminated on one side of the substrate; alternatively, in order to avoid the influence of impurities in the substrate on the driving layer, a buffer layer may be further disposed between the substrate and the driving layer, and the driving layer may be disposed on a surface of the buffer layer facing away from the substrate. The driving layer at least comprises a pixel area and a peripheral area, wherein the peripheral area can be an annular area surrounding the pixel area or two discontinuous areas separated from two sides of the pixel area, and the peripheral area is only required to be positioned outside the pixel area.

The driving circuit of the driving layer may include a plurality of pixel circuits and a peripheral circuit, the pixel circuits being disposed in the pixel region, and of course, a partial region where a part of the pixel circuits may exist may be located in the peripheral region. The number of the pixel circuits may be the same as the number of the light emitting devices OLED, and the pixel circuits are connected to the light emitting devices OLED in a one-to-one correspondence, so as to control the light emitting devices OLED to emit light independently, respectively. Of course, the same pixel circuit may be connected through the light emitting device OLED to drive the plurality of light emitting devices OLED to emit light. The peripheral circuit is located in the peripheral area, and the peripheral circuit is connected to the pixel circuit and is used for inputting driving signals such as scanning signals, data signals, power signals and reset signals to the pixel circuit so as to control the light emitting device OLED to emit light. The peripheral circuits may include a gate driving circuit, a source driving circuit, a power supply circuit, and the like.

As shown in fig. 1, each pixel circuit may include a plurality of transistors, each of which includes a control terminal, a first terminal, and a second terminal, and each of which includes a driving transistor DT. Meanwhile, the driving layer may further include a plurality of data lines DAL and reset lines REL, the data lines DAL and reset lines REL may extend in the column direction and be distributed at intervals in the row direction, and both the data lines DAL and the reset lines REL extend into the peripheral region and are connected to the peripheral circuit; for example, the data line DAL may be connected to a source driving circuit, and the reset line REL may be connected to a reset circuit.

Any pixel circuit may be connected to a data line DAL through a control terminal of a driving transistor thereof, and connected to a reset line REL through a second terminal of the driving transistor, and meanwhile, the second terminal of the driving transistor may be connected to a light emitting device, and the first terminal of the driving transistor is configured to receive a power signal. The same row of pixel circuits may be connected to the same data line DAL, and the same column of pixel circuits may be connected to the same reset line REL. The peripheral circuit may input a data voltage to the control terminal of the driving transistor DT through the data line DAL and a reference voltage to the second terminal of the driving transistor DT through the reset line REL.

The following description will be given by taking a pixel circuit of 3T1C structure as an example, and the structure and driving method of the pixel circuit are exemplarily described:

as shown in fig. 1, the pixel circuit may include three transistors and one storage capacitor, i.e., a driving transistor DT, a first transistor T1, a second transistor T2, and a storage capacitor Cst, wherein:

the driving transistor DT has a first terminal for receiving a first power signal VDD, a second terminal connected to a first electrode of a light emitting device OLED, and a second electrode for receiving a second power signal VSS.

The storage capacitor Cst is connected between the control terminal and the second terminal of the driving transistor DT, and a first electrode of the storage capacitor Cst is connected to the control terminal of the driving transistor DT and a second electrode thereof is connected to the second terminal of the driving transistor DT.

A control terminal of the first transistor T1 is operable to receive scan signals G1 and G2, a first terminal is connected to a data line DAL, and a second terminal is connected to a control terminal of the driving transistor DT.

The second transistor T2 has a control terminal for receiving the write scan signals G1 and G2, a first terminal connected to the second terminal of the driving transistor DT, and a second terminal connected to the second terminal of the driving transistor DT and the second electrode of the storage capacitor Cst and the first electrode of the light emitting device OLED.

The transistors can be N-type thin film transistors, the light emitting device OLED is an organic light emitting diode, the first electrode of the organic light emitting device OLED is the anode of the organic light emitting diode, and the second electrode of the organic light emitting device OLED is the cathode of the organic light emitting diode. The driving transistor DT, the first transistor T1, and the second transistor T2 are all turned on at a high level and turned off at a low level. Of course, the one or more transistors may also be P-type thin film transistors, and the transistors may be low temperature polysilicon transistors, metal oxide transistors, etc., and the types thereof are not particularly limited herein.

In addition, in order to facilitate transmission of the scan signals G1 and G2, the driving layer may further include scan lines GAL, the scan lines GAL may extend to the peripheral region in the row direction and be spaced apart in the column direction, a control terminal of the first transistor T1 may be connected to a scan line GAL1, a control terminal of the second transistor T2 may be connected to a scan line GAL2, and the peripheral circuit may transmit the scan signals to the control terminals of the first transistor T1 and the second transistor T2 by scanning so as to turn on the first transistor T1 and the second transistor T2.

In some embodiments of the present disclosure, the scan lines GAL to which the control terminals of the first transistor T1 and the second transistor T2 are connected are the same scan line GAL, that is, the same pixel circuit is connected to one scan line GAL, so that the same row of pixel circuits is connected to the same scan line GAL, and the scan lines GAL connected to two rows of pixel circuits are different. The peripheral circuit may include a gate driving circuit that may simultaneously transmit scan signals G1 and G2 to the first transistor T1 and the second transistor T2 through the scan line GAL.

In other embodiments of the present disclosure, the scan lines GAL to which the control terminals of the first transistor T1 and the second transistor T2 are connected are different scan lines GAL, so that the same pixel circuit needs to connect two scan lines GAL1 and GAL2, and accordingly, the same row of pixel circuits connects two scan lines GAL, and the adjacent two rows of pixel circuits can connect four scan lines GAL in total. The peripheral circuit may include a gate driving circuit and a reset control circuit, and for any row of pixel circuits, the gate driving circuit may simultaneously transmit a scan signal G1 to each of the first transistors T1 through one scan line GAL1 to turn on the first transistor T1, and the reset control circuit may transmit a scan signal G2 to the second transistor T2 through another scan line GAL2 to turn on the second transistor T2.

The thin film transistor of the driving circuit layer may be a top gate or bottom gate thin film transistor, each thin film transistor may include an active layer, a gate electrode, a source electrode, and a drain electrode, wherein the gate electrode may be a dual gate structure, or a single gate or other structures, the active layers of the thin film transistors are disposed on the same layer, the gate electrode is disposed on the same layer, and the source electrode and the drain electrode are disposed on the same layer, so as to simplify the process.

The structure of the driving layer is exemplarily illustrated below by taking a top gate type thin film transistor in the pixel circuit as an example:

as shown in fig. 1, the driving layer may include an active layer, a first gate insulating layer, a gate electrode, a second gate insulating layer, an interlayer dielectric layer, a source drain layer, and a planarization layer, wherein:

the active layer is arranged on one side surface of the substrate, and the first gate insulating layer covers the active layer and the substrate; the grid electrode is arranged on the surface of the first grid insulating layer, which is deviated from the substrate, and is opposite to the active layer; the second gate insulating layer covers the gate electrode and the first gate insulating layer; the interlayer dielectric layer covers the second gate insulating layer; the source drain layer is arranged on the surface of the interlayer dielectric layer, which is deviated from the substrate, and comprises a source electrode and a drain electrode, and the source electrode and the drain electrode are connected to two ends of the active layer through contact holes; the flat layer covers the source drain layer and the interlayer dielectric layer. Of course, the driving layer may also include other film layers as long as the light emitting device OLED can be driven to emit light, and will not be described in detail herein.

In addition, the driving layer may further include a first electrode and a second electrode of the storage capacitor Cst, the first electrode may be disposed on the same layer as the gate electrode, the second electrode may be disposed on a surface of the second gate insulating layer facing away from the substrate and facing the first electrode, and the interlayer dielectric layer covers the second electrode.

As shown in fig. 1, the light emitting layer is disposed on one side of the driving layer, and may include a plurality of light emitting devices OLED arranged in an array, each of which may emit light under the driving of the pixel circuit.

In some embodiments of the present disclosure, the light emitting device OLED is an organic light emitting diode, which may include a first electrode, a light emitting functional layer, and a second electrode sequentially stacked in a direction away from the substrate, wherein:

the first electrode may be disposed on a surface of the planarization layer facing away from the substrate, and connected to a second terminal of the driving transistor DT of a pixel circuit through the contact hole.

The light-emitting function layer is arranged on the surface of the first electrode, which is deviated from the substrate, and can comprise a hole injection layer, a hole transport layer, a composite light-emitting layer, an electron transport layer and an electron injection layer which are sequentially stacked along the direction of deviating from the substrate, and in addition, an electron blocking layer can be arranged between the hole transport layer and the composite light-emitting layer.

The second electrode covers the light-emitting functional layer and can extend to the peripheral area, and the second electrode can be connected with the power signal end so as to receive a second power signal VSS. The first electrode and the second electrode may work together to make the light emitting device OLED emit light, and the specific light emitting principle of the organic light emitting diode is not described in detail herein. The material of the second electrode may be magnesium (Mg), silver alloy, or other material.

In order to define the range of each light emitting device OLED, the light emitting layer may further include a pixel defining layer, which may be disposed on the surface of the driving layer away from the substrate with the first electrode, and has a plurality of openings exposing the first electrodes in a one-to-one correspondence, and the light emitting functional layer is stacked on the area of the first electrode in the opening. The light emitting functional layers of each light emitting device OLED are distributed at intervals independently. The light emission colors of the different light emission functional layers may be the same or different. The second electrode covers the light emitting function layers at the same time, so that the light emitting devices OLED can share the same second electrode. Each of the light emitting devices OLED may be defined by the plurality of openings, and the boundary of any one of the light emitting devices OLED is the boundary of its corresponding opening.

The light emitting devices OLED include a plurality of light emitting devices OLED emitting different colors of light, for example, a red light emitting device OLED, a green light emitting device OLED, and a blue light emitting device OLED.

The following description will be made of the principle of driving the light emitting device OLED to emit light, taking a pixel circuit and the light emitting device OLED connected thereto as an example:

scan signals G1 and G2 may be input to the pixel circuit through the scan line GAL, and the first transistor T1 and the second transistor T2 are turned on; at this time, the data voltage Vdata may be written to the control terminal of the driving transistor DT through the data line DAL, and the reference voltage Vref is transmitted to the second terminal of the driving transistor DT of the pixel circuit through the reset line REL, thereby charging the storage capacitor Cst of the pixel circuit. Meanwhile, the first terminal of each driving transistor DT receives a first power voltage VDD, and the second electrode of the light emitting device OLED receives a second power voltage. The driving transistor DT is continuously turned on by the storage capacitor Cst, thereby causing the light emitting device OLED to emit light. Wherein, the current I of the driving transistor DT is k (Vgs-Vth)²K is a constant, Vgs is the voltage of the control terminal (g node) and the second terminal (s node) of the driving transistor DT, and Vth is the threshold voltage of the driving transistor DT.

The following describes a driving method of each row of the light emitting devices OLED when displaying any one frame of image:

as shown in fig. 1, the pixel circuits of each row may be scanned by the scan line GAL row by row, i.e., the scan signals G1 and G2 are input to the pixel circuits of each row in sequence; when scanning to any one row of pixel circuits, the first transistor T1 and the second transistor T2 of each pixel circuit of the row are turned on; at this time, the data voltage may be simultaneously written to the control terminal of the driving transistor DT of the row pixel circuit through the data lines DAL, and the reference voltage may be transferred to the second terminal of the driving transistor DT of the row pixel circuit through the reset lines REL. At the same time. Under the action of each storage capacitor Cst, the driving transistor DT is continuously turned on, so that the light emitting devices OLED connected to the pixel circuits in the same row emit light. Based on the method, when each row of pixel circuits are scanned line by line and the corresponding light-emitting device OLED is lighted, one frame of image is displayed, and then the driving process of the previous frame is repeated when the next frame of image is displayed, but the data signals can be different.

Further, in order to avoid the display phenomenon, each frame may be divided into at least a display stage L and a black insertion stage B, in the display stage, the light emitting device OLED is driven to emit light based on the principle of driving the light emitting device OLED, in the black insertion stage B, the voltage of each data line DAL is reduced to zero, so as to display a black picture, and shorten the display time within a frame time, so as to reduce the afterimage phenomenon caused by the persistence of vision, and the specific principle of black insertion is not described in detail herein.

In the same frame, the magnitude of the data voltage Vdata required for each pixel circuit depends on the requirements of the displayed screen, and the data voltage Vdata may be different. The data voltage Vdata in fig. 2 is a straight line in the same frame, and only the timing of the data voltage Vdata of each pixel circuit in the same frame is schematically shown, and the data voltages Vdata of the pixel circuits in the same frame are not limited to being completely equal.

As shown in fig. 1, in some embodiments of the present disclosure, the display panel may further include an encapsulation layer, which may cover a surface of the light emitting layer away from the substrate and cover all the light emitting devices OLEDs, so as to protect the light emitting layer and prevent external water and oxygen from corroding the light emitting devices OLEDs.

In addition, the display panel may further include a touch Layer and a transparent cover plate, where the touch Layer may be disposed On a side of the encapsulation Layer TFE away from the substrate, that is, an FMLOC (Flexible Multi-Layer On Cell) manner may be adopted for sensing touch operation. The touch layer may be a self-capacitive or mutual capacitive touch structure, and the specific structure is not particularly limited as long as the touch function can be realized. The transparent cover plate can be arranged on the surface of the touch layer, which is far away from the substrate, and is used for protecting, and a user can touch the transparent cover plate when performing touch operation. The transparent cover plate can be adhered to the surface of the touch layer, which is far away from the substrate, by optical cement or other adhesives, and can be UTG (Ultra Thin Glass) or other transparent film layers as long as the functions of protection and light transmission are achieved.

In the display panel, the inventor has found that, for the data line DAL and the reset line REL connected to the same column of pixel circuits, when the display period L transits to the black insertion period B in each frame, the voltage on the data line DAL drops from the data voltage Vdata to zero, and at this time, although the reset line REL receives the constant reference voltage Vref, the voltage on the reset line REL may be jittered downward due to the coupling effect of the data line DAL and the reset line REL, that is, the voltage on the reset line REL is pulled down and restored slowly. Then, when the display period of the next frame is entered, the voltage of the data line DAL increases again by the large data voltage Vdata from zero, and the voltage on the reset line REL is made to dither upward, that is, the voltage of the reset line REL is pulled high and then restored to the reference voltage Vref. During the dithering, the voltage at the second end of the driving transistor DT is abruptly changed to the voltage at the data line DAL, which may cause the voltage at the reset line REL to be first dithered and then restored. In combination with the above current formula of the driving transistor DT, it can be seen that if the voltage at the second terminal of the driving transistor DT is jittered, Vgs is abnormally changed, thereby affecting the current I and thus the normal light emission of the light emitting device.

Based on the above problem, the present disclosure proposes a driving method to solve the above problem: that is, the influence of the change of the signal of the data line DAL on the reset line REL is detected in advance, and the signal of the data line DAL can be compensated according to the influence when the driving transistor operates, so that even if the voltage of the second terminal of the driving transistor changes due to the voltage jitter of the reset line REL, the change of Vgs can be reduced to the maximum extent, and the light emitting device OLED can be ensured to emit light normally.

The following describes in detail a driving method according to an embodiment of the present disclosure:

as shown in fig. 1 and 2, the driving method of the present disclosure may include steps S110 to S130, in which:

in step S110, a pixel circuit is selected as a target pixel circuit, and a correction amount of the pixel circuit in each row is determined according to a voltage change of a reset line caused by a voltage change of a data line DAL connected to the target pixel circuit, where the correction amount of the pixel circuit in the ith row is an ith correction amount.

Step S110 may be performed before the display panel leaves the factory, and the correction amount is directly applied in the process of actually using the display panel by the user without performing a test. The target pixel circuit may be an arbitrary pixel circuit. The present pixel circuit may be any pixel circuit, and is not limited herein.

Therefore, the voltage jitter of the reset line REL caused by the data line DAL can be detected by simulating the signal of the display panel during normal operation in step S110, so as to determine the correction amount.

In some embodiments of the present disclosure, step S110 may include steps S1110-S1130, wherein:

step S1110 is to input a detection data voltage to the data line connected to the target pixel circuit, and to input a detection reference voltage to the reset line REL.

For the data line and the reset line connected to the same pixel circuit, a detection data voltage may be input to the data line, and a detection reference voltage may be input to the reset line. In order to improve the accuracy of the correction amount and reduce the influence of the voltage jitter on the current of the driving transistor to the maximum extent, the detected data voltage can be the data voltage when the image is normally displayed, and the detected reference voltage can be the reference voltage when the image is normally displayed.

Step S1120 detects a variation amount of the detection reference voltage of the reset line when the detection data voltage is set to zero.

The transition from the display phase to the black insertion phase may be simulated by setting the detection data voltage to zero, so as to obtain the variation of the detection reference voltage on the reset line REL. The variation is a voltage difference between the changed detection reference voltage and the detection reference voltage.

Step S1130 determines a correction amount of the pixel circuit for each line based on the change amount.

The correction quantity of the pixel circuit of the ith row is the correction quantity of the ith row, i is a positive integer not greater than N, and N is the row number of the pixel circuit.

Each row of pixel circuits can compensate the data voltage with the same correction amount, that is, each correction amount is the ith correction amount.

In addition, the inventor found that the voltage jitter on the reset line REL is removed within a certain time, so as to recover the reference voltage Vref, and only during the jitter period, the interference is generated on the light emitting device OLED, and since the pixel circuits are scanned line by line in each frame to drive the light emitting device OLED to emit light, the voltage jitter caused by the black insertion stage B of the previous frame continues to the display stage L of the current frame, but as the line by line scanning of the current frame proceeds, the voltage jitter is gradually reduced, even before scanning to the last line or scanning to the last line of pixel circuits, the voltage jitter is removed, only the data voltage needs to be determined for the pixel circuits of each line scanned before the voltage jitter is recovered, and after the voltage jitter is removed, no correction amount is needed.

The correction amount may be equal to the variation amount; alternatively, in order to further improve the accuracy of the correction amount, a correction coefficient K may be determined through a plurality of tests or empirical data, and the correction amount may be determined based on the correction coefficient and the change amount. In addition, the jitter value of the voltage can be more accurately fitted by adding the constant b,

as shown in fig. 2, in some embodiments of the present disclosure, the correction amounts of the pixel circuits of different rows are different; the correction amount and the change amount satisfy the following relation:

VT＝KΔV；

VT is correction quantity, Δ V is variation quantity, K is correction coefficient, and K is positive real number.

In some embodiments of the present disclosure, the i-1 th correction amount is larger than the i-th correction amount, that is, the jitter gradually decreases with time, and the required correction amount may gradually decrease until the jitter is recovered when scanning to the nth row pixel circuit, and the nth correction amount may be set to zero without correction amount.

Further, as shown in fig. 2, the j-th correction amount and the change amount may satisfy the following relationship:

VT1＝KΔV；

VTj＝(K(N-j)/N)ΔV；

VT1 is the first correction amount, i.e. the correction amount required when scanning the first row of pixel circuits; VTj is a jth correction amount, Δ V is a variation amount, j is a positive integer greater than 1 and not greater than N, K is a correction coefficient, and K is a positive real number.

As shown in fig. 2, in some embodiments of the present disclosure, the j-th correction amount and the 1 st correction amount satisfy the following relationship:

VT1＝KΔV+b；

VTj＝(K(N-j)/N)ΔV+b；

VT1 is the first correction amount, i.e. the correction amount required when scanning the first row of pixel circuits; VTj is the jth correction quantity, Δ V is the variation, j is a positive integer greater than 1 and not greater than N, K is a positive real number, b is a constant, and the specific numerical value of b is not particularly limited herein and can be determined by experiments and empirical data.

In step S120, in a display phase of an nth frame, inputting a data voltage to the pixel circuit through the data line and inputting a reference voltage to the pixel circuit through the reset line; the data voltage of any one of the pixel circuits in the ith row is a sum of a reference data voltage and the ith correction amount, and the correction amount is smaller than the reference data voltage.

Since the black insertion period B does not exist before the first frame image is displayed, the data voltage Vdata for displaying the first frame image does not need to be compensated, and thus N is a positive integer greater than 1 and not greater than N, which is the last frame of the display screen.

Of course, in another embodiment of the present disclosure, step S110 may be performed in a state where a special correction state different from the state of the display image is set in the display panel during the use of the display panel after the shipment of the display panel, and then the display state is restored to calibrate the correction amount.

In some embodiments of the present disclosure, step S120 may include:

scanning each row of pixel circuits line by line, and respectively inputting a data voltage Vdata to each pixel circuit in the ith row through each data line DAL when scanning to the pixel circuits in the ith row; and inputs a reference voltage Vref to each of the i-th row pixel circuits to the respective reset lines REL, respectively.

The data voltage input from the data line DAL to the pixel circuit in the ith row of pixel circuits may be a sum of a reference data voltage and an ith correction amount, the reference data voltage Vdata may be a design value not considering voltage jitter, and after superimposing the ith correction amount and the reference data voltage, the data voltage Vdata actually input to the data line DAL may be made larger than the design value thereof, that is, the voltage on the data line DAL is increased, the difference between the data voltage Vdata and the reference voltage after jitter may be reduced, and increase in Vgs due to voltage jitter may be reduced, thereby reducing interference with the current of the driving transistor DT.

Meanwhile, the correction amount is smaller than the reference data voltage, for example: the voltage on the reset line REL varies by 0.2V or less due to the variation of the data line DAL, and the reference data voltage may be greater than 1V.

In step S130, in the black insertion phase of the nth frame, the data voltage of the pixel circuit is set to zero through the data line.

As shown in fig. 2, when the display period nL of the nth frame transitions to the black insertion period nB of the nth frame, the data voltage is set to zero, and the reference voltage Vref gradually increases after shaking down. When the black insertion period nB of the nth frame transitions to the display period (N +1) L of the (N +1) th frame, the reference voltage Vref is dithered upward, but is superimposed with the data voltage Vdata set to zero due to the display period (N +1) L. In the display period (N +1) L of the (N +1) th frame, the data voltage Vdata is superimposed with the correction amount VT, so that the difference between the superimposed Vdata and the dithered Vref does not change significantly, thereby reducing abnormal fluctuation of Vgs and facilitating guarantee of the display effect.

In addition, in some embodiments of the present disclosure, the reset line REL may be further used as a sensing line for performing external compensation, which is used to detect a signal at the second end of the driving transistor DT and transmit the signal to a sensing circuit in the peripheral circuit, and a parameter of the threshold voltage may be determined by the sensing circuit according to the detected signal, so as to compensate the data signal in the next frame of image, and a specific principle of the external compensation is not particularly limited herein.

It should be noted that although the various steps of the driving method in the present disclosure are depicted in the drawings in a particular order, this does not require or imply that all of the steps must be performed in this particular order to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A driving method of a display panel is characterized in that the display panel comprises a plurality of pixel circuits, a data line and a reset line which are distributed in an array; the pixel circuit includes a driving transistor; the data lines and the reset lines extend along the column direction and are distributed at intervals along the row direction; any pixel circuit is connected with a data line through a control end of a driving transistor of the pixel circuit, connected with the reset line through a second end of the driving transistor and used for being connected with a light-emitting device, and one end of the driving transistor is used for inputting a power supply signal; the pixel circuits in the same column are connected with the same data line and the same reset line;

the driving method includes:

2. The driving method according to claim 1, wherein a correction amount of the pixel circuit for each row is determined in accordance with a voltage change of a reset line caused by a voltage change of a data line to which the target pixel circuit is connected; the method comprises the following steps:

3. The driving method according to claim 2, wherein a correction amount of the pixel circuit is equal for each row.

4. The driving method according to claim 3, wherein the correction amount and the change amount satisfy the following relation:

VT＝KΔV；

5. The driving method according to claim 2, wherein correction amounts of the pixel circuits in different rows are different.

6. The drive method according to claim 5, characterized in that the i-1 th correction amount is larger than the i-th correction amount.

7. The driving method according to claim 6, wherein the nth correction amount is zero.

8. The driving method according to claim 7, wherein a j-th correction amount and the change amount satisfy a relationship:

VT1＝KΔV；

VTj＝(K(N-j)/N)ΔV；

9. The driving method according to claim 7, wherein the j-th correction amount and the 1 st correction amount satisfy the following relationship:

VT1＝KΔV+b；

VTj＝(K(N-j)/N)ΔV+b；

10. The driving method according to any one of claims 1 to 9, wherein in a display phase of an nth frame, a data voltage is input to the pixel circuit through the data line, and a reference voltage is input to the pixel circuit through the reset line; the method comprises the following steps:

11. The driving method according to claim 10, wherein the pixel circuit further comprises:

a first pole of the storage capacitor is connected with the control end of the driving transistor, and a second pole of the storage capacitor is connected with the second end of the driving transistor;

scanning each row of the pixel circuits line by line; the method comprises the following steps: