CN113986715A

CN113986715A - Debugging method and system of processor, and system-on-chip

Info

Publication number: CN113986715A
Application number: CN202111143637.2A
Authority: CN
Inventors: 郑文斌
Original assignee: Pingtouge Shanghai Semiconductor Co Ltd
Current assignee: Hangzhou C Sky Microsystems Co Ltd
Priority date: 2021-09-28
Filing date: 2021-09-28
Publication date: 2022-01-28

Abstract

The application provides a debugging method, a debugging system and a system-on-chip of a processor, wherein the method comprises the following steps: acquiring a debugging request; responding to the debugging request, and acquiring a debugging enabling signal; determining an executable domain allowed to enter a debugging mode according to the debugging enabling signal; the control processor enters a super user mode and debugs the executable domain that is allowed to enter a debug mode. The processor is controlled to enter the super user mode to debug the executable domain instead of adopting a machine mode to regulate and control the executable domain, so that the safety in the debugging process can be effectively improved, the debugging enabling signal is set to represent which executable domains need to be debugged, the requirement of independently debugging a single executable domain can be met, and the requirement of debugging isolation in safety debugging is met.

Description

Debugging method and system of processor, and system-on-chip

Technical Field

The present application relates to the field of semiconductor chip technology, and in particular, to a method and system for debugging a processor, and a system-on-chip.

Background

In order to solve the security threat faced by smart devices, internet of things devices, and the like, a terminal chip generally provides a trusted execution environment to ensure that system programs, terminal parameters, security data, and user data in the chip are not tampered or illegally acquired. Therefore, a plurality of independent executable domains (zones) can be virtualized under the coordination of underlying software through an isolation mechanism provided by hardware, and the software and hardware resources in each Zone are ensured not to be illegally accessed by other zones.

However, the existing RISC-V based debug architecture cannot support independent debugging of zones. Because the processor directly enters the machine mode with the highest execution authority after entering the debugging, the debugger can access any resource on the system beyond the Zone isolation limit in the machine mode because the machine mode has the highest execution authority. The peripheral debugging module can acquire the running state and sensitive data of the processors of other zones through the debugging interface, and even the processors can be controlled to run malicious codes with high authority through the debugging interface, so that the whole system is subjected to security threat.

Aiming at the problem of how to safely debug different zones in the prior art, no effective solution is provided at present.

Disclosure of Invention

The application aims to provide a debugging method, a debugging system and a system-on-chip of a processor, which can realize safe debugging of an executable domain.

The application provides a debugging method, a system and a system-on-chip of a processor, which are realized as follows:

a method of debugging a processor, comprising:

acquiring a debugging request;

responding to the debugging request, and acquiring a debugging enabling signal;

determining an executable domain allowed to enter a debugging mode according to the debugging enabling signal;

the control processor enters a super user mode and debugs the executable domain that is allowed to enter a debug mode.

A debugging system of a processor, comprising:

the processor virtualizes a plurality of independent executable domains;

the debugging authentication module is used for setting a debugging enabling signal;

the debugging module is used for receiving a debugging request of a debugger, responding to the debugging request, obtaining a debugging enabling signal, determining an executable domain allowed to enter a debugging mode according to the debugging enabling signal, controlling the processor to enter a super user mode, and debugging the executable domain allowed to enter the debugging mode.

A system-on-chip includes the above processor debugging system.

A computer readable storage medium having stored thereon computer instructions which, when executed, implement the steps of the above-described method.

According to the debugging method of the processor, the processor is controlled to enter the super user mode to debug the executable domain instead of adopting the machine mode to regulate and control the executable domain, so that the safety in the debugging process can be effectively improved, the debugging enabling signal is set to represent which executable domains need to be debugged, the requirement of independent debugging of a single executable domain can be met, and the requirement of debugging isolation in safety debugging is met.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without any creative effort.

FIG. 1 is a flow chart of a method of one embodiment of a method for debugging a processor provided herein;

FIG. 2 is an architecture diagram of one embodiment of a debugging system of a processor provided herein;

fig. 3 is a schematic diagram of an architecture of a signal line arrangement provided in the present application.

Detailed Description

In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In order to meet the isolation requirement of the TEE (Trusted Execution Environment), multiple executable domains (zones) are virtualized on the basis of a processor architecture, and each Zone can independently run a respective operating system and an application program based on the operating system. The processor can switch between different zones according to needs, and when the processor is switched to a certain Zone to run, the Zone occupies the whole physical core in real time. For Zone switching, it can be done by Trusted Firmware (TF) running in the highest privilege mode (machine mode).

A plurality of executable domains are virtualized, different OSs or services are allowed to run in the respective independent execution domains, the services can be isolated from each other, and the possibility that other services are also broken due to the fact that a certain service or OS is broken is reduced. In the ARM architecture, there are only 2 executable domains at most, that is, all security services need to be put into the same executable domain for execution, and once a certain service has a bug, all services may be contaminated. In this example, a plurality of executable domains are virtualized to enable different services to run in different executable domains, so that isolation among different services can be increased, and the possibility that other services are polluted due to a vulnerability of one service is reduced. For example: some services with high security requirements, such as cryptographic services, secure storage and the like, run in independent execution domains, so that the possibility of stealing sensitive data is reduced.

However, in the existing processor architecture, after the processor enters the debugging, the processor directly enters the machine mode with the highest execution authority, and because the machine mode has the highest execution authority, in the machine mode, the debugger can cross the Zone isolation limitation, access any resource on the system, that is, when debugging each executable domain, the security of data and the system cannot be guaranteed.

For this reason, in this example, the processor can only enter the super-user mode, i.e. can only access the debug resources with the super-user permission of the current Zone, considering that all the debugs of the current Zone can be controlled. Furthermore, a single Zone can be independently debugged by setting a debugging enabling signal so as to meet the debugging isolation of the safety debugging requirement. For example, the processor may add a debug enable signal line for each Zone to control whether the Zone is debuggable, and if there are 16 zones, add 16 control signal lines to obtain a debug enable signal ZDBGEN [15: 0]. For example: when the debugging control signal of a certain Zone is pulled high, the processor allows the Zone to enter a debugging mode; when the debugging control signal of a certain Zone is pulled down, the processor does not allow the Zone to enter a debugging mode; when multiple debug control signals are pulled high at the same time, the processor allows all the zones with the debug control signals pulled high to enter the debug mode.

Furthermore, in order to meet the debugging requirement of debugging with the highest authority, a debugging control signal can be additionally added for controlling whether the processor enters a debugging mode with the highest authority (machine mode).

Based on this, in this example, a debugging method of a processor is provided, as shown in fig. 1, which may include the following steps:

step 101: acquiring a debugging request;

in practical implementation, a debug request may be obtained through the debug module, where the debug request may be sent by an external debugger, that is, if the external debugger determines that debugging is required, a debug request may be sent to trigger debugging.

Step 102: responding to the debugging request, and acquiring a debugging enabling signal;

after receiving the debug request, a debug enable signal may be obtained, by which it is characterized which executable domain needs to be debugged. For example, the debug enable signal may be implemented by a signal line or by a message mechanism.

If the implementation is realized by using signal lines, one signal line may be set for each executable domain, and whether the corresponding executable domain needs to be debugged is determined by whether the signal line is pulled high. If the message mechanism is adopted, a part of space can be allocated in the memory, the debug enable signal is stored, and when needed, the debug enable signal is read from the memory to determine which executable domains need to be debugged. In consideration of hardware implementation cost, in actual implementation, if the number of executable domains is large, the message mechanism is more suitable, and if the number of executable domains is small, the signal line is used, which method can be selected according to actual needs.

Step 103: determining an executable domain allowed to enter a debugging mode according to the debugging enabling signal;

for example, when the signal lines are arranged, there are currently 8 executable domains, and the corresponding debug enable signals are arranged as shown in table 1 below:

TABLE 1

Executable domain	0	1	2	3	4	5	6	7
									Value taking	0/1	0/1	0/1	0/1	0/1	0/1	0/1	0/1

Assume that the current debug enable signal is: 00101000, it may be determined that executable domain 2 and executable domain 4 are executable domains that need to be debugged, i.e. determined executable domains that are allowed to enter debug mode.

For each executable domain, a domain identification (Zone ID) may be added per executable domain to enable differentiation of the respective executable domains.

Step 104: the control processor enters a super user mode and debugs the executable domain that is allowed to enter a debug mode.

Furthermore, in order to meet the debugging requirement of debugging with the highest authority, a debugging control signal can be added for controlling whether the processor enters a debugging mode with the highest authority (machine mode). For this reason, after the debug request is obtained, the debug control signal may be obtained and a determination may be made to determine whether or not debugging in machine mode is required. If the debugging is needed, the debugging is directly carried out through the machine mode, and if the debugging is not needed, the debugging enabling signal is obtained so as to determine which control domains need to be debugged in the super user mode. That is, in response to the debug request, a debug control signal is acquired; determining whether the processor is required to enter a debugging state in a machine mode according to the debugging control signal; controlling the processor to enter a debug state in machine mode if it is determined that the processor is required to enter the debug state in machine mode; in the event that it is determined that the processor is not required to enter a debug state in machine mode but the processor is currently in machine mode, controlling the processor to enter a debug wait state.

Specifically, the machine mode may be abbreviated as M mode, which is the highest privilege mode that hart (hardware thread) can execute under the reduced instruction set architecture.

The processor may be in machine mode not only during debugging, but also during normal processing. Thus, in the event that it is determined that the processor is not required to enter a debug state in machine mode, if the current processor is in machine mode, then a wait is required until the processor is not in machine mode and then triggers debugging. Accordingly, where it is determined that the processor is not required to enter a debug state in machine mode and the processor is not currently in machine mode, a debug enable signal may be obtained to determine which executable domains need to be debugged.

Considering simple implementation on hardware implementation to reduce complexity, the debug enable signal may be characterized by a signal line established between the debug authentication module and the processor, where one signal line may correspond to one executable domain, and in a case where a level of the signal line of a target executable domain is pulled high, it indicates that the target executable domain is allowed to enter a debug mode, or it may also be that an ID of the executable domain is characterized by the signal line, and which executable domain needs to be debugged is determined based on the ID.

Under the condition that the number of executable domains is large, the hardware cost is overhigh in a signal line mode, therefore, a message mechanism mode can be adopted to store the debugging enabling signal in the memory, and other modules acquire data by accessing the memory. That is, acquiring the debug enable signal may include: and calling a debugging enabling signal from the memory, wherein the debugging enabling signal is stored in the memory in a message mechanism mode.

The processor can be a processor which provides the capability of realizing a trusted execution environment based on a RISC-V processor architecture, and if processors of other architectures are divided into a plurality of executable domains, a scene of isolated debugging is needed, and the method is also suitable for the embodiment.

The hardware resources are under the coordination management of Trusted Firmware (TF) running in a machine mode, the processor virtualizes a plurality of completely independent executable domains, and it is required to ensure that the software and hardware resources in each Zone are not illegally accessed by other zones, where the software and hardware resources may include: execution, memory, peripherals, I/O, etc. For a processor, the resources of the processor may include: after processor resources are isolated and System controlled by a PMP (Physical Memory Protection in a processor architecture), the processor runs in different zones in a time-sharing manner, and cooperates with other Protection mechanisms (e.g., IOPMP (Input/Output Physical Memory Protection)) of a System on Chip (SoC) to jointly construct a security System based on software and hardware cooperative work.

In order to implement the processor debugging method, a processor debugging system is further provided in this example, as shown in fig. 2, which may include: a processor 201 virtualizing a plurality of independent executable domains; the debugging authentication module 202 is used for setting a debugging enabling signal; the debugging module 203 is configured to receive a debugging request of a debugger, obtain a debugging enable signal in response to the debugging request, determine an executable domain allowed to enter a debugging mode according to the debugging enable signal, control the processor to enter a super user mode, and debug the executable domain allowed to enter the debugging mode.

The debugging authentication module can be connected with the processor through a plurality of signal lines, one signal line corresponds to one executable domain, and when the level of the signal line of the target executable domain is pulled high, the target executable domain is allowed to enter a debugging mode. The debugging authentication module can be further used for setting a debugging enabling signal through a signal line between the debugging authentication module and the processor, wherein the debugging enabling signal is used for representing whether the processor needs to enter a debugging state in a machine mode. For how to perform debugging specifically, reference may be made to the description in the processor debugging method, and details are not described herein again.

The processor may be a RISC-V (reduced instruction set) architecture based processor, such as a System of processors (e.g., System C908 processor), or other family of processors designed based on a RISC-V architecture.

The processor debugging system can be arranged on a system-on-chip, and the method and the processor debugging system are particularly suitable for selective debugging of a plurality of (more than three) zone conditions.

The method and system are described below with reference to a specific embodiment, however, it should be noted that the specific embodiment is only for better describing the present application and is not to be construed as limiting the present application.

Taking a switch C908 processor as an example, the switch C908 is a processor that provides a capability of implementing a trusted execution environment based on a RISC-V processor architecture, and the switch C908 processor virtualizes a plurality of independent execution environments under coordination of bottom layer software through an isolation mechanism provided by hardware, and ensures that software and hardware resources in each Zone are not illegally accessed by other zones. Wherein, the software and hardware resources may include: execution, memory, peripherals, I/O, etc. That is, the metro C908 processor is securely extended based on the RISC-V standard architecture, and the processor virtualizes a plurality of completely independent executable domains under the coordination management of the Trusted Firmware (TF) operating in the machine mode. After the processor resources (such as Cache, TLB, interrupt, access and execution authority) of the metro C908 are isolated and managed by the PMP, the processors run in different zones in a time-sharing manner, and cooperate with other protection mechanisms (such as IOPMP) of the SoC to construct a security system based on software and hardware cooperative work.

However, the existing debugging architecture of RISC-V cannot support independent debugging of Zone, and the Debugging Module (DM) controls the RISC-V processor to enter the machine mode debugging state after receiving the debugging request. After entering the debug state, the debugger can continue to send commands to the debug module, and the control processor executes any instruction sent by the debugger. Because the processor enters a machine mode with the highest authority after debugging, the external debugger can control the processor to access any system resource, thereby bypassing the security line of the Zone.

In order to support independent debugging of a Zone under the condition that a plurality of independent zones are virtualized after a new security extension is added to a RISC-V debugging architecture, in this example, a control signal is introduced, and the debugging permission is separated by introducing the control signal. For example, a Zone debug enable signal (ZDBGEN [15:0]) may be added.

Assuming that the processor virtualizes 16 independent zones, the processor may add a signal line (0, 1, 2 … 15) for each Zone to control whether the Zone is debuggable as shown in fig. 3, and the debug enable signal may be represented as ZDBGEN [15:0], i.e., there are 16 zones in total, and thus 16 control signal lines are newly added.

When the debugging enabling signal of a certain Zone is pulled high, the processor allows the Zone to enter a debugging mode; when the debug enable signal of a certain Zone is pulled down, the processor does not allow the Zone to enter a debug mode; when multiple debug enable signals are pulled high at the same time, the processor allows all the zones with the debug enable signals pulled high to enter the debug mode. For all the debugging of the current Zone, the processor can only enter the super user mode, namely, the processor can only access the debugging resources with the super user authority of the current Zone.

In order to meet the debugging requirement of the highest authority, the metro C908 adds an MDBGEN debugging control signal for controlling whether the processor enters the debugging mode with the highest authority (machine mode).

As shown in figure 3 of the drawings,

when the processor receives a Debug request sent by a Debug Module (DM), the processor needs to perform the following additional checks on the Debug request according to the Debug authority controlled by the Debug Authentication Module (DAM):

when MDBGEN is equal to 1, the processor enters an M-mode debugging mode;

when MDBGEN is 0:

if the processor runs in the machine mode, the processor enters a debugging waiting state and does not respond to the debugging request;

if the processor runs in a non-machine mode and the debugging control signal ZDBGEN of the current Zone is 1, the processor enters a super user mode;

if the processor is operating in non-machine mode and the debug control signal ZDBGEN of the current Zone is 0, the processor will enter a debug wait state and not respond to debug requests.

That is, the debugging authority can be controlled by setting the debugging authentication module, that is, the debugging authentication module manages MDBGEN and ZDBGEN [15:0] signals to be output to the processor, and the debugging authentication module can be customized when being implemented, for example, implemented by a system-level chip manufacturer during hardware design.

The number of bits of the debug control signal ZDBGEN may be determined according to the number of zones, and the number of bits of the debug control signal ZDBGEN may be implemented by a system-on-chip vendor during hardware design.

As shown in table 2, the correspondence between the Zone ID bit width, the Zone number, and the number of ZDBGEN signal lines is:

TABLE 2

In practical implementation, the method may use a one-hot mode to encode the ZDGBEN, that is, each signal line represents an enable bit, and then 16 signal lines are set by 16 zones; the ZDDBEN may also be encoded in a multi-hot manner, such as by conveying a Zone ID, which may reduce the number of signal lines if the ZDBGEN conveys a Zone ID, and in the case of 16 zones, the processor decodes the ZID [3:0] signal. That is, based on the received signal, the corresponding Zone ID is identified to determine which Zone needs to be debugged.

For the security control side (Secure Server), authentication and identification can be performed through a user name/password and other login modes, after authentication and identification, management of MDBGEN and ZDBGEN [15:0] signals can be achieved, for example, 0/1 is set for MDBGEN, which bits are set to 0 for ZDBGEN [15:0], and which bits are set to 1, so that management and control of a debugging process are achieved.

The executable domain is debugged by controlling the processor to enter the super user mode instead of regulating and controlling the executable domain by adopting the machine mode, so that the safety in the debugging process can be effectively improved, the debugging enabling signal is set to represent which executable domains need to be debugged, the requirement of independently debugging a single executable domain can be met, and the requirement of debugging and isolation in safety debugging is met.

An embodiment of the present application further provides a specific implementation manner of an electronic device, which is capable of implementing all steps in the debugging method of the processor in the foregoing embodiment, where the electronic device specifically includes the following contents: a processor (processor), a memory (memory), a communication Interface (Communications Interface), and a bus; the processor, the memory and the communication interface complete mutual communication through the bus; the processor is configured to call a computer program in the memory, and the processor implements all steps in the debugging method of the processor in the foregoing embodiments when executing the computer program, for example, the processor implements the following steps when executing the computer program:

step 1: acquiring a debugging request;

step 2: responding to the debugging request, and acquiring a debugging enabling signal;

and step 3: determining an executable domain allowed to enter a debugging mode according to the debugging enabling signal;

and 4, step 4: the control processor enters a super user mode and debugs the executable domain that is allowed to enter a debug mode.

As can be seen from the above description, in the embodiment of the present application, the processor is controlled to enter the super user mode to debug the executable domain, instead of using the machine mode to regulate and control the executable domain, so that the security in the debugging process can be effectively improved, a debugging enable signal is set to indicate which executable domains need to be debugged, and the requirement for independent debugging of a single executable domain can be met, thereby meeting the requirement for debugging isolation in security debugging.

Embodiments of the present application further provide a computer-readable storage medium capable of implementing all steps in the debugging method of the processor in the foregoing embodiments, where the computer-readable storage medium stores thereon a computer program, and when the computer program is executed by the processor, the computer program implements all steps of the debugging method of the processor in the foregoing embodiments, for example, when the processor executes the computer program, the processor implements the following steps:

step 1: acquiring a debugging request;

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the hardware + program class embodiment, since it is substantially similar to the method embodiment, the description is simple, and the relevant points can be referred to the partial description of the method embodiment.

The foregoing description has been directed to specific embodiments of this disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

Although the present application provides method steps as described in an embodiment or flowchart, additional or fewer steps may be included based on conventional or non-inventive efforts. The order of steps recited in the embodiments is merely one manner of performing the steps in a multitude of orders and does not represent the only order of execution. When an actual apparatus or client product executes, it may execute sequentially or in parallel (e.g., in the context of parallel processors or multi-threaded processing) according to the embodiments or methods shown in the figures.

The systems, devices, modules or units illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions. One typical implementation device is a computer. In particular, the computer may be, for example, a personal computer, a laptop computer, a vehicle-mounted human-computer interaction device, a cellular telephone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

Although embodiments of the present description provide method steps as described in embodiments or flowcharts, more or fewer steps may be included based on conventional or non-inventive means. The order of steps recited in the embodiments is merely one manner of performing the steps in a multitude of orders and does not represent the only order of execution. When an actual apparatus or end product executes, it may execute sequentially or in parallel (e.g., parallel processors or multi-threaded environments, or even distributed data processing environments) according to the method shown in the embodiment or the figures. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the presence of additional identical or equivalent elements in a process, method, article, or apparatus that comprises the recited elements is not excluded.

For convenience of description, the above devices are described as being divided into various modules by functions, and are described separately. Of course, in implementing the embodiments of the present description, the functions of each module may be implemented in one or more software and/or hardware, or a module implementing the same function may be implemented by a combination of multiple sub-modules or sub-units, and the like. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

Those skilled in the art will also appreciate that, in addition to implementing the controller as pure computer readable program code, the same functionality can be implemented by logically programming method steps such that the controller is in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Such a controller may therefore be considered as a hardware component, and the means included therein for performing the various functions may also be considered as a structure within the hardware component. Or even means for performing the functions may be regarded as being both a software module for performing the method and a structure within a hardware component.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.

Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.

As will be appreciated by one skilled in the art, embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, embodiments of the present description may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present description may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and so forth) having computer-usable program code embodied therein.

The embodiments of this specification may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The described embodiments may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment. In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of an embodiment of the specification. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

The above description is only an example of the embodiments of the present disclosure, and is not intended to limit the embodiments of the present disclosure. Various modifications and variations to the embodiments described herein will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present specification should be included in the scope of the claims of the embodiments of the present specification.

Claims

1. A method for debugging a processor, comprising:

acquiring a debugging request;

responding to the debugging request, and acquiring a debugging enabling signal;

2. The method of claim 1, after obtaining the debug request, further comprising:

responding to the debugging request, and acquiring a debugging control signal;

determining whether the processor is required to enter a debugging state in a machine mode according to the debugging control signal;

controlling the processor to enter a debug state in machine mode if it is determined that the processor is required to enter the debug state in machine mode;

in the event that it is determined that the processor is not required to enter a debug state in machine mode but the processor is currently in machine mode, controlling the processor to enter a debug wait state.

3. The method of claim 2, wherein obtaining a debug enable signal in response to the debug request comprises:

the debug enable signal is obtained if it is determined that the processor is not required to enter a debug state in machine mode and the processor is not currently in machine mode.

4. The method of claim 1, wherein the debug enable signal is characterized by a signal line established between a debug authentication module and a processor.

5. The method of claim 4, wherein a signal line corresponds to an executable domain, and wherein the pulling of the level of the signal line of the target executable domain indicates that the target executable domain is allowed to enter the debug mode.

6. The method of claim 1, wherein obtaining a debug enable signal comprises:

and calling a debugging enabling signal from the memory, wherein the debugging enabling signal is stored in the memory in a message mechanism mode.

7. The method of any of claims 1 to 6, wherein the processor is a RISC-V processor architecture based processor that provides the capability to implement a trusted execution environment.

8. A debugging system for a processor, comprising:

the processor virtualizes a plurality of independent executable domains;

9. The system of claim 8, wherein the debug authentication module is coupled to the processor via a plurality of signal lines, one signal line corresponding to each executable domain, and wherein the signal lines of a target executable domain are pulled high to indicate that the target executable domain is allowed to enter the debug mode.

10. The system of claim 8, wherein the debug authentication module is further configured to set a debug enable signal via a signal line with the processor, the debug enable signal being used to characterize whether the processor needs to enter a debug state in machine mode.

11. The system of claim 8, wherein the processor is a reduced architecture instruction set based processor.

12. A system-on-chip comprising the debug system of the processor of any of claims 8 to 11.

13. A computer readable storage medium having stored thereon computer instructions which, when executed, implement the steps of the method of any one of claims 1 to 7.