CN113986637A

CN113986637A - UVM-based Level-2 market decoding circuit verification excitation generation method and verification platform

Info

Publication number: CN113986637A
Application number: CN202111370597.5A
Authority: CN
Inventors: 余乐; 张世伟; 李亚祺; 赵嵩
Original assignee: Beijing Technology and Business University
Current assignee: Beijing Technology and Business University
Priority date: 2021-11-18
Filing date: 2021-11-18
Publication date: 2022-01-28

Abstract

The invention relates to a UVM-based Level-2 market decoding circuit verification excitation generation method. The method includes the STEPs of generating an excitation, randomizing, assembling a STEP structure message, and the like. The UVM-based Level-2 market decoding circuit verification excitation generation method can generate verification excitation conforming to the Level-2 market definition specification, and can assist verification personnel to quickly build a verification platform for the Level-2 market decoding circuit. The excitation generation method can generate the affair containing the expected output, simplifies the implementation process of the reference model, and the reference model only needs to position the part of the message body in the STEP affair and take out the part of the message body, so that the expected output of the score counting plate can be obtained. Meanwhile, the excitation generation method can simplify the process that the driver drives the transaction into a pin-level signal, and the first byte sequence can be directly driven to the input end of the circuit to be tested by the driver.

Description

UVM-based Level-2 market decoding circuit verification excitation generation method and verification platform

Technical Field

The invention relates to a UVM-based Level-2 market decoding circuit verification excitation generation method and a verification platform, and belongs to the technical field of digital circuits.

Background

Level-2 is a market product introduced by Shanghai securities exchange, and market data is transmitted by a financial information exchange protocol adopting compression coding. The components are a STEP head, FAST message data and a STEP tail in sequence. Step (security Trading Exchange protocol) is a data Exchange protocol part of securities Trading, and fast (fix Adapted for Trading) data is a compressed coding part and contains real market information. The STEP protocol portion of the market data is organized in a "field = value" format. FAST data contains only "values," whose "fields" are stripped from the delivered market, exist as message templates, and are known to both the sender and the receiver. Another characteristic of FAST data is that the "value" of each "field" in the message template is not delivered in full, and redundant "field" values are discarded as needed for the actual market data.

In real-disk trading, the speed of the market system directly determines the transaction rate of the customer and the amount of income. Currently, security dealer has begun to develop market decoding circuits that can be adapted to Level-2. The market decoding circuit has the main functions of decoding Level-2 market data, extracting FAST data, and decoding the values corresponding to the fields of the market transmitted currently according to the message template to recover complete market information. Level-2 market data has the characteristics of complex data structure and flexible and diverse transmitted information, and a digital circuit capable of decoding the Level-2 market is large in scale and complex in function. And relates to the development of securities business, and the designed digital circuit is required to have ultrahigh reliability and stability. The designed market hardware circuit is usually verified using UVM (universal verification methodology).

In the prior art, CN112486835A provides a UVM verification platform and method applied to stock counters. However, the content of the technical scheme only focuses on the futures counter verification realized based on the FPGA, and the input stimulus of the technical scheme cannot randomly generate FAST data transmitted by the STEP protocol, so that the technical scheme cannot cover the verification scene of Level-2 market.

To verify Level-2 market decoding circuits using UVM, attention is paid not only to how each "field" is constrained to generate random excitation, but also to various combinations of "fields" of FAST data portions. If one transaction is defined for each combination of "fields", then multiple transactions are required for the same message type to cover all combinations of FAST "fields". Different message types also have different message templates, and the above traditional random excitation generation mode needs huge workload, so that the overall verification efficiency is reduced. There is also a risk of missing individual "field" combinations, reducing verification reliability. Meanwhile, most of the existing verification schemes directly generate an incentive to be decoded by referring to the functional description of the design requirement. To obtain the desired output, the implementation details of the reference model need to be consistent with the circuit to be tested, which may increase the development difficulty and cycle of the verification platform to some extent.

Disclosure of Invention

The invention aims to solve the technical problems that: the defects of the technology are overcome, and a UVM-based Level-2 market decoding circuit verification excitation generation method is provided; and on the basis, a Level-2 market decoding circuit verification platform capable of reducing development difficulty and development period is provided.

In order to solve the above technical problem, a first technical solution proposed by the present invention is: a UVM-based Level-2 market decoding circuit verification excitation generation method comprises the following steps:

(1) uvm _ test starts a verification case with uvm _ do to cause the sequence generator to start generating a STEP transaction; STEP transaction selects a FAST message class; the FAST message class comprises a presence bitmap sequence and fields corresponding to the sequence of the presence bitmap sequence one by one;

(2) FAST message class randomization exists bitmap sequences and fields; the existing bitmap sequence is pressed into a second byte queue; pressing the corresponding field with the bitmap sequence identification as valid into a second byte queue;

(3) generating a message head by the STEP transaction, and pressing the message head into a first byte queue;

(4) the STEP affairs take out the second byte queue in the FAST message class and press the second byte queue into the first byte queue;

(5) the STEP transaction generates a message trailer that is pushed into the first byte queue.

The scheme is further improved in that: the STEP transaction inherits from an uvm _ sequence _ item base class, and internally generates a message header and a message tail which conform to the STEP protocol by using string type definition, thereby ensuring that the message header and the message tail are in an ASCII encoding form when being pressed into a byte queue.

The scheme is further improved in that: defining a random type existence bitmap sequence and a specific FAST message template in the FAST message class; the FAST message template consists of field variables corresponding to the template, and each field variable is of a random type; each field variable in the FAST message template has constraints that are compliant with the exchange specifications.

The scheme is further improved in that: the STEP transaction and FAST message class has the function of writing out the currently generated message data to a local file; the written message data is in a state before being pushed into the byte queue.

In order to solve the above technical problem, a second technical solution proposed by the present invention is: a UVM-based Level-2 market decoding circuit verification platform comprises: uvm _ test, sequence generator, and environment components;

the uvm _ test is responsible for configuring different verification cases and starting a sequence generator corresponding to the verification cases; instantiating each component of the verification platform according to the uvm tree-shaped hierarchical structure by taking the root node as the root node;

the sequence generator generates corresponding random excitation, namely STEP transaction according to the verification case configured by uvm _ test;

the environment component comprises an input agent, an output agent, a reference model and a scoring board;

the input agent is instantiated in an environment component and comprises a sequence launcher and a driver;

the sequence initiator is responsible for transmitting the STEP transaction generated by the sequence generator to the driver;

the driver receives the STEP affair transmitted by the sequence initiator and transmits the message data contained in the STEP affair to the input port of the circuit to be tested and the reference model through the interface layer;

the export agent instantiated in an environment component, comprising a monitor;

the monitor receives the pin-level signal output by the circuit to be tested through the interface layer and converts the pin-level signal into a transaction; and sent as actual output to the scoreboard;

the reference model extracts the FAST message data from the STEP transactions generated by the sequence generator and sends it as the desired output to the scoreboard;

and the score board compares whether the expected output is consistent with the actual output, if so, the function of the circuit to be tested is judged to be in accordance with the design requirement, otherwise, the function of the circuit to be tested is judged to be not in accordance with the design requirement, and the verification process is interrupted.

The interface layer is connected with the input port, the output port and the verification platform of the circuit to be tested; and defining according to the input/output port required by the design of the circuit to be tested.

The scheme is further improved in that: the driver takes out the byte queue in the STEP transaction, converts the byte queue into a pin-level signal and sends the pin-level signal to an input port of a circuit to be tested through the interface layer; the reference model receives the STEP transaction passed by the driver through uvm _ tlm _ analysis _ fifo and, through the field information within the transaction, takes the parts in the FAST message data to combine into the desired output.

The scheme is further improved in that: the STEP affairs keep the field information of the STEP protocol and the FAST message template in Level-2 market; with the aid of the field information, FAST message data as a message body in a STEP transaction can be directly output as desired.

The UVM-based Level-2 market decoding circuit verification excitation generation method can generate verification excitation conforming to the Level-2 market definition specification, and can assist verification personnel to quickly build a verification platform for the Level-2 market decoding circuit. The excitation generation method can generate the affair containing the expected output, simplifies the implementation process of the reference model, and the reference model only needs to position the part of the message body in the STEP affair and take out the part of the message body, so that the expected output of the score counting plate can be obtained. Meanwhile, the excitation generation method can simplify the process that the driver drives the transaction into a pin-level signal, and the first byte sequence can be directly driven to the input end of the circuit to be tested by the driver.

Drawings

The invention will be further explained with reference to the drawings.

FIG. 1: FAST message class definition structure diagram.

FIG. 2: STEP transaction definition structure diagram.

FIG. 3: UVM-based Level-2 market decoding hardware circuit verification excitation generation method flow chart.

FIG. 4: and (5) a schematic structural diagram of the verification platform.

Detailed Description

Examples

The verification excitation generating method for the UVM-based Level-2 market decoding circuit in this embodiment, as shown in FIG. 3, includes the following steps:

s1: uvm _ test starts a verification case, with uvm _ do to make the sequencer start to generate stimuli, i.e., a STEP transaction, which instantiates a FAST message class;

s2: a FAST message class randomizes a presence bitmap sequence 101 and a FAST message template 102; there is a bitmap sequence 101 pushed into the byte queue 103; determining which field in the FAST message template to push into the byte queue 103 based on the randomized presence bitmap sequence;

s3: the STEP header template 205 generates a message header and pushes the message header into the byte queue 204;

s4: the instantiated FAST message 203 pushes the byte queue 103 to the byte queue 204 as a message body;

s5: STEP tail template 206 generates a message tail and pushes the message tail into byte queue 204.

The FAST message class definition structure is shown in fig. 1. The FAST message class includes a presence bitmap sequence 101, a FAST message template 102, a byte queue 103, and a FAST data write-out module 104. The length of the bitmap sequence 101 is consistent with the number of fields in the FAST message template 102, and the sequence corresponds to the fields one by one. The presence bitmap sequence 101 is used to indicate whether the corresponding fields in the FAST message template 102 are pushed to the byte queue and whether their content is written out to the local file by the FAST data write-out module 104, with both valid and invalid states. The various fields in the FAST message template 102 are random values and each field has constraints that are compliant with the exchange specification.

The internal definition structure of the STEP transaction is shown in fig. 2. A STEP transaction inherits from the uvm _ sequence _ item base class, including defined several FAST message classes, selection instantiation 201, weight control 202, instantiation FAST message 203, byte queue 204, STEP header template 205, STEP tail template 206. Where selecting instantiation 201 will instantiate a specified proportion of FAST message classes according to weight control 202. Only one FAST message class is selected for instantiation per instantiation operation and exists in the STEP transaction as an instantiated FAST message class 203. The byte queue 204 is composed of three parts, a message header, a message body, and a message trailer. Data generated by the STEP head template 205 is first pushed into the byte queue 204 as a message head, then the byte queue 103 in the instantiated FAST message 203 is pushed into the byte queue 204 as a message body, and finally data generated by the STEP tail template 205 is pushed into the byte queue 204 as a message tail.

Specifically, the post _ random function in the STEP transaction completes the process of the byte queue 204 pushing the message header, the message body, and the message trailer, the execution process being triggered by uvm _ do in uvm _ test. And generating a message head and a message tail which conform to the STEP protocol by using string type definition in the STEP transaction, and ensuring that the message head and the message tail are in an ASCII (American standard code for information interchange) encoding form when being pressed into the byte queue.

In the verification platform of this embodiment, as shown in fig. 4, the internal components include: uvm _ test401, sequence generator 402, and environment component 403. Wherein the environment component 403 comprises: input agent 404, reference model 405, scoreboard 406, output agent 407. Included in the input agent 404 are a sequence launcher 408 and a driver 409. The output agent 407 includes a monitor 410 therein. uvm _ test401 is implemented in the top level file with the circuit 411 under test.

The sequence generator 402 is connected to a sequence initiator 408. The sequence initiator 408 is connected to a driver 409. One path of the driver 409 is connected to the input terminal of the circuit to be tested 411 through the interface layer, and the other path is connected to the reference model 405. The reference model 405 output is connected to a scoreboard 406. The output terminal of the circuit to be tested 411 is connected to the monitor 410 through the interface layer. The monitor 410 output is connected to the scoreboard 406.

uvm _ test401 configures different verification cases for the environment component 403. The sequence generator 402 generates stimuli corresponding to the message type according to the configured verification case.

The STEP transaction generated by sequence generator 402 is sent to driver 409 via sequence initiator 408. The driver 409 takes out the byte queue 204 in the STEP transaction, processes the byte queue into a pin-level signal, and sends the pin-level signal to the circuit to be tested 411 through the interface layer. Meanwhile, the driver 409 sends the reference model 405 after copying the STEP transaction. The reference model 405 extracts the FAST message part from the STEP transaction as the expected output to the scoreboard 406. The monitor 410 collects the output of the circuit 411 under test and sends it to the scoreboard 406 as the actual output. The score board 406 compares the expected output with the actual output to determine whether the function of the circuit under test is correct.

The driver 409 communicates with the reference model 405, the reference model 405 communicates with the score board 406, and the monitor 410 communicates with the score board 406 in a transaction-level communication manner, and is connected through uvm _ tlm _ analysis _ fifo.

The STEP transaction and FAST message class has the function of writing out the currently generated message data to a local file; the written message data is in a state before being pushed into the byte queue, namely, is presented in a plaintext form. Can be used as a reference for manual interpretation.

Specifically, when the circuit 411 is verified by the verification platform, the sequence generator 402 generates a plurality of random stimuli, i.e., a plurality of STEP transactions, in a cycle. The weight control 202 causes the STEP transaction generated each time to instantiate a different FAST message class, i.e., generate Level-2 market data of a different message type, thereby enabling authentication of different message types. The FAST message class instantiated in the STEP transaction will push the random value of the valid field into the byte queue 103 as the message body part of the byte queue 204, as indicated by the randomized presence bitmap sequence 101. Instantiating the same FAST message class for multiple times, wherein each message class can randomly generate different existing bitmap sequences 101, and the types and the number of effective fields can be changed correspondingly, so that the verification of different field combinations under the same message type is realized. Therefore, the verification scene of the market data of different message types and the market data of different field combinations of the same message can be covered step by step only by increasing the cycle times of the random excitation generated by the sequence generator 402.

The present invention is not limited to the above-described embodiments. All technical solutions formed by equivalent substitutions fall within the protection scope of the claims of the present invention.

Claims

1. A UVM-based Level-2 market decoding circuit verification excitation generation method is characterized by comprising the following steps:

2. The UVM-based Level-2 market decoding circuit verification excitation generation method of claim 1, wherein: the STEP transaction inherits from an uvm _ sequence _ item base class, and a message header and a message tail which conform to a STEP protocol are generated by string type definition inside the STEP transaction, so that the STEP transaction is ensured to be in an ASCII encoding form when being pressed into a byte queue; the first byte queue in the STEP transaction is used to store and deliver the header, body and trailer to the drive.

3. The UVM-based Level-2 market decoding circuit verification excitation generation method of claim 1, wherein: defining a random type existence bitmap sequence and a specific FAST message template in the FAST message class; the FAST message template consists of field variables corresponding to the template, and each field variable is of a random type; each field variable in the FAST message template has a constraint which is in accordance with the exchange specification; the FAST message class will be instantiated in the STEP transaction to produce a randomized message body part.

4. The UVM-based Level-2 market decoding circuit verification excitation generation method of claim 1, wherein: the STEP transaction and FAST message class has the function of writing out the currently generated message data to a local file; the written message data is in a state before being pressed into the byte queue; i.e. in the clear; can be used as a reference for manual interpretation.

5. A verification platform for applying the UVM-based Level-2 market decoding circuit verification stimulus generation method of claim 1, comprising: uvm _ test, sequence generator, and environment components;

the score board compares whether the expected output is consistent with the actual output, if so, the function of the circuit to be tested is judged to be in accordance with the design requirement, otherwise, the function of the circuit to be tested is judged to be not in accordance with the design requirement, and the verification process is interrupted;

6. The verification platform of claim 5, wherein: the driver takes out the byte queue in the STEP transaction, converts the byte queue into a pin-level signal and sends the pin-level signal to an input port of a circuit to be tested through the interface layer; the reference model receives the STEP transaction passed by the driver through uvm _ tlm _ analysis _ fifo and, through the field information within the transaction, takes the parts in the FAST message data to combine into the desired output.

7. The verification platform of claim 5, wherein: the STEP affairs keep the field information of the STEP protocol and the FAST message template in Level-2 market; with the aid of the field information, FAST message data as a message body in a STEP transaction can be directly output as desired.