CN113986354A - RISC-V instruction set based six-stage pipeline CPU - Google Patents
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Abstract
The invention discloses a six-stage pipeline CPU based on RISC-V instruction set, which can realize RV32I basic instruction set, multiplication instruction and CSR read-write instruction, and sets an interrupt register to suspend the pipeline; the CPU has the remarkable characteristics of a six-level pipeline structure which is respectively an IF level, an FD level, a CSG level, an EXE level, an MEM level and a WB level and has higher dominant frequency; related circuits are designed for solving the hazard problem in the pipeline; the data hazard is solved by utilizing internal forward pushing, the load _ use hazard is solved by utilizing a pipeline suspension method, and the control hazard is solved by utilizing a static prediction method. The CPU has the characteristics of small area, low power consumption and multiple functions, and can be widely applied to the fields of Internet of things and embedding.
Description
Technical Field
The invention belongs to the field of processor design, and particularly relates to a six-stage pipeline CPU based on a RISC-V instruction set.
Background
The RISC-V ISA is an open instruction set architecture completed by a Berkeley division school related team of California university, RISC represents a reduced instruction set computer, and V represents a fifth generation, so the architecture is built based on a reduced instruction set computing principle. Compared to most instruction sets, the RISC-V instruction set has the characteristics of being completely free and open source, allowing anyone to design, manufacture and sell RISC-V instruction set based chips and software. Nowadays, a microprocessor based on a RISC-V instruction set is widely used in an internet of things terminal due to its advantages of low power consumption and open source.
There are many foreign researches on the RISC-V instruction set, and various open-source RISC-V processors are designed and widely used. For the domestic RISC-V processor design, hummingbird E203 has to be mentioned, which is the first national fully open-source low-power processor based on the RISC-V instruction set. The designer Hu-Sha wave et al, based on the design objective of the ultra-low power consumption embedded application, takes the compromise requirements of power consumption and performance into consideration, and adopts a pipeline structure with two stages of sequential pipelines as a main body and variable pipeline lengths of other components as an auxiliary body. And finally, running a program test, and comparing the test result with an ARM Cortex-M microcontroller, wherein the comparison result shows that the product can be applied to the IoT low-power-consumption scene. In addition, many research teams have designed a variety of microprocessors based on the RISC-V instruction set, including out-of-order execution processors, floating-point processors, specialized metering processors, and the like.
Although there are various domestic processors, the stage division of the pipeline is not fine enough, which greatly affects the execution efficiency of the CPU, and the main frequency and instruction throughput of the CPU are greatly reduced. Like the more popular domestic hummingbird E203 processor, there are only two levels of pipeline structures, which make the CPU with low master frequency and throughput. Therefore, to obtain higher main frequency and higher instruction throughput, the CPU with the multi-stage pipeline structure is the focus of research.
Disclosure of Invention
The invention aims to provide a six-stage pipeline CPU based on a RISC-V instruction set.
The technical solution for realizing the purpose of the invention is as follows: a RISC-V instruction set based six-stage pipelined CPU comprising:
an instruction fetch circuit for generating a next instruction address and fetching an instruction of a current address;
the field decoding circuit is used for decoding the instruction field and detecting load _ use hazard;
the control signal generating circuit is used for generating a control signal of an instruction and reading the general register according to the rs1 and rs2 field addresses;
the instruction execution circuit is used for performing operation of the instruction, solving data hazard and controlling hazard;
memory access circuitry for accessing memory, primarily for load and store instructions;
and the result write-back circuit is used for writing the data result into the register file, reading and writing the CSR register and generating an interrupt signal.
Compared with the prior art, the invention has the following remarkable advantages:
(1) the CPU has a six-stage pipeline structure, and each stage of circuit is more finely divided, so that the execution time of each stage of circuit is greatly reduced, and the main frequency of the CPU is greatly improved;
(2)20 the CPU has higher execution efficiency and higher instruction throughput, and can execute more instructions at the same time compared with other processors;
(3) the static prediction structure is adopted to solve the control hazard, and the circuit is simple and easy to control.
The present invention is described in further detail below with reference to the attached drawing figures.
Drawings
Fig. 1 is a circuit diagram of a pipelined IF stage.
Fig. 2 is a circuit diagram of a pipeline FD stage.
Fig. 3 is a circuit diagram of a pipeline CSG stage.
FIG. 4 is a circuit diagram of EXE stage of the pipeline.
Fig. 5 is a circuit diagram of a pipeline WB stage.
Fig. 6 is a six-stage pipelined CPU circuit diagram.
FIG. 7 is a circuit diagram of the first three stages of a pipeline CPU.
FIG. 8 is a circuit diagram of the last three stages of the pipeline CPU.
Detailed Description
A six-stage pipeline CPU based on RISC-V Instruction set divides a six-stage pipeline structure, which is respectively an Instruction Fetch (IF) stage, a Field Decoding (FD) stage, a Control Signal Generation (CSG) stage, an Instruction execution (EXE) stage, a Memory access (MEM) stage and a Result write-back (WB) stage.
The instruction fetching IF stage circuit generates a next instruction address and fetches an instruction of a current address;
the field decoding FD stage circuit decodes the instruction field and detects load _ use hazard;
the control signal generation CSG level circuit generates a control signal of an instruction and reads the general register according to the rs1 and rs2 field addresses;
the instruction executes the EXE-level circuit, performs operation on the instruction, and solves data hazards and control hazards;
the memory accesses MEM stage circuitry, accesses memory, primarily for load and store instructions;
and the result is written back to the WB-level circuit, the data result is written into the register file, the CSR register is read and written, and an interrupt signal is generated.
Further, the IF stage circuit includes:
an instruction address generation module: after 4 is added to both the current pc and the jump pc, the current pc and the jump pc are input to a data selector imux1, a pc _ sel generation module generates a control signal pc _ sel of imux1, and imux1 outputs a next instruction address to a pc counter;
an instruction fetching module: a selector imux2 for selecting proper address as ITCM address end input, and the instruction memory ITCM stores program instruction;
pc buffer: as inter-stage registers of the IF stage and the FD stage, the pc value of the IF stage is output to the FD stage of the next stage.
Further, the FD stage circuit includes:
an instruction output module: selecting a cache instruction or a current instruction to be used by a decoding module, outputting the cache instruction when load _ use hazard occurs and needs to be suspended, and directly using the output instruction of the ITCM when no hazard exists;
a decoding module: receiving an instruction signal transmitted by the instruction module, carrying out field decoding, and outputting a decoding signal; load _ use detection unit: the load _ use hazard is detected and a suspend signal stall and discard signal discard are output, the suspend signal suspends the IF stage and the FD stage, and the discard signal discards the CSG stage instruction.
Further, the CSG level circuitry comprises:
a register reading module: the two register reading modules output register reading signals rf _ rs1 and rf _ rs2 according to decoding signals crs1 and crs2 transmitted from the FD stage and register file related signals transmitted from the WB stage.
A control component module: five control signals are generated according to the instruction operation code opcode, output to the inter-stage register CSG/EXE reg, and flow into the EXE stage in the next clock cycle.
Further, the EXE stage circuit comprises:
a forward push circuit: the bypass detection unit is composed of two selectors and a bypass detection unit. And the bypass detection unit judges the occurrence of data hazard according to related signals returned by the WB stage and the MEM stage and outputs control signals of the two selectors. The data selector selects different data to output according to the control signal. The bypass detection unit detects data hazards, and the data hazards occurring with the MEM stage are called MEM stage hazards, and the data hazards occurring with the WB stage are called WB stage hazards. The conditions under which the MEM-level data hazard occurs are as follows: the MEM level instruction has a write register file function and the destination address is equal (not zero) to the source address of the EXE level instruction. The conditions under which the WB level data hazard occurs are as follows: the WB stage instruction has a write register file function and the destination address is equal (not zero) to the source address of the EXE stage instruction.
An ALU component: and performing instruction operation, selecting different operations according to different instructions, and outputting an operation result to the next stage.
A static prediction circuit: and determining a jump address and jump execution at an EXE level, wherein a jump address generating module generates a jump address pc _ jump, a jump _ en generating module generates a jump execution signal jump _ en, and the jump execution signal jump _ en are delayed to the next level. At the MEM stage, a jump address signal and a jump execution signal are passed to the IF stage, causing the IF stage to fetch instructions based on the jump address. At this point, the three instructions following the jump instruction have entered the pipeline, requiring the three instructions to be discarded. The abandonment of the instruction can prevent the instruction from rewriting the CPU state only by clearing the control signal of the instruction, thereby achieving the purpose of abandonment. The control signal zero clearing needs to be carried out by three steps of bit splicing, judgment and operation.
Further, the MEM stage circuit comprises:
a data memory: the data memory DTCM stores load and lw instruction usage data.
Further, the WB stage circuit includes:
a register file: 32 general integer registers.
Interrupt register minterropt: the register address is 0x000, and the minterropt outputs an interrupt signal intr _ done to the control end of the PC counter, so that the output of the PC counter is kept unchanged, and the purpose of pausing the pipeline is achieved.
The invention is explained in detail below with reference to the figures and the examples.
Examples
The pipeline IF stage circuit is shown in figure 1 and comprises an instruction address generation module, an instruction fetching module and a pc cache module. The working flow of the IF stage circuit is as follows: in the instruction address generating module, 4 is added to the current PC and the jump PC and then the added value is input to the data selector imux1, the PC _ sel generating module generates a control signal PC _ sel of imux1, and the imux1 outputs the next instruction address to the PC counter. In the instruction fetching module, a selector imux2 selects a proper address as an ITCM address end input, and the ITCM outputs an instruction according to the input address. The PC buffer may also serve as an inter-stage register for the IF stage and the FD stage, outputting the PC value of the IF stage to the next FD stage.
The FD stage circuit of the assembly line is shown in figure 2 and comprises a load _ use detection unit, an instruction output module and a decoding module. The working flow of the FD stage circuit is as follows: the load _ use detection unit detects load _ use hazard and outputs a pause signal stall and a discard signal discard, wherein the pause signal suspends an IF stage and an FD stage, and the discard signal discards a CSG stage instruction; the instruction output module selects a proper instruction to be used by the decoding module, outputs a cache instruction when load _ use hazard occurs and needs to be suspended, and directly uses the output instruction of the ITCM when no hazard exists; the decoding module receives the instruction signal transmitted by the instruction module, performs field decoding, outputs a decoding signal, and writes the decoding signal into the inter-segment register FD/CFP reg at the end of a cycle (at the rising edge of a clock).
The flow line CSG stage circuit is shown in figure 3 and comprises an rs1 register reading module, an rs2 register reading module and a control part. The CSG level circuit work flow is as follows: the two register reading modules output register reading signals rf _ rs1 and rf _ rs2 according to decoding signals crs1 and crs2 transmitted from the FD stage and register file related signals transmitted from the WB stage; the control part generates five control signals, namely a register file write signal, a memory read-write signal, an ALU calculation signal, a CSR read-write instruction signal and a WB level data selection signal according to the instruction operation code opcode, and outputs the control signals to the inter-stage register CSG/EXE reg.
The EXE stage circuit of the pipeline is shown in figure 4 and comprises a forward circuit, a static prediction circuit and an ALU calculation circuit. The EXE-level circuit work flow is as follows: the forward circuit detects data hazards through a bypass detection unit and outputs proper data serving as source operands of the ALU component according to a detection result; the ALU performs instruction operation, selects different operations according to different instructions, and outputs an operation result to the next stage; the static prediction circuit solves the control hazard, and clears the control signal of the level of instruction when the hazard occurs; in addition, the CSR module generates CSR register related signals.
The push-forward circuit is composed of two selectors and a bypass detection unit. And the bypass detection unit judges the occurrence of data hazard according to related signals returned by the WB stage and the MEM stage and outputs control signals of the two selectors. The data selector selects different data to output according to the control signal.
The bypass detection unit detects data hazards, and the data hazards occurring with the MEM stage are called MEM stage hazards, and the data hazards occurring with the WB stage are called WB stage hazards.
The two data selectors are muxa and muxb, respectively. muxa selects ALU a port input data and directly selects rs1 register to read contents without data hazard. muxb selects ALU b port input data and directly selects rs2 register to read contents without data hazard.
The static prediction circuit determines a jump address and jump execution at an EXE level, wherein a jump address generating module generates a jump address pc _ jump, a jump _ en generating module generates a jump execution signal jump _ en, and the two signals are delayed to the next level. At the MEM stage, a jump address signal and a jump execution signal are passed to the IF stage, causing the IF stage to fetch instructions based on the jump address. At this point, the three instructions following the jump instruction have entered the pipeline, requiring the three instructions to be discarded. The abandonment of the instruction can prevent the instruction from rewriting the CPU state only by clearing the control signal of the instruction, thereby achieving the purpose of abandonment. The control signal zero clearing needs to be carried out by three steps of bit splicing, judgment and operation.
The pipelined MEM stage circuit consists of a data register DTCM, which enables access to the data memory.
The pipeline WB stage circuit is shown in figure 5 and comprises a register file writing module and an interrupt register writing module. For the interrupt register write module, if the CSR read-write instruction is used, the read-write address is 0x000, the minterrupt interrupt register is written, and an interrupt signal intr _ done is output to suspend the pipeline.
And the register file writing module consists of a register file, a data selector and a regfile _ en generation module. The data selector selects the appropriate data as the write data for the register file, and the regfile _ en generation module generates control signals for the register file that writes the data at the end of the cycle (at the rising edge of the clock).
The two alternative data selectors are wmux1 and wmux2, respectively. Control signal aluormem _ sel is used as the select signal of wmux1, control signal wcsr _ wr is used as the select signal of wmux2, and the output wmux2_ out of the wmux2 selector is used as the write data of the register file. The regfile _ en generation module outputs an enable signal regfile _ en of the register file according to the destination address wrd of the instruction and the control signal wregfile _ wr. The register file writes data at the rising edge of the clock and outputs the value of each register.
The whole circuit of the pipeline CPU is shown in figures 6, 7 and 8, wherein figure 7 is a front three-stage circuit, and figure 8 is a rear three-stage circuit. Each stage circuit performs a different function and outputs a relevant signal to the next stage through the inter-stage register. The intersegment register connects each stage of circuits in sequence, so that the execution of the instruction becomes orderly and efficient. The whole pipeline CPU work flow is as follows: the IF stage fetches an instruction and outputs the address of the next instruction; the FD stage decodes the instruction field and outputs the decoded instruction field to the next stage; the CSG level generates a control signal of the instruction according to the decoding signal, and the control signal influences the operation of the subsequent circuit part; the EXE stage completes the calculation task of the instruction according to the decoding and control signal; the MEM stage performs accesses to memory by instructions; the WB stage writes the results of the previous calculation or read of the instruction into the register file. In addition, a data hazard processing circuit and a control hazard processing circuit are added, so that the hazard is effectively solved. Therefore, the pipeline divides the execution content of the instruction finely, and the front and the back are closely associated, so that the high-efficiency execution of the CPU is ensured.
After the instructions have filled the pipeline, at each clock rising edge, execution of instructions from the WB stage is complete and new instructions are input from the IF stage. At the same time, six instructions are processed in the production line, and the execution speed of the CPU is greatly improved.
It should be noted that, for those skilled in the art, various modifications and equivalents can be made without departing from the principle of the present invention, and those modifications and equivalents of the claims are intended to fall within the scope of the present invention.
Claims (7)
1. A RISC-V instruction set based six-stage pipelined CPU comprising:
an instruction fetch circuit for generating a next instruction address and fetching an instruction of a current address;
the field decoding circuit is used for decoding the instruction field and detecting load _ use hazard;
the control signal generating circuit is used for generating a control signal of an instruction and reading the general register according to the rs1 and rs2 field addresses;
the instruction execution circuit is used for performing operation of the instruction, solving data hazard and controlling hazard;
memory access circuitry for accessing memory, primarily for load and store instructions;
and the result write-back circuit is used for writing the data result into the register file, reading and writing the CSR register and generating an interrupt signal.
2. A RISC-V instruction set based six-stage pipelined CPU as claimed in claim 1 wherein said instruction fetch circuit comprises:
an instruction address generation module: after 4 is added to both the current pc and the jump pc, the current pc and the jump pc are input to a data selector imux1, a pc _ sel generation module generates a control signal pc _ sel of imux1, and imux1 outputs a next instruction address to a pc counter;
an instruction fetching module: adopting a selector imux2, selecting a proper address as an ITCM address end input, and storing program instructions in an instruction memory ITCM;
pc buffer: the inter-stage register as an instruction fetch circuit and a field decode circuit outputs the pc value of the instruction fetch circuit to a next stage field decode circuit.
3. A RISC-V instruction set based six-stage pipelined CPU as claimed in claim 2 wherein said field decoding circuit comprises:
an instruction output module: selecting a cache instruction or a current instruction to be used by a decoding module, outputting the cache instruction when load _ use hazard occurs and needs to be suspended, and directly using the output instruction of the ITCM when no hazard exists;
a decoding module: receiving an instruction signal transmitted by the instruction module, carrying out field decoding, and outputting a decoding signal;
load _ use detection unit: detecting load _ use hazard, outputting a pause signal stall and a discard signal discard, pausing a signal pause instruction fetching circuit and a field decoding circuit, and generating a circuit instruction by a discard signal discard control signal.
4. A RISC-V instruction set based six-stage pipelined CPU as claimed in claim 3, wherein said control signal generating circuit comprises:
a register reading module: the two register reading modules output register reading signals rf _ rs1 and rf _ rs2 according to decoding signals crs1 and crs2 transmitted from the field decoding circuit and register file related signals transmitted from WB stages;
a control component module: five control signals are generated according to the instruction operation code opcode, output to the intersegment register CSG/EXEreg, and flow into the instruction execution circuit in the next clock cycle.
5. A RISC-V instruction set based six-stage pipelined CPU as recited in claim 4, wherein the instruction execution circuit comprises:
a forward push circuit: the system consists of two selectors and a bypass detection unit; the bypass detection unit judges the occurrence of data hazard according to related signals returned by the result write-back circuit and the memory access circuit and outputs control signals of the two selectors; the selector selects different data to output according to the control signal; the bypass detection unit detects data hazards, the data hazards generated with the memory access circuit are called MEM level hazards, and the data hazards generated with the result write-back circuit are called WB level hazards;
an ALU component: performing instruction operation, selecting different operations according to different instructions, and outputting operation results to the next stage;
a static prediction circuit: determining a jump address and jump execution in an instruction execution circuit, wherein a jump address generating module generates a jump address pc _ jump, a jump _ en generating module generates a jump execution signal jump _ en, and the two signals are delayed to the next stage; in the memory access circuit, a jump address signal and a jump execution signal are transmitted to an instruction taking-out circuit, so that the instruction taking-out circuit takes out an instruction according to the jump address; at this time, three instructions behind the jump instruction already enter the pipeline, and the three instructions need to be discarded; the abandonment of the instruction can prevent the instruction from rewriting the CPU state only by clearing the control signal of the instruction; the control signal zero clearing needs to be carried out by three steps of bit splicing, judgment and operation.
6. A RISC-V instruction set based six-stage pipelined CPU as claimed in claim 1 wherein said memory access circuit comprises:
a data memory: the data memory DTCM stores load and lw instruction usage data.
7. A RISC-V instruction set based six-stage pipelined CPU as claimed in claim 1, wherein said result write back circuit comprises:
a register file: 32 general integer registers;
interrupt register minterropt: at register address 0x000, minterropt outputs an interrupt signal intr _ done to the control terminal of the pc counter to keep the output of the pc counter unchanged, thereby halting the pipeline.
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