CN113986131A - MCU of double MRAM and method for caching data - Google Patents

MCU of double MRAM and method for caching data Download PDF

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CN113986131A
CN113986131A CN202111255005.5A CN202111255005A CN113986131A CN 113986131 A CN113986131 A CN 113986131A CN 202111255005 A CN202111255005 A CN 202111255005A CN 113986131 A CN113986131 A CN 113986131A
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memory
mcu
mram
information
data
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李月婷
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Qingdao Haicun Microelectronics Co ltd
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Zhizhen Storage Beijing Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/065—Replication mechanisms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices

Abstract

The application discloses an MCU of a double-MRAM type memory and a method for caching data, and relates to the field of the MCU of the double-MRAM type memory. The present application provides in a first aspect a dual MRAM-cache MCU, the MCU comprising: the processor is connected with the memory through the AHB, the AHB is connected with a peripheral bus through the AHB-to-APB bridge, the memory comprises 2 MRAM, and 1 MRAM is used as a backup. A second aspect of the present application provides a caching method, including: different storage rules are made according to different working modes of the MCU, and a priority decision rule is established in the environment of requiring partial data storage. By accessing double MRAM to a system bus as a memory MCU structure and combining the caching method, the effective management of the caching space is realized, and the stability of the MCU system is improved.

Description

MCU of double MRAM and method for caching data
Technical Field
The embodiment of the invention relates to the field of magnetic storage, in particular to an MCU (microprogrammed control unit) of double MRAM (magnetic random access memory) and a method for caching data.
Background
A Micro control Unit (MCU, Micro Controller Unit), also called a single-chip microcomputer, is a computer formed by appropriately reducing the frequency and specification of a Central Processing Unit (CPU), and integrating peripheral interfaces such as a Memory, a counter, a Universal Serial Bus (USB), an a/D converter, a UART (Universal Asynchronous Receiver Transmitter), a Programmable Logic Controller (PLC), a Direct Memory Access (DMA), and the like, and even devices and interfaces related to the operation of a Liquid Crystal Display (LCD) driving circuit computer, on a single chip. Because the MCU volume is relatively less, MCU is widely used in fields such as AI, cloud computing, 5G and intelligent automobile at present.
With the rapid development of the fields such as AI, cloud computing, 5G and intelligent automobiles, the types of data to be processed in each field are more and more, and based on the types of data, the problems of null pointer reading and writing, memory leakage, stack overflow, parameter errors and the like can occur in a storage of the MCU. Because the Memory used by the conventional MCU is an SRAM (Static Random-Access Memory), which is a volatile Memory, data in the SRAM is lost in a scenario where the MCU is halted due to these problems, which is not conducive to the related technicians to perform troubleshooting.
Disclosure of Invention
The embodiment of the invention provides an MCU of double MRAM (magnetic random Access memory) and a method for caching data, which aim to solve the problem that a conventional MCU memory is a volatile memory.
In order to solve the above problem, a first aspect of the present invention provides a method for caching data, which is applied to a dual MRAM MCU, and the MCU includes: the MCU comprises a first memory 3A and a second memory 3B, the method comprising:
storing information generated in the running process of the MCU in the first memory 3A;
detecting the operation mode of the MCU, wherein the operation mode of the MCU comprises a non-user mode and a user mode;
when the running mode of the MCU is the non-user mode, all information in the first memory 3A is stored in the second memory 3B;
and when the MCU is in a user mode, storing the information matched with the user mode in the first memory 3A to the second memory 3B.
In some embodiments, the information matched with the user matching pattern includes:
and the MCU runs an operation log corresponding to the fault.
In some embodiments, the method of caching data further comprises:
determining the priority of various types of information in the first memory, wherein each type of information corresponds to one type of service;
and determining the information matched with the user mode according to the priority of the various types of information.
In some embodiments, each of the types of information includes an operation event corresponding to a corresponding service, and the determining the priority of the types of information in the first memory includes:
the MCU acquires the access time and the access times of at least one storage area of the first memory, and establishes the corresponding relation between each storage area and the corresponding access times at each access time to obtain at least one operation event;
the MCU determines the operation time of each operation event in the at least one operation event;
determining the weight of each operation event at each moment, wherein the weight represents the demand degree of the corresponding operation event;
and determining the priority of each operation event according to the weight.
In some embodiments, the weights are derived from at least one of the following factors: the used storage capacity of the storage area, the preset system priority and the access times.
In some embodiments, the MCU periodically updates the access times and access time corresponding to the storage area in the first memory.
In some embodiments, the MCU non-user mode corresponding application scenario comprises: the product with the MCU is in the factory production process and the aging test scene, and the user mode corresponding scene comprises: and a scene used by a product user with the MCU.
In some embodiments, a decision matrix is constructed based on the operation event and the operation time, and a relation between the two is established, where the concrete representation includes:
Figure BDA0003323600970000031
wherein the content of the first and second substances,iindicating the read time for the MRAM to read the operating event, j indicating a different memory region in the MRAM, E ═ { E { (E) }1，E2…En}、D＝{D1，D2…DnAnd O ═ O1，O2…OnAnd represents the running time of each service event.
In some embodiments, the system kernel calculates the task priority Pi of each functional service by using a formula, where the formula includes:
Figure BDA0003323600970000032
in some embodiments, the processor performs storage allocation on each service module according to the calculation result, including:
Figure BDA0003323600970000033
Biindicates the bandwidth of the storage area, StotalRepresenting the total amount of MRAM storage, SallocIndicating the allocated storage capacity of the service function i,
the storage area bandwidth BiThe solving formula is as follows:
Figure BDA0003323600970000034
wherein, N is the number of bytes accessed by the service behavior, and T + (N-1) × val represents the time when each service behavior accesses the storage region.
In some embodiments, the method further comprises optimizing data of the MRAM internal storage space, wherein the optimization includes deletion of data and location of specific data.
In some embodiments, assume that the system kernel fetches the latest instruction data at time T1, fetches the latest system behavior log at time T2,
when the time T1 is earlier than the time T2, namely the current system is in normal operation, the current pointer data is read by the system, and the MRAM internal storage log executes deletion operation;
when the T1 is not earlier than the time T2, i.e., (T1 to T2) or at the time T1, there is a failure or other specific requirement of the system, the backup uses MRAM to internally store data as the data stored when the system fails.
In some embodiments, the MCU work preamble performs system initialization.
In some embodiments, the MCU is initialized, the 1# MRAM reads the internal configuration information and confirms whether it is the first boot through the system internal flag,
if the starting is started for the first time, the state is marked as 0;
if not, it is labeled as "1", and at this time, the 1# MRAM reads the system configuration information of "1".
In some embodiments, the MCU further comprises a data encryption process, the encrypting step comprising:
the MRAM receives and reads plaintext data;
the MRAM internal key converts plaintext data into ciphertext data through an encryption algorithm;
and the MRAM outputs the ciphertext data to a subsequent unit module or stores the ciphertext data by the MRAM.
In some embodiments, the MCU further comprises a data decryption process, the decrypting step comprising:
the MRAM receives and reads the ciphertext data;
the MRAM internal key converts the ciphertext data into plaintext data through a decryption algorithm;
the MRAM outputs plaintext data to a subsequent unit module or stores the data in the subsequent unit module.
In another aspect of the present application, an MCU of a dual MRAM includes:
the system comprises a processor 1, a system bus 2, a first memory 3A and a second memory 3B, wherein the processor 1 is connected with the first memory and the second memory through the system bus 2, and the first memory 3A and the second memory 3B are nonvolatile memories;
the first memory 3A is used for storing information related to the processor 1 and a system running log, and the second memory 3B is used for storing all or part of the information of the first memory 3A.
In some embodiments, the MCU further includes a peripheral bus 4 and a transfer bridge 5, where the transfer bridge 5 is used for the system bus 2 to transfer the peripheral bus 4, the processor 1 is connected to the first memory 3A and the second memory 3B through the system bus 2, and the system bus 2 is connected to the peripheral bus 4 through the transfer bridge 5.
In some embodiments, the MCU employs a queued serial peripheral interface QSPI, a QSPI controller driving the first memory 3A and the second memory 3B.
In some embodiments, the MCU enables the information transfer of the first memory 3A and the second memory 3B through QSPI communication protocol
In some embodiments, the modules used by the MCU further include I2C (synchronous serial bus), I2S (integrated circuit built-in audio bus), SPI (serial peripheral interface),
the module is mounted on the external bus 4.
In some embodiments, the system bus 2 comprises: a master module, a slave module, and an infrastructure.
In some embodiments, the MCU further comprises an arbiter configured to determine whether the system bus 2 and the connected modules complete data inter-working.
The embodiment of the invention provides a double-MRAM type cache MCU and a method for caching data. And the data storage scheme under three working modes is provided for the double MRAM type cache MCU, the problems of single block abrasion, storage overflow, thread interlocking and the like in the MRAM due to an unbalanced writing mode are avoided, the stability of the MCU system is improved, and the two MRAM can be mutually backed up, so that the accurate positioning of data when an abnormity occurs is ensured, and the efficiency of abnormity processing is improved.
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In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application.
FIG. 1 is a schematic diagram of an internal architecture scheme of a dual MRAM-based MCU according to the present invention;
FIG. 2 is a system bus architecture according to one embodiment of the present invention;
FIG. 3 is a schematic diagram of the operation mode of a dual MRAM-based MCU according to an embodiment of the present invention;
FIG. 4a is a diagram illustrating an MRAM encryption process of a system according to an embodiment of the invention;
FIG. 4b is a diagram illustrating an MRAM decryption process in the system according to an embodiment of the invention;
FIG. 5 is a diagram illustrating the row shifting of the encryption/decryption process of the MRAM in the system according to an embodiment of the present invention;
FIG. 6 is a diagram of column alias merge replacement in a system MRAM in accordance with an embodiment of the present invention;
fig. 7 is a flow chart of adding keys for encryption/decryption according to an embodiment of the present invention.
Detailed Description
In order to make the objects, features and advantages of the present invention more apparent and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It will be understood by those within the art that the terms "first", "second", etc. in this application are used only to distinguish one device, module, parameter, etc., from another, and do not denote any particular technical meaning or necessary order therebetween.
A Micro control Unit (MCU, Micro Controller Unit), also called a single-chip microcomputer, is to reduce the frequency and specification of a Central Processing Unit (CPU) appropriately, and integrate peripheral interfaces such as a Memory, a counter, a Universal Serial Bus (USB), an a/D converter, an Asynchronous Receiver Transmitter (UART), a Programmable Logic Controller (PLC), and a Direct Memory Access (DMA), and even a Liquid Crystal Display (LCD) driving circuit on a single chip to form a chip-level computer, which is used for different combined control in different application occasions, and has wide application in the fields of AI, cloud computing, 5G, smart vehicles, and the like.
At the present stage, with the rapid development of consumer electronics, industrial control, new energy and other fields, the demand for memory devices is increasing explosively. Along with the existence of various kinds of structured or unstructured data of system equipment in various fields, situations such as null pointer reading and writing, memory leakage, stack overflow, parameter errors and the like can occur in the system, the MCU can be caused to run down due to the problems, in order to quickly recover the system and locate the problem occurrence points, the system needs to restore the running state before the halt as soon as possible, related technicians can conveniently locate the product actual problem occurrence points, and the problem solving efficiency is improved.
In an embodiment of the present application, as shown in fig. 1, a first aspect of the present invention provides a dual MRAM MCU, comprising:
the system comprises a processor 1, a system bus 2, a first memory 3A and a second memory 3B, wherein the processor 1 is connected with the first memory and the second memory through the system bus 2, and the first memory 3A and the second memory 3B are nonvolatile memories;
the first memory 3A is used for storing information related to the processor 1 and a system running log, and the second memory 3B is used for storing all or part of the information of the first memory 3A.
Optionally, the MCU further includes a peripheral bus 4 and a transfer bridge 5, where the transfer bridge 5 is used to transfer the system bus 2 to the peripheral bus 4, the processor 1 is connected to the first memory 3A and the second memory 3B through the system bus 2, and the system bus 2 is connected to the peripheral bus 4 through the transfer bridge 5.
Generally, a cache memory inside an MCU mainly operates with an SRAM as a main component, i.e., a static random access memory, which is a kind of random access memory, and the term "static" refers to a defect that data stored in the SRAM is lost when power supply is stopped, i.e., the data stored in the SRAM is volatile as it is.
In general, an Advanced High Performance Bus (AHB), also called a High Performance Bus, is a Bus interface, like a USB. AHB is mainly used for the connection between high performance modules (such as CPU, DMA, and DPS).
The MRAM memory cell array realizes addressing through the gate grid and the bit line, realizes information reading and writing through the bit line current, has the characteristics of non-volatility, simple structure, low preparation process cost, low reading and writing times and high power consumption, and is widely applied to the field of storage.
Optionally, the MCU further includes an MRAM controller, and the MRAM controller connects the # 1 MRAM to the AHB system bus 2.
Optionally, the system bus 2 structure is shown in fig. 2, and includes: a Master module (AHB Master), a Slave module (AHB Slave), and an infrastructure.
Typically, the basic modules of the system bus 2 include an arbiter and a decoder, as shown in fig. 2.
Optionally, the MCU further includes an arbiter, and the arbiter is configured to determine whether the system bus 2 and the connected module complete data interworking.
Optionally, the modules used by the MCU further include I2C (synchronous serial bus), I2S (integrated circuit built-in audio bus), and SPI (serial peripheral interface), and the modules are mounted on the APB external bus 4.
In general, an Advanced Peripheral Bus (APB) is a standard on-chip Bus architecture. The APB is mainly used for connection between peripheral peripherals with low bandwidth, and unlike the AHB which supports multiple masters, the only master inside the APB is the APB bridge. The method is characterized by comprising the following steps: two clock cycles transmission; no waiting period and no response signal are needed; the control logic is simple and only has four control signals. The transmission on the APB can be illustrated with a state diagram as shown in the overview diagram.
Typically, data transfers on the system bus 2 are commanded by the master and responded to by the slave.
In another aspect of the present application, a method of caching data is presented,
applied to a dual MRAM-type MCU, the MCU comprising: the MCU comprises a first memory 3A and a second memory 3B, the method comprising:
storing information generated in the running process of the MCU in the first memory 3A;
detecting the operation mode of the MCU, wherein the operation mode of the MCU comprises a non-user mode and a user mode;
when the running mode of the MCU is the non-user mode, all information in the first memory 3A is stored in the second memory 3B;
and when the MCU is in a user mode, storing the information matched with the user mode in the first memory 3A to the second memory 3B.
Optionally, the information matched with the user matching pattern includes:
and the MCU runs an operation log corresponding to the fault.
Optionally, the information matched with the user matching pattern includes:
and the MCU runs an operation log corresponding to the fault.
Optionally, the method for caching data further includes:
determining the priority of various types of information in the first memory, wherein each type of information corresponds to one type of service;
and determining the information matched with the user mode according to the priority of the various types of information.
Optionally, each type of information in the various types of information includes an operation event corresponding to a corresponding service, and the determining the priority of the various types of information in the first memory includes:
the MCU acquires the access time and the access times of at least one storage area of the first memory, and establishes the corresponding relation between each storage area and the corresponding access times at each access time to obtain at least one operation event;
the MCU determines the operation time of each operation event in the at least one operation event;
determining the weight of each operation event at each moment, wherein the weight represents the demand degree of the corresponding operation event;
and determining the priority of each operation event according to the weight.
Optionally, the weight is obtained according to at least one of the following factors: the used storage capacity of the storage area, the preset system priority and the access times.
Optionally, the MCU periodically updates the access times and the access time corresponding to the storage area in the first memory.
Optionally, the MCU non-user mode corresponding application scenario includes: the product with the MCU is in the factory production process and the aging test scene, and the user mode corresponding scene comprises: the data storage state of the MCU in different working modes is shown in FIG. 3.
When the MCU is in a factory mode, the second memory 3B backs up all information of the first memory 3A;
when the MCU is in an aging test mode, the second memory 3B backs up all information of the first memory 3A;
when the MCU is in user mode, the second memory 3B is only used for storing the information of the user mode matching of the MCU system,
the information of the user pattern matching is provided by the first memory 3A.
Optionally, the MCU work preamble performs system initialization.
Optionally, after the MCU is initialized, the first memory 3A reads the internal configuration information, and determines whether the system is started up for the first time through the system internal label,
if the starting is started for the first time, the state is marked as 0;
if the computer is not started for the first time, the computer is marked as a state "1", and at this time, the first memory 3A reads the system configuration information in the state "1".
Optionally, when the MCU is in the user mode, since the second storage 3B only backs up the information matched with the user mode in the first storage 3A, the system needs to implement priority ranking on data by a data processing method to identify and preferentially record a specific behavior log of the system, where the data processing method includes:
the processor establishes a relation between the access times and the access time in the MRAM storage area;
the processor builds a decision matrix based on the access time and the specific behavior log, and builds a relation between the access time and the specific behavior log;
the MCU system periodically inquires the access times of each storage area, updates and records the access time of each service instruction accessing the storage area in real time, and records the task of each specific event to generate a specific behavior log;
the processor builds a decision matrix based on the access time and the specific behavior log, and builds a relation between the access time and the specific behavior log;
the processor calculates the priority of each functional service so as to determine the basis of memory area allocation;
and the processor allocates storage areas to the service modules according to the calculation result.
Optionally, the establishing of the relationship between the access times and the access time in the MRAM storage area is specifically represented as: nc (C, T), indicates that the number of times the specific storage area is accessed at the specific time T is C.
Optionally, the MCU system periodically queries the number of access times of each storage area, updates and records the access time of each service instruction accessing the storage area in real time,
the concrete expression is as follows: flow ═ (T, Event), indicates that a specific Event occurred at T time.
Optionally, a decision matrix is constructed based on the operation event and the operation time, and a relation between the operation event and the operation time is established, wherein the concrete representation includes
Figure BDA0003323600970000101
Wherein i represents a read time for the MRAM to read the operating event, j represents a different memory region in the MRAM, E ═ { E ═ E { (E) }1，E2…En}、D＝{D1，D2…DnAnd O ═ O1，O2…OnAnd represents the running time of each service event.
Optionally, the specific event includes: the MCU system fails and the MCU system performs special operations.
Optionally, the obtaining, by the MCU, a service decision matrix from the relevant factors includes: used memory capacity, system priority, and access times, the traffic decision matrix is used to prioritize different functional traffic within system processes and threads,
the construction weight coefficient vector W of the service data stream is specifically represented as: w ═ Wb，Wd，Wc]T，
Wherein, WbIndicating the used storage capacity of the corresponding storage area, WdIndicating the internal priority of the system, WcCorresponding to the number of memory region accesses.
Optionally, the MCU calculates the task priority Pi of each functional service through a formula, where the formula includes:
Figure BDA0003323600970000111
optionally, the MCU allocates storage areas to the service modules according to the calculation result, including:
Figure BDA0003323600970000112
Biindicates the bandwidth of the storage area, StotalRepresenting the total amount of MRAM storage, SallocIndicating the allocated storage capacity of the service function i,
the storage area bandwidth BiThe solving formula is as follows:
Figure BDA0003323600970000113
wherein, N is the byte number accessed by the service behavior, and T + (N-1) × val represents the time of accessing the storage region by each service behavior.
Optionally, the method further includes optimizing data in the MRAM internal storage space, where the optimization includes deletion of data and location of specific data.
Alternatively, assuming that the time when the system kernel acquires the latest instruction data is T1, the time when the latest system behavior log is acquired is T2,
when the time T1 is earlier than the time T2, namely the current system is in normal operation, the current pointer data is read by the system, and the MRAM internal storage log executes deletion operation;
when the T1 is not earlier than the time T2, i.e., (T1 to T2) or at the time T1, there is a failure or other specific requirement of the system, the backup uses MRAM to internally store data as the data stored when the system fails.
Generally, since MRAM is a non-volatile type memory, the non-data-loss nature of non-volatile storage also provides more access opportunities for system attackers and data thieves. When the MCU is in the factory mode and the aging test mode, the MCU testing system is mainly used for testing the stability of the MCU system and the period, and the requirement on data safety is low. However, when the MCU operates in the user mode, it needs to encrypt and protect the behavior events of the user and the data stored in the MRAM, so as to ensure the privacy security of the user during the use.
Optionally, the MCU further includes a data encryption process, the encryption process is shown in fig. 4a, and the encryption step includes:
the MRAM receives and reads plaintext data;
the MRAM internal key converts plaintext data into ciphertext data through an encryption algorithm;
and the MRAM outputs the ciphertext data to a subsequent unit module or stores the ciphertext data by the MRAM.
Optionally, the MCU further includes a data decryption process, the decryption process is as shown in fig. 4b, and the decryption step includes:
the MRAM receives and reads the ciphertext data;
the MRAM internal key converts the ciphertext data into plaintext data through a decryption algorithm;
the MRAM outputs plaintext data to a subsequent unit module or stores the data in the subsequent unit module.
Optionally, the MCU data encryption/decryption process includes:
the processor performs a shift process on the storage data of the storage area, the process is as shown in fig. 5,
specifically, the first row of data of the storage data in the storage area is kept unchanged, the second row is circularly shifted left by one byte, the third row is circularly shifted left by two bytes, the nth row is circularly shifted left by (N-1) bytes, and the storage data matrix is set to State and is expressed by the formula:
State[i][j]＝State[i][(j+i)％n]；i,j∈[0,n-1]；
the processor performs byte replacement and data column obfuscation merging on the stored data, as shown in figure 6,
in general, the S-box (Substition-Box) is the basic structure for a symmetric key algorithm to perform permutation computation, and its function is a simple "substitute" operation.
Specifically, the MCU system completes byte conversion of byte event mapping by means of the S-box, and at the same time, directly performs data processing to improve data time by a column conversion method, and the specific calculation is represented as:
text64[0]^＝keyExtended64[2*round]；
text64[1]^＝keyExtended64[2*round+1]；
……
text64[n-1]^＝keyExtended64[2*round+(n-1)]；
the processor adopts different keys for encrypting/decrypting the MRAM, the MCU system also comprises a six-axis sensor, the keys are derived from the six-axis sensor,
specifically, when the MCU system reads data of the data storage cartridge, a key is formed according to the six-side numerical values of the six-axis sensor in the current state,
if the data acquisition key B is stored, the data acquisition key a is read, and after the data acquisition key is obtained, both the storage and reading processes exchange keys, that is, the key a is used for encryption when data storage is performed, and the key B is used for decryption when data reading is performed, as shown in fig. 7.
The embodiment of the invention provides a double-MRAM type cache MCU and a method for caching data. And the data storage scheme under three working modes is provided for the double MRAM type cache MCU, the problems of single block abrasion, storage overflow, thread interlocking and the like in the MRAM due to an unbalanced writing mode are avoided, the stability of the MCU system is improved, and the two MRAM can be mutually backed up, so that the accurate positioning of data when an abnormity occurs is ensured, and the efficiency of abnormity processing is improved.

Claims (10)

1. A method of buffering data, applied to an MCU of a dual magnetic random access memory MRAM, the MCU comprising a first memory (3A) and a second memory (3B), the method comprising:
storing information generated in the running process of the MCU in the first memory (3A);
detecting the operation mode of the MCU, wherein the operation mode of the MCU comprises a non-user mode and a user mode;
when the operation mode of the MCU is the non-user mode, storing all information in the first memory (3A) to the second memory (3B);
when the MCU is in a user mode, storing information in the first memory (3A) matching the user mode to the second memory (3B).
2. The method of claim 1, wherein the information matching the user pattern comprises:
and the MCU runs an operation log corresponding to the fault.
3. The method of claim 2, further comprising:
determining the priority of various types of information in the first memory, wherein each type of information corresponds to one type of service;
and determining the information matched with the user mode according to the priority of the various types of information.
4. The method of claim 3, wherein each of the types of information includes an operational event corresponding to the corresponding service, and wherein the determining the priority of the types of information in the first memory includes:
the MCU acquires the access time and the access times of at least one storage area of the first memory, and establishes the corresponding relation between each storage area and the corresponding access times at each access time to obtain at least one operation event;
the MCU determines the operation time of each operation event in the at least one operation event;
determining the weight of each operation event at each moment, wherein the weight represents the demand degree of the corresponding operation event;
and determining the priority of each operation event according to the weight.
5. The method of claim 4, wherein the weight is derived from at least one of: the used storage capacity of the storage area, the preset system priority and the access times.
6. The method of claim 4, further comprising:
and the MCU periodically updates the access times and the access time corresponding to the storage area in the first memory.
7. An MCU of a dual MRAM, the MCU comprising:
a processor (1), a system bus (2), a first memory (3A) and a second memory (3B), the processor (1) being connected to the first and second memories by the system bus (2), the first and second memories (3A, 3B) being non-volatile memories;
wherein the first memory (3A) is used for storing information related to the processor (1) and a system running log, and the second memory (3B) is used for storing all or part of the information of the first memory (3A).
8. MCU according to claim 7, characterized in that it further comprises a peripheral bus (4) and a transfer bridge (5), said transfer bridge (5) being used for said system bus (2) to transfer said peripheral bus (4), said processor (1) being connected with said first memory (3A) and second memory (3B) through said system bus (2), said system bus 2 being connected with peripheral bus (4) through transfer bridge (5).
9. MCU according to claim 7, characterized in that it employs a queued serial peripheral interface QSPI, a QSPI controller driving the first memory (3A) and the second memory (3B).
10. MCU according to claim 7, characterized in that it implements the information transfer of the first memory (3A) and the second memory (3B) by QSPI communication protocol.
CN202111255005.5A 2021-10-27 2021-10-27 MCU of double MRAM and method for caching data Pending CN113986131A (en)

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