CN113986001A - Chip and control method - Google Patents
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- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3243—Power saving in microcontroller unit
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- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/781—On-chip cache; Off-chip memory
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The application discloses a chip and a control method, wherein the chip comprises a cache, a flash memory and a processor, wherein the cache or the flash memory is used for storing target data, and when the chip is in a preset clock mode, the processor is used for preferentially acquiring the target data from the cache; and controlling the flash memory to enter a working mode after the target data is failed to be acquired from the cache, and controlling the flash memory to enter a low power consumption mode after the target data is acquired from the flash memory. The method and the device can reduce the overall power consumption of the chip reading operation.
Description
Technical Field
The application relates to the technical field of microcontrollers, in particular to a chip and a control method.
Background
SoC (System on Chip ) is also called System on Chip, which is a micro System. In low power applications, such as low power read operations, a low speed clock is often used as the SoC operating frequency to reduce power consumption. Under the working frequency of the SoC, the dynamic power consumption and the static power consumption of the logic circuit are very low, but the overall power consumption of the SoC is usually at a higher level, so that the overall power consumption of the SoC is not low in a low-speed working mode.
Disclosure of Invention
The embodiment of the application provides a chip and a control method, which can reduce the overall power consumption of the chip reading operation.
In a first aspect, an embodiment of the present application provides a chip, including: the system comprises a cache, a flash memory and a processor, wherein the cache or the flash memory is used for storing target data;
when the chip is in a preset clock mode,
the processor is used for preferentially acquiring the target data from the cache; and controlling the flash memory to enter a working mode after the target data is failed to be acquired from the cache, and controlling the flash memory to enter a low power consumption mode after the target data is acquired from the flash memory.
Optionally, the chip further includes a control module;
the processor is used for sending a first read request to the target data;
the cache is used for sending a second read request for the target data to the control module after the processor fails to acquire the target data from the cache according to the first read request;
and the control module is used for controlling the flash memory to enter a working mode according to the second read request, controlling the flash memory to enter a low power consumption mode after the target data is read from the flash memory, and sending the target data to the cache.
Optionally, the control module includes:
the controller is used for sending a first power supply control instruction according to the second reading request;
the power supply management unit is used for controlling the flash memory to enter a working mode according to the first power supply control instruction and sending a reading permission instruction to the controller;
the controller is further configured to read the target data from the flash memory according to the read permission instruction, send the target data to the cache, and send a second power supply control instruction to the power management unit;
and the power supply management unit is further used for adjusting the power supply voltage of the flash memory according to the second power supply control instruction so that the flash memory enters the low power consumption mode.
Optionally, the power management unit is further configured to adjust a power supply voltage to the flash memory according to the second power supply control instruction, so that the flash memory enters the low power consumption mode, where the power management unit includes:
and the power supply management unit is also used for powering off the flash memory according to the second power supply control instruction, or regulating the voltage of the flash memory to a preset voltage, wherein the preset voltage is lower than the normal working voltage of the flash memory.
Optionally, the cache, the flash memory and the processor are integrated in one module.
Optionally, the cache and the processor are integrated in one module, and the flash memory is disposed outside the module.
Optionally, the Cache is a Cache memory or a buffer register.
In a second aspect, an embodiment of the present application provides a chip control method, which is applied to the chip described above, and the method includes:
when the chip is in a preset clock mode, the processor preferentially acquires the target data from the cache, and when the processor fails to acquire the target data from the cache, the flash memory is controlled to enter a working mode, and after the target data is acquired from the flash memory, the flash memory is controlled to enter a low power consumption mode.
Optionally, the method further includes:
the processor sending a first read request for the target data to the cache;
if the processor fails to acquire the target data from the cache, the cache sends a second read request for the target data to the control module;
the control module controls the flash memory to enter a working mode according to the second read request;
and the control module reads the target data from the flash memory, sends the target data to the cache, and controls the flash memory to enter the low power consumption mode.
Optionally, the method further includes:
the controller sends a first power supply control instruction to the power supply management unit according to the second reading request;
the power supply management unit controls the flash memory to enter a working mode according to the first power supply control instruction and sends a reading permission instruction to the controller;
the controller reads the target data from the flash memory according to the read permission instruction, sends the target data to the cache, and sends a second power supply control instruction to the power management unit;
and the power supply management unit adjusts the power supply voltage for the flash memory according to the second power supply control instruction so that the flash memory enters the low power consumption mode.
Optionally, the adjusting, by the power management module, the power supply voltage to the flash memory according to the second power supply control instruction so that the flash memory enters the low power consumption mode includes:
and the power supply management module cuts off the power of the flash memory according to the second power supply control instruction, or adjusts the voltage of the flash memory to a preset voltage, wherein the preset voltage is lower than the normal working voltage of the flash memory.
In an embodiment of the present application, a chip may include a cache, a flash memory, and a processor. The cache and the flash memory can store target data, when the chip is in a preset clock mode, the processor preferentially obtains the target data from the cache, when the target data obtained from the cache fails, the processor controls the flash memory to enter a working mode, then obtains the target data from the flash memory, and controls the flash memory to enter a low power consumption mode after obtaining the target data. That is, in the embodiment of the present application, the target data is preferentially obtained from the high-speed and low-power cache, when the target data is stored in the high-speed cache, the target data does not need to be read from the low-speed and high-power flash memory, at this time, the flash memory is in the low-power mode, only when the target data is not stored in the high-speed cache, the processor obtains the target data from the flash memory, at this time, the flash memory is controlled to enter the operating mode from the low-power mode, and after the target data is obtained from the flash memory, the flash memory is controlled to enter the low-power mode, and the flash memory can be kept in the low-power mode most of the time. Therefore, the embodiment of the application can reduce the overall power consumption of the chip reading operation.
Drawings
The technical solutions and advantages of the present application will become apparent from the following detailed description of specific embodiments of the present application when taken in conjunction with the accompanying drawings.
Fig. 1 is a schematic structural diagram of a chip according to an embodiment of the present application.
Fig. 2 is another schematic structural diagram of a chip provided in the second embodiment of the present application.
Fig. 3 is a logic control diagram of a chip provided in an embodiment of the present application.
Fig. 4 is another logic control diagram of the chip provided in the embodiment of the present application.
FIG. 5 is a schematic diagram of another structure of a chip according to the second embodiment of the present application
Fig. 6 is a schematic flowchart of a chip control method provided in the third embodiment of the present application.
Fig. 7 is a schematic flowchart of another chip control method according to the fourth embodiment of the present application.
Detailed Description
Referring to the drawings, wherein like reference numbers refer to like elements, the principles of the present application are illustrated as being implemented in a suitable computing environment. The following description is based on illustrated embodiments of the application and should not be taken as limiting the application with respect to other embodiments that are not detailed herein.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a chip according to a first embodiment of the present application, where the chip 100 may include: cache 101, flash memory 102, and processor 103. Cache 101 and flash memory 102 may store target data, and processor 103 may retrieve the target data from cache 101 or flash memory 102.
Due to the development of various integrated circuit technology and application-oriented system-on-chip (SoC), a complex electronic system, such as a mobile phone chip, a digital television chip, a DVD chip, etc., can be implemented on a single integrated circuit chip. In low power applications, such as low power read operations, a low speed clock is often used as the SoC operating frequency to reduce power consumption. At this operating frequency, both the dynamic power consumption and the static power consumption of the logic circuit are very low, but in order to maintain the operation of the SoC, a part of the memory (e.g., a nonvolatile memory) of the SoC must be in an operating state to ensure that the CPU can smoothly execute the program. In the working state of such a memory, even if there is no read/write operation, a certain working current is still required to maintain the working state, so that the overall power consumption of the SoC is still relatively high in the low-speed clock working mode.
In this embodiment, the Cache 101 may be a Cache memory or a buffer register (buffer). The capacity of the Cache memory and the buffer register is smaller, but the speed is much higher than that of the main memory and is close to the speed of the CPU, so the power consumption is lower. The flash memory 102 is a non-volatile memory (NVM), and when the current is turned off, the data stored in the NVM does not disappear. Flash memory 102 has a lower read and write speed and a much higher power consumption than cache memory 101, and it is understood that cache memory 101 has a higher priority than flash memory 102. When the processor 103 reads data, it preferentially reads data from the cache memory 101, and power consumption can be reduced.
It should be noted that the target data may be preferentially stored in the cache memory 101 to increase the reading speed of the chip. When the cache memory 101 is full of other data or a preset data format stored in the cache memory 101 is set in advance, if the data format of the target data is different from the preset data format, the target data is stored in the flash memory 102. When the storage space of the cache memory 101 is insufficient, a part of the target data (data a) may be stored in the cache memory 101 and another part of the target data (data B) may be stored in the flash memory 102.
When the processor 103 reads the target data, it first reads from the cache memory 101 having a higher priority, and power consumption can be reduced. When the target data is not stored in the cache memory 101, the target data is read from the flash memory 102. For example, when the chip 100 is in the preset clock mode and the target data is stored in the cache memory 101, the processor 103 may directly read the target data from the cache memory 101, which not only has a fast data reading speed, but also reduces the power consumption of data reading, and at the same time, since the target data does not need to be read from the flash memory 102, the flash memory 102 may be in the low power consumption mode at this time, so as to reduce the overall power consumption of the chip.
For another example, when the target data is stored in the flash memory 102, the processor 103 may control the flash memory 102 to enter the operating mode from the low power consumption mode after failing to obtain the target data from the cache memory 101, may then read the target data from the flash memory 102, and controls the flash memory 102 to enter the low power consumption mode after reading the target data from the flash memory 102, so as to reduce the overall power consumption of the chip.
For another example, when the storage space of the cache memory 101 is insufficient, a part of the target data (assumed to be data a) is stored in the cache memory 101, and another part of the target data (assumed to be data B) is stored in the flash memory 102, after confirming that the cache memory 101 stores only the data a, the processor 103 may read the data a from the cache memory 101, control the flash memory 102 to enter the operating mode from the low power consumption mode, then read the data B from the flash memory 102, and after acquiring the data B from the flash memory 102, control the flash memory 102 to enter the low power consumption mode, and combine the data a and the data B into the target data. The flash memory 102 is in the working mode only during reading and writing, and is in the low power consumption mode most of the time, so that the overall power consumption of the chip reading and writing operation can be reduced.
It should be noted that the clock mode may be divided by using clock frequencies, and the operating states of the chip 100 are different according to different clock frequencies, for example, at a high-speed clock frequency, the chip is in a normal operating state, and at a low-speed clock frequency, the chip may be in a low-power consumption state such as a sleep state. In this embodiment, the preset clock mode is a low-speed clock mode, for example, the clock frequency of the preset clock mode may be 32KHz, and the chip 100 is in a low-power application state in the preset clock mode.
It is understood that in the embodiment of the present application, the chip 100 may include a cache 101, a flash memory 102, and a processor 103. The cache memory 101 and the flash memory 102 may store target data, when the chip 100 is in a preset clock mode, the processor 103 preferentially obtains the target data from the cache memory 101, and when the processor 103 fails to obtain the target data from the cache memory 101, the processor 103 controls the flash memory 102 to enter an operating mode, then obtains the target data from the flash memory 102, and controls the flash memory 102 to enter a low power consumption mode after obtaining the target data. That is, in the embodiment of the present application, the target data is preferentially obtained from the high-speed and low-power-consumption cache, when the target data is stored in the cache 101, the target data does not need to be read from the low-speed and high-power-consumption flash memory 102, at this time, the flash memory 102 is in the low-power-consumption mode, only when the target data is not stored in the cache 101, the processor 103 obtains the target data from the flash memory 102, at this time, the flash memory 102 is controlled to be switched from the low-power-consumption mode to the operating mode, and after the target data is obtained from the flash memory 102, the flash memory 102 is controlled to enter the low-power-consumption mode, and the flash memory 102 can be kept in the low-power-consumption mode most of the time. Therefore, the embodiment of the application can reduce the overall power consumption of the chip 100 in the reading operation.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a chip according to a second embodiment of the present application, where the chip 100 may include: cache 101, flash memory 102, processor 103, and control module 104. Cache 101 and flash memory 102 may store target data. In one connection, the processor 103 may be connected to the cache memory 101, the cache memory 101 may be connected to the control module 104, and the control module 104 may be connected to the flash memory 102.
In this embodiment, the processor 103 sends a first read request for target data to the cache memory 101, after receiving the first read request, if the cache memory 101 does not store the target data, the cache memory 101 may send a second read request for the target data to the control module 104, and the control module 104 controls the flash memory 102 to enter a working mode according to the second read request, and after reading the target data from the flash memory 102, controls the flash memory 102 to enter a low power consumption mode, and sends the target data to the cache memory 101; of course, after receiving the first read request, if the cache 101 stores the target data, the processor 103 may directly read the target data from the cache 101.
In this embodiment, the control module 104 may control the flash memory 102 to enter the operating mode after receiving the second read request sent by the cache memory 101, and control the flash memory 102 to enter the low power consumption mode after reading the target data from the flash memory 102, where the low power consumption mode may be a low voltage holding state or a power-off state, as some examples. For example, after the control module 104 receives the second read request sent by the cache 101, if the flash memory 102 is in the low voltage retention state, the control module 104 may control the flash memory 102 to recover to the normal operating voltage; for another example, after the control module 104 receives the second read request sent by the cache 101, if the flash memory 102 is in a power-down state, the control module 104 may control to power up the flash memory 102, so that the flash memory 102 enters the operating mode.
For example, referring to fig. 3, fig. 3 is a logic control diagram of the chip 100 in the low speed clock mode according to the embodiment of the present application. The processor 103 sends a first read request for the target data to the cache memory 101, and when the target data is not stored in the cache memory 101, which indicates "miss", the control module 104 sends a second read request to the flash memory 102, so that the flash memory 102 recovers to a normal operating voltage and enters an operating mode. After the flash memory 102 enters the operating mode, the control module 104 may read the target data from the flash memory 102, and then control the flash memory 102 to enter a low voltage holding state, for example, control the power supply voltage of the flash memory 102 to be a preset voltage threshold, where the preset voltage threshold is lower than the normal operating voltage of the flash memory 102. After retrieving the target data, control module 104 may send the target data to cache 101 so that processor 103 may retrieve the target data from cache 101. When the target data is stored in the cache memory 101, which indicates "hit", the processor 103 directly obtains the target data from the cache memory 101, and the flash memory 102 is still in the low power consumption mode of the low voltage retention state. In this embodiment, the flash memory 102 is in a low voltage holding state during the period of non-access, and the power consumption is lower than that during normal operation, so that the overall power consumption of the chip 100 in the low speed clock mode for the read operation can be reduced. Meanwhile, the low-voltage state is recovered to the normal working voltage, the recovery time is short, and therefore the working efficiency of the chip can be improved.
For another example, please refer to fig. 4, in which fig. 4 is another logic control diagram of the chip 100 in the low speed clock mode according to the embodiment of the present application. The difference from fig. 3 is that in the present embodiment, the flash memory 102 is in the power-off state during the period of non-access, and the power consumption during the period of non-access can be greatly reduced by completely powering off compared with the low-voltage retention state. The overall power consumption of the chip 100 in the low speed clock mode for read operations may thereby be significantly reduced.
As an example, continuing to refer to fig. 2, in this embodiment, the control module 104 may further include a controller 1041 and a power management unit 1042. In one connection, the controller 1041 is connected to the cache memory 101 and the flash memory 102, respectively, and the power management unit 1042 is connected to the flash memory 102 and the controller 1041. The controller 1041 may send a first power supply control instruction to the power management unit 1042 according to the second read request, for example, the first power supply control instruction may be a power supply request instruction, so that the flash memory 102 enters the operating mode from the low power consumption mode; the power management unit 1042 may control the flash memory 102 to enter the operating mode according to the first power control instruction, and send a read permission instruction to the controller 1041, for example, the read permission instruction may be a signal indicating that the flash memory 102 has been powered on to cause the flash memory 102 to enter the operating mode; the controller 1041 may access the flash memory 102 according to the read permission instruction, read the target data from the flash memory 102, send the target data to the cache memory 101, and send a second power supply control instruction to the power management unit 1042, for example, the second power supply control instruction may be a request power-off instruction or a hold low voltage instruction, so as to cause the flash memory 102 to enter a low power consumption mode. The power management unit 1042 may adjust a power supply voltage to the flash memory 102 according to the second power supply control command, so that the flash memory 102 enters the low power consumption mode.
In order to further reduce the overall power consumption of the chip 100 in the preset clock mode, a large-capacity cache memory may be used as the cache memory 101, for example, the capacity of the cache memory 101 may be 8M, 16M, or 32M, and the like, and the use of the large-capacity cache memory 101 may reduce the access frequency of the processor 103 to the flash memory 102, thereby reducing the power-on frequency of the flash memory 102, and directly reading the target data from the cache memory 101, which not only achieves the purpose of reducing the overall power consumption of the chip 100 during the reading operation, but also improves the efficiency of program execution.
It should be noted that, as an example, the cache memory 101, the flash memory 102 and the processor 103 are integrated into a module, and the structure diagram is shown in fig. 2, that is, the SoC may have the flash memory 102 built therein, and the chip reading speed of the structure is faster. As another example, the cache memory 101 and the processor 103 may be integrated into a SoC module, and the flash memory 102 is disposed outside the SoC module, and the structure of the structure is shown in fig. 5, i.e. the flash memory 102 may be disposed outside the SoC module, but still may be controlled by the power management unit 1042. The flash memory 102 is disposed outside the SoC, and although the chip processing speed is reduced, the flash memory can adapt to different application scenarios. Therefore, different chip structures of the embodiment can meet different application scenarios, and different requirements for power consumption and speed are balanced.
It is understood that in the embodiment of the present application, the chip 100 may include a cache 101, a flash memory 102, a processor 103, and a control module 104, and the control module 104 may further include a controller 1041 and a power management unit 1042. Processor 103 may send a first read request for the target data to cache 101, and when the target data is not stored, cache 101 may send a second read request for the target data to controller 1041; the controller 1041 may send a first power supply control instruction to the power management unit 1042 according to the second read request; the power management unit 1042 may control the flash memory 102 to enter the operating mode according to the first power supply control instruction, and send a read permission instruction to the controller 1041; the controller 1041 may read target data from the flash memory 102 according to the read permission instruction, send the target data to the cache memory 101, and send a second power supply control instruction to the power management unit 1042. The power management unit 1042 may adjust a power supply voltage to the flash memory 102 according to the second power control instruction to enable the flash memory 102 to enter a power-off state or a low-voltage retention state, and the cache 101 sends the target data to the processor 103.
In the embodiment of the present application, when the target data is stored in the cache memory 101, the target data does not need to be read from the flash memory 102, and the flash memory 102 is in the low-voltage holding state or the power-off state, only when the target data is not stored in the cache memory 101, the processor 103 obtains the target data from the flash memory 102, and at this time, the control module 104 controls the flash memory 102 to enter the operating mode from the low-voltage holding state or the power-off state, and after obtaining the target data from the flash memory 102, the control module 104 controls the flash memory 102 to enter the low-voltage holding state or the power-off state, and the flash memory 102 can be kept in the low-power consumption mode of the low-voltage state or the power-off state most of the time. Therefore, the embodiment of the present application can reduce the overall power consumption of the read/write operation of the chip 100.
An embodiment of the present application further provides a chip control method, which can be applied to the chips in the foregoing embodiments, and the method includes: when the chip is in a preset clock mode, the processor preferentially acquires target data from the cache, and when the processor fails to acquire the target data from the cache, the processor controls the flash memory to enter a working mode, and controls the flash memory to enter a low power consumption mode after acquiring the target data from the flash memory.
In an implementation manner, please refer to fig. 6, where fig. 6 is a schematic flowchart of a chip control method according to a third embodiment of the present application, and the method may include:
601. the processor sends a first read request for target data to the cache.
In this embodiment, the priority of the cache is higher than that of the flash memory, and when the processor needs to acquire the target data, the processor preferentially sends a first read request for the target data to the cache. For example, the Cache may be a Cache memory or a buffer register, and the Flash memory may be a non-volatile memory (e.g., Flash). When the processor reads the data, the processor preferentially sends a first read request for the target data to the cache so as to read the target data from the cache.
602. If the processor fails to obtain the target data from the cache, the cache sends a second read request for the target data to the control module.
It should be noted that, the target data is preferentially stored in the cache to accelerate the data reading speed; when the cache is full of other data or a preset data format stored in the cache is set in advance, if the data format of the target data is different from the preset data format, the target data is stored in the flash memory. When the storage space of the cache is insufficient, a part of the target data (data a) may be stored in the cache and another part of the target data (data B) may be stored in the flash memory.
When the processor reads the target data, the processor firstly reads the target data from the high-priority cache, and when the target data is not stored in the cache, the processor reads the target data from the flash memory. For example, when the chip is in the preset clock mode, when the target data is stored in the cache, the processor may directly read the target data from the cache to increase the data reading speed, and the power consumption for reading the target data from the cache is lower than that for reading the target data from the flash memory.
For another example, when the target data is stored in the flash memory, the processor may control the flash memory to enter the operating mode from the low power consumption mode after confirming that the cache does not store the target data, that is, after failing to acquire the target data from the cache, and then may read the target data from the flash memory, and control the flash memory to enter the low power consumption mode after reading the target data from the flash memory, so as to reduce the overall power consumption of the chip.
For another example, when the storage space of the cache is insufficient, a part of the target data (assumed to be data a) is stored in the cache, and another part of the target data (assumed to be data B) is stored in the flash memory, after confirming that the cache only stores the data a, the processor may read the data a from the cache, control the flash memory to enter the operating mode from the low power consumption mode, then may read the data B from the flash memory, and control the flash memory to enter the low power consumption mode after acquiring the data B from the flash memory, and combine the data a and the data B into the target data.
In this embodiment, when the processor needs to obtain the target data, the first read request for the target data may be preferentially sent to the cache, and if the cache does not store the target data, the cache sends a second read request for the target data to the control module.
603. And the control module controls the flash memory to enter a working mode according to the second read request.
For example, the control module may control the flash memory to enter the operating mode from the low power consumption mode after receiving the second read request sent by the cache. For example, after receiving the second read request sent by the cache, the control module may control the flash memory to recover to the operating voltage if the flash memory is in the low-voltage retention state. For another example, after receiving the second read request sent by the cache, if the flash memory is in a power-down state, the control module may control the flash memory to be powered on, so that the flash memory enters the operating mode.
604. The control module reads the target data from the flash memory, sends the target data to the cache, and controls the flash memory to enter a low power consumption mode.
For example, after the flash memory is switched from the low power consumption mode to the operating mode, the control module may read the target data from the flash memory and send the target data to the cache memory, so that the processor may obtain the target data from the cache memory. And then the control module controls the flash memory to enter a low power consumption mode. For example, the control module may control the power supply voltage of the flash memory to be a preset voltage threshold, and the preset voltage threshold is lower than the working voltage of the flash memory, so that the flash memory is in a low-voltage holding state, thereby reducing the overall power consumption of the chip reading operation, and meanwhile, the low-voltage state is recovered to the working voltage, so that the recovery time is short, thereby improving the working efficiency of the chip. For another example, the control module may control the flash memory to be in a power-off state, and completely powering off may greatly reduce power consumption during a period when the flash memory is not accessed, so that overall power consumption of a chip read operation may be reduced.
In the embodiment of the application, when the target data is stored in the cache, the target data is directly read from the cache, the flash memory is in the low power consumption mode at the moment, only when the target data is not stored in the cache, the processor can acquire the target data from the flash memory, the flash memory can be controlled to enter the working mode from the low power consumption mode through the control module at the moment, and after the target data is acquired from the flash memory, the flash memory is controlled to enter the low power consumption mode through the control module, and the flash memory can be kept in the low power consumption mode in most of time. Therefore, the embodiment of the application can reduce the overall power consumption of the read-write operation of the chip.
In an implementation manner, please refer to fig. 7, where fig. 7 is a schematic flowchart of a chip control method according to a fourth embodiment of the present application, where the method may include:
701. the processor sends a first read request for target data to the cache.
For a specific implementation of 701, please refer to the embodiment 601, which is not described herein.
702. If the processor fails to obtain the target data from the cache, the cache sends a second read request for the target data to the controller.
It should be noted that, the target data is preferentially stored in the cache to accelerate the data reading speed; when the cache is full of other data or a preset data format stored in the cache is set in advance, if the data format of the target data is different from the preset data format, the target data is stored in the flash memory. When the cache receives a first read request for target data sent by the processor, if the cache does not store the target data, the cache sends a second read request for the target data to the controller.
703. The controller sends a first power supply control instruction to the power management unit according to the second read request.
For example, the controller may send a first power control command to the power management unit after receiving a second read request sent by the cache. For example, the first power supply control command may be a request power supply command to cause the flash memory to enter the operating mode from the low power consumption mode.
704. And the power supply management unit controls the flash memory to enter a working mode according to the first power supply control instruction and sends a reading permission instruction to the controller.
For example, after receiving the first power control command, the power management unit may provide an operating voltage to the flash memory to enable the flash memory to enter an operating mode from a low power consumption mode, and meanwhile, the power management unit may further send a read permission command to the controller to allow the controller to read the target data from the flash memory. The read permission command may be a signal indicating that the flash memory has been powered up and put into an operating mode.
705. The controller reads the target data from the flash memory according to the read permission instruction, sends the target data to the cache, and sends a second power supply control instruction to the power management unit.
For example, after receiving the read permission command sent by the power management unit, the controller may read the target data from the flash memory and send the target data to the cache memory, so that the processor may read the target data from the cache memory. Meanwhile, the controller can also send a second power supply control instruction to the power management unit. For example, the second power control command may be a request power-off command or a hold low voltage command to cause the flash memory to enter a low power consumption mode.
706. And the power supply management unit adjusts the power supply voltage for the flash memory according to the second power supply control instruction so that the flash memory enters a low power consumption mode.
For example, after receiving the second power supply control command sent by the controller, the power management unit adjusts the power supply voltage to the flash memory to enable the flash memory to enter the low power consumption mode. For example, the power management unit can control power supply to the flash memory, the power supply voltage is a preset voltage threshold value, and the preset voltage threshold value is lower than the working voltage of the flash memory, so that the flash memory is in a low-voltage holding state, the whole power consumption of the chip reading operation can be reduced, meanwhile, the low-voltage state is recovered to the working voltage, the recovery time is short, and the working efficiency of the chip can be improved. For another example, the power management unit may control not to supply power to the flash memory, so that the flash memory is in a power-off state, and completely powering off may greatly reduce power consumption of the flash memory during a period when the flash memory is not accessed, so that overall power consumption of a chip reading operation may be reduced.
In the embodiment of the application, when the target data is stored in the cache, the target data is directly read from the cache, the flash memory is in the low power consumption mode, only when the target data is not stored in the cache, the processor can acquire the target data from the flash memory through the controller, the flash memory is controlled to enter the working mode from the low power consumption mode through the power management unit, the flash memory is controlled to enter the low power consumption mode through the power management unit after the target data is acquired from the flash memory, and the flash memory can be kept in the low power consumption mode most of the time. Therefore, the embodiment of the application can reduce the overall power consumption of the read-write operation of the chip.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and parts that are not described in detail in a certain embodiment may refer to the above detailed description of the chip, which is not described herein again.
The chip control method provided by the embodiment of the present application and the chip in the above embodiment belong to the same concept, any method provided in the chip control method embodiment may be operated on the chip, and the specific implementation process of the chip control method is described in the chip embodiment in detail, and is not described herein again.
The chip and the control method provided by the embodiment of the present application are described in detail above, and a specific example is applied in the description to explain the principle and the implementation of the present application, and the description of the embodiment is only used to help understanding the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (11)
1. A chip comprising a cache, a flash memory and a processor, the cache or the flash memory for storing target data,
when the chip is in a preset clock mode,
the processor is used for preferentially acquiring the target data from the cache; and controlling the flash memory to enter a working mode after the target data is failed to be acquired from the cache, and controlling the flash memory to enter a low power consumption mode after the target data is acquired from the flash memory.
2. The chip of claim 1, wherein the chip further comprises a control module;
the processor is used for sending a first read request to the target data;
the cache is used for sending a second read request for the target data to the control module after the processor fails to acquire the target data from the cache according to the first read request;
and the control module is used for controlling the flash memory to enter a working mode according to the second read request, controlling the flash memory to enter a low power consumption mode after the target data is read from the flash memory, and sending the target data to the cache.
3. The chip of claim 2, wherein the control module comprises:
the controller is used for sending a first power supply control instruction according to the second reading request;
the power supply management unit is used for controlling the flash memory to enter a working mode according to the first power supply control instruction and sending a reading permission instruction to the controller;
the controller is further configured to read the target data from the flash memory according to the read permission instruction, send the target data to the cache, and send a second power supply control instruction to the power management unit;
and the power supply management unit is further used for adjusting the power supply voltage of the flash memory according to the second power supply control instruction so that the flash memory enters the low power consumption mode.
4. The chip of claim 3, wherein the power management unit is further configured to adjust a power supply voltage to the flash memory according to the second power control command, so that the flash memory enters the low power consumption mode, and the power management unit includes:
and the power supply management unit is also used for powering off the flash memory according to the second power supply control instruction, or regulating the voltage of the flash memory to a preset voltage, wherein the preset voltage is lower than the normal working voltage of the flash memory.
5. The chip of claim 1, wherein the cache, the flash memory, and the processor are integrated in one module.
6. The chip of claim 1, wherein the cache and the processor are integrated in a module, and wherein the flash memory is disposed outside the module.
7. The chip of any one of claims 1 to 6, wherein the Cache is a Cache memory or a buffer register.
8. A chip control method applied to the chip according to any one of claims 1 to 7, wherein the method comprises:
when the chip is in a preset clock mode, the processor preferentially acquires the target data from the cache, and when the processor fails to acquire the target data from the cache, the flash memory is controlled to enter a working mode, and after the target data is acquired from the flash memory, the flash memory is controlled to enter a low power consumption mode.
9. The chip control method according to claim 8, further comprising:
the processor sending a first read request for the target data to the cache;
if the processor fails to acquire the target data from the cache, the cache sends a second read request for the target data to a control module;
the control module controls the flash memory to enter a working mode according to the second read request;
and the control module reads the target data from the flash memory, sends the target data to the cache, and controls the flash memory to enter the low power consumption mode.
10. The chip control method according to claim 9, further comprising:
the controller sends a first power supply control instruction to the power supply management unit according to the second reading request;
the power supply management unit controls the flash memory to enter a working mode according to the first power supply control instruction and sends a reading permission instruction to the controller;
the controller reads the target data from the flash memory according to the read permission instruction, sends the target data to the cache, and sends a second power supply control instruction to the power management unit;
and the power supply management unit adjusts the power supply voltage for the flash memory according to the second power supply control instruction so that the flash memory enters the low power consumption mode.
11. The chip control method according to claim 10, wherein the adjusting, by the power management unit, the power supply voltage to the flash memory according to the second power supply control instruction to enable the flash memory to enter the low power consumption mode comprises:
and the power supply management unit cuts off the power of the flash memory according to the second power supply control instruction, or adjusts the voltage of the flash memory to a preset voltage, wherein the preset voltage is lower than the normal working voltage of the flash memory.
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