CN113971374A - Method and device for determining special password processor - Google Patents
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Abstract
The invention discloses a method and a device for determining a special password processor, which comprise the following steps: acquiring a parameter set of a processor, and determining a first matrix corresponding to a functional component set, a second matrix corresponding to a time-area product set and a third matrix corresponding to a path delay parameter set based on the parameter set of the processor; determining time-area product amplification according to the first matrix, the second matrix and the third matrix; inputting the time-area product amplification and the initially configured fourth matrix into a target energy efficiency analysis model to obtain a target matrix corresponding to the fourth matrix; determining target parameters and values of a processor based on the target matrix; and configuring a functional module of the processor according to the target parameter and the value of the processor to obtain the target password special processor. The method and the device can predict the values of various parameters in the processor frame more accurately and efficiently by using the model, realize that the special password processor meets the actual application requirements, and improve the processing accuracy and efficiency.
Description
Technical Field
The present invention relates to the field of cryptographic technology, and in particular, to a method and an apparatus for determining a cryptographic special process.
Background
Processors are a core component of computers, and their performance and complexity are increasing. The conventional design-implementation-evaluation-improvement method in the processor determination process cannot meet the requirements of the current design application because the iteration time is too long and the cost is too large.
Taking a dedicated cryptographic processor as an example, the dedicated cryptographic processor is a single chip or microprocessor on a dedicated computer for performing encryption operations, is embedded in a physical security measure having a plurality of packages, has tamper-resistant performance, and unlike a cryptographic processor that outputs decrypted data onto a bus in a secure environment, the secure cryptographic processor does not output decrypted data or decrypted program instructions in an environment where security cannot always be maintained. At present, a prediction model based on a regression problem and a prediction model based on a sequencing problem are usually implemented in a determination process of a special password processor, and specifically quantifiable parameters such as storage capacity, instruction transmission parallelism and the like in a functional module of the processor are mainly analyzed, but the influence of the parameters in a functional component cannot be comprehensively determined, so that the finally determined special password processor cannot meet the actual application requirement, and the processing accuracy and efficiency are reduced.
Disclosure of Invention
In order to solve the above problems, the present invention provides a method and an apparatus for determining a special password processor, so that the special password processor meets the actual application requirements, and the processing accuracy and efficiency are improved.
In order to achieve the purpose, the invention provides the following technical scheme:
a method for cryptographic specialized processor determination, comprising:
acquiring a parameter set of a processor, wherein the parameter set at least comprises a functional unit of the processor, a target cryptographic algorithm, a path delay parameter, a time area product and a clock cycle parameter, and the time area product represents the product of the time required by the processor to complete a specific cryptographic algorithm and the area of the processor;
determining a first matrix corresponding to a functional component set, a second matrix corresponding to a time area product set and a third matrix corresponding to a path delay parameter set based on a parameter set of the processor;
determining a time-area product amplification according to the first matrix, the second matrix and the third matrix;
inputting the time area product amplification value and a fourth matrix which is initially configured to a target energy efficiency analysis model to obtain a target matrix corresponding to the fourth matrix, wherein the fourth matrix is a space matrix which is initially configured to a processor, and the target matrix is a matrix which enables the time area product amplification value to be minimum;
determining target parameters and values of a processor based on the target matrix;
and configuring a functional module of the processor according to the target parameter and the value of the processor to obtain the special processor for the target password.
Optionally, the method further comprises:
acquiring training samples corresponding to a processor parameter set, wherein the training samples are space matrixes configured for a plurality of processors, each space matrix configured for the processors corresponds to a group of configuration information, and time area product amplification is marked on each space matrix configured for the processors;
and training based on the training samples to obtain a target energy efficiency analysis model.
Optionally, the training based on the training samples to obtain a target energy efficiency analysis model includes:
extracting a group of configuration information from an unknown configuration set through random sampling, and carrying out simulation calculation on the configuration information to obtain time-area product amplification matched with the configuration information;
comparing the time area product amplification with the marked time area product amplification to determine whether a processor configuration space matrix corresponding to the marked time area product amplification is target configuration information or not, and obtaining a judgment result;
and updating the probability matrix according to the judgment result to complete iterative optimization, and obtaining a target energy efficiency analysis model.
Optionally, the method further comprises:
and creating a probability matrix based on the time-area product amplification and the fourth matrix, wherein the probability matrix represents the relation between the highest energy efficiency probability and the fourth matrix, and the highest energy efficiency probability is the probability that the time-area product amplification is minimum due to the fourth matrix.
Optionally, the updating the probability matrix according to the judgment result to complete iterative optimization to obtain a target energy efficiency analysis model includes:
initializing a configuration matrix K and a probability matrix P, and simulating the initialization configuration matrix K to obtain a time-area product amplification f;
selecting a matrix corresponding to any configuration information in the matrix K, and knowing the highest energy efficiency probability corresponding to all configurations in the configuration set by using the probability matrix P;
determining whether a matrix corresponding to any configuration information is an optimal matrix or not based on the highest energy efficiency probability;
if yes, selecting a matrix corresponding to any configuration information in the matrix K, and knowing the highest energy efficiency probability corresponding to all configurations in the configuration set by using the probability matrix P;
if not, adjusting parameters of elements in the probability matrix P to obtain an updated probability matrix;
and optimizing according to the updated probability matrix to obtain a target energy efficiency analysis model.
A password private processor determining apparatus comprising:
the system comprises a first acquisition unit, a second acquisition unit and a third acquisition unit, wherein the first acquisition unit is used for acquiring a parameter set of the processor, the parameter set at least comprises a functional unit of the processor, a target cryptographic algorithm, a path delay parameter, a time-area product and a clock cycle parameter, and the time-area product represents the product of the time required by the processor to complete a specific cryptographic algorithm and the area of the processor;
a first determining unit, configured to determine, based on a parameter set of the processor, a first matrix corresponding to a functional component set, a second matrix corresponding to a time-area product set, and a third matrix corresponding to a path delay parameter set;
a second determining unit configured to determine a time-area product amplification according to the first matrix, the second matrix, and the third matrix;
the model processing unit is used for inputting the time-area product amplification value and a fourth matrix which is initially configured to a target energy efficiency analysis model to obtain a target matrix corresponding to the fourth matrix, wherein the fourth matrix is a space matrix which is initially configured to the processor, and the target matrix is a matrix which enables the time-area product amplification value to be minimum;
a third determining unit, configured to determine a target parameter and a value of the processor based on the target matrix;
and the configuration unit is used for configuring the functional module of the processor according to the target parameters and the values of the processor to obtain the special processor for the target password.
Optionally, the apparatus further comprises:
the second acquisition unit is used for acquiring training samples corresponding to the processor parameter set, wherein the training samples are space matrixes configured for a plurality of processors, each space matrix configured for the processors corresponds to a group of configuration information, and time area product amplification is marked on each space matrix configured for the processors;
and the training unit is used for training based on the training samples to obtain a target energy efficiency analysis model.
Optionally, the training unit comprises:
the calculation subunit is used for extracting a group of configuration information from an unknown configuration set through random sampling, and carrying out simulation calculation on the configuration information to obtain the time-area product amplification matched with the configuration information;
the comparison subunit is configured to compare the time-area product amplification with the labeled time-area product amplification to determine whether a processor configuration space matrix corresponding to the labeled time-area product amplification is target configuration information, and obtain a determination result;
and the optimization subunit is used for updating the probability matrix according to the judgment result so as to complete iterative optimization and obtain a target energy efficiency analysis model.
Optionally, the apparatus further comprises:
and the creating unit is used for creating a probability matrix based on the time-area product amplification and the fourth matrix, wherein the probability matrix represents the relation between the highest energy efficiency probability and the fourth matrix, and the highest energy efficiency probability is the probability that the time-area product amplification is minimum due to the fourth matrix.
Optionally, the optimization unit is specifically configured to:
initializing a configuration matrix K and a probability matrix P, and simulating the initialization configuration matrix K to obtain a time-area product amplification f;
selecting a matrix corresponding to any configuration information in the matrix K, and knowing the highest energy efficiency probability corresponding to all configurations in the configuration set by using the probability matrix P;
determining whether a matrix corresponding to any configuration information is an optimal matrix or not based on the highest energy efficiency probability;
if yes, selecting a matrix corresponding to any configuration information in the matrix K, and knowing the highest energy efficiency probability corresponding to all configurations in the configuration set by using the probability matrix P;
if not, adjusting parameters of elements in the probability matrix P to obtain an updated probability matrix;
and optimizing according to the updated probability matrix to obtain a target energy efficiency analysis model.
Compared with the prior art, the invention provides a method and a device for determining a special password processor, which comprise the following steps: acquiring a parameter set of a processor, and determining a first matrix corresponding to a functional component set, a second matrix corresponding to a time-area product set and a third matrix corresponding to a path delay parameter set based on the parameter set of the processor; determining time-area product amplification according to the first matrix, the second matrix and the third matrix; inputting the time-area product amplification and the initially configured fourth matrix into a target energy efficiency analysis model to obtain a target matrix corresponding to the fourth matrix; determining target parameters and values of a processor based on the target matrix; and configuring a functional module of the processor according to the target parameter and the value of the processor to obtain the target password special processor. The method and the device can predict the values of various parameters in the processor frame more accurately and efficiently by using the model, realize that the special password processor meets the actual application requirements, and improve the processing accuracy and efficiency.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a flowchart illustrating a method for determining a password for a special purpose processor according to an embodiment of the present invention;
FIG. 2 is a diagram of a probabilistic model learning framework according to an embodiment of the present invention;
FIG. 3 is a flowchart of a probability matrix transfer algorithm according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a device for determining a password special purpose processor according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first" and "second," and the like in the description and claims of the present invention and the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not set forth for a listed step or element but may include steps or elements not listed.
For convenience of explaining technical schemes in the embodiments of the present invention, related terms will now be explained.
A cryptographic specialized processor: a single chip or microprocessor on a special purpose computer is used to perform cryptographic operations, embedded in a physical security measure having multiple packages, with tamper-resistant features. Unlike a secure cryptoprocessor that outputs decrypted data onto a bus in a secure environment, the secure cryptoprocessor does not output decrypted data or decrypted program instructions in an environment where security cannot always be maintained.
Time area product: the product of the time required for the processor to complete an algorithm and the processor area can be used to evaluate the energy efficiency of the processor.
The highest energy efficiency probability: the probability that the currently configured processor is most energy efficient in the processor configuration space.
Energy efficiency probability model: the method is a model which takes probability as a target parameter and is used for judging whether the configuration is the most efficient configuration in the current design space.
Referring to fig. 1, a flow diagram of a method for determining a special password processor according to an embodiment of the present invention is provided, where the method is mainly used to achieve the purpose of configuring the special password processor, and a processor generally has a plurality of functional units, and there may be a plurality of parameters of corresponding functional units, and different cryptographic algorithms or cryptographic processing environments have different performance requirements on the processor.
Specifically, the method may comprise the steps of:
s101, acquiring a parameter set of the processor.
The parameter set includes various functional components that can affect the energy efficiency of the processor, and corresponding processing parameters. At least comprising functional components of the processor, a target cryptographic algorithm, a path delay parameter, a time-area product characterizing a product of a time required for the processor to complete a particular cryptographic algorithm and a processor area, and a clock cycle parameter
The energy efficiency of a processor core is defined as the ratio of chip performance to power consumption in bps/W. Therefore, describing the energy efficiency of the processor core requires acquiring two parameters of the performance and the power consumption of the chip. The performance parameters can be approximately evaluated through logic synthesis in the design stage, and the power consumption data can be accurately acquired only after the design of the rear end of the chip is completed. If the ratio of performance to power consumption is directly used as an evaluation index, longer time and cost are needed for design iteration. Therefore, the energy efficiency of the processor is typically approximated using a time-area product parameter.
Whether the cryptographic special processor meets the high-energy-efficiency target needs to be embodied in the process of executing a specific algorithm, and the algorithm sets are different, so that the configuration sets required by the processor to reach the high-energy-efficiency target are necessarily different. To describe the impact of the algorithm on processor energy efficiency, the set of target algorithms is described as { y }1,y2,...,ymIn which y islI.e. to represent a specific cryptographic algorithm, such as the AES algorithm or the like. Setting a configuration of cryptographic processor cores to complete algorithm ylThe required Time is TimelThe total Area of the cryptographic processor core is Area, then the cryptographic processor core completes the time Area product W of the algorithmlCan be represented by formula (1).
Wl＝Timel·Area (1)
When the comprehensive energy efficiency of all algorithms in the algorithm execution set is considered comprehensively, the most obvious way is to add the time area products of the algorithms to obtain the total time area product W, which is shown in equation (2).
Obviously, as shown in equation (2), the influence of the time-area product of executing each algorithm on the total time-area product W is balanced. Then W for the algorithm with the larger number of instructionslThe larger the value, the larger the ratio thereof in the total time-area product W, and the larger the influence on the value thereof. In the experimental process, the search result is easy to be biased to the algorithm with a large number of instructions. Therefore, in order to balance the influence of the system difference of each cryptographic algorithm on the energy analysis process, the time-area product amplification f is adopted in the embodiment of the inventionlThe sum is used as a final evaluation standard, and the total time area product amplification f is expressed as a formula (3), wherein Wl0Y representing implementation of a cryptographic algorithm by a reference configuration processor selected from a design spacelTime area product.
In summary, the goal of an energy efficient crypto-specific processor is to find an architectural configuration that minimizes the overall time-area product increase f.
A cryptographic specialized processor must be able to perform all of its required operations to implement a target set of algorithms, but there may be many different implementations of the same operation. Taking the arithmetic unit as an example, a three-input boolean function can be implemented by using a basic two-input logic gate cascade, a basic three-input logic gate cascade, or a three-input logic array. The critical path delay, the size and the required clock period number of the three implementations are all different, and the final energy efficiency is determined by the three implementations. It is difficult to determine which granularity and bit width of the basic operation unit of the password has higher energy efficiency through qualitative analysis. When the arithmetic unit is integrated into a processor, the delay and the size of the arithmetic unit are limited by the self-architecture of the processor and other arithmetic units, and the situation is more complicated. Taking the memory location as an example, instruction and data memory is required to implement any cryptographic algorithm. The instruction and data memories have different cache numbers, storage capacities, instruction fetching bit widths, instruction fetching delays, instruction densities and the like, and the constructed memory system has different instruction execution numbers, highest operating frequency and areas in each cycle. These differences affect the overall architecture and necessarily also the overall energy efficiency of the processor. In addition, some processor optimization techniques, such as: branch processing techniques, addressing mode optimization techniques, data-dependent processing techniques, etc., also impact processor energy efficiency.
Analyzing the above-mentioned influencing factors one by one to construct a processor architecture prediction model is too complicated and difficult to analyze comprehensively. However, in order to address the processor energy efficiency itself, in any of the above implementations, different cryptographic processor components (including storage, arithmetic, branching, and the like) affect the main frequency and scale of the processor and the number of clock cycles required to complete the algorithm, further affecting the overall energy efficiency of the cryptographic processor. Therefore, the problem of the design space exploration of the processor architecture can be mathematized only by paying attention to the three attributes of the inherent dominant frequency, scale and clock cycles required for completing the algorithm.
Specifically, the expression of the mathematical mode in the architecture of the special-purpose cryptographic processor is analyzed by taking the influence of various key factors in the architecture design of the special-purpose cryptographic processor on energy efficiency as a starting point.
If any processor is configured in one configuration, it performs a certain cryptographic algorithm ylTime area product W oflIt can be further expressed as formula (4), the total time-area product increase f can be expressed as formula (5), the related parameters in formula (4) and formula (5) are explained as shown in table 1, and each parameter in table 1 is a related parameter in the processor parameter set.
TABLE 1 parameter List
Each functional part xiThe difference between them mainly comes from the difference in function, granularity and bit width. The functional difference comprises the existence of an operation accelerating unit, the existence of caches at all levels, the existence of a branch prediction mechanism and the like; the differences between the granularity and the bit width include the granularity and the bit width of the processor acceleration unit, the capacity of the storage unit, the bit width of the instruction transmission, and other quantifiable parameters, and for a certain fixed functional unit, the parameters often have a certain fixed association relationship, for example, the association relationship between the parameters can be represented by a functional relationship.
S102, determining a first matrix corresponding to the functional component set, a second matrix corresponding to the time area product set and a third matrix corresponding to the path delay parameter set based on the parameter set of the processor.
And S103, determining time-area product amplification according to the first matrix, the second matrix and the third matrix.
Assuming that a total of a functions are available from the functional units of the processor and b total of granularity and bit width value ranges, k1,k2,...,knPossible values ofSpace is 2abAnd (4) seed preparation. However, units of different granularity and bit width but identical function do not exist simultaneously, and therefore, { k }1,k2,...,knThe values of the users have certain mutual exclusion relationship. To embody this mutual exclusion relationship, the present invention will { k }1,k2,...,knRewriting into a matrix form, so that each row in the matrix represents the same functional unit, and increasing from left to right according to granularity and bit width. The matrix K after rewriting is expressed as formula (6). Obviously, one and only one bit per row of matrix K is 1.
K＝{kij|0＜i≤a,0＜j≤b} (6)
In correspondence with the K matrix, the function block set, the area set, and the delay set are also rewritten into a matrix form, and equation (5) can be further expressed as equation (10) as shown in equations (7), (8), and (9).
X＝{xij|0＜i≤a,0＜j≤b} (7)
S＝{sij|0＜i≤a,0＜j≤b} (8)
T＝{tij|0＜i≤a,0＜j≤b} (9)
At this point, the energy efficient crypto-specific processor design problem may be described as a "1" value location problem in the matrix K. That is, when the "1" in each row element of the K matrix is located at what position, the total time-area product amplification f is made to take the minimum value.
And S104, inputting the time-area product amplification and the initially configured fourth matrix into a target energy efficiency analysis model, and obtaining a target matrix corresponding to the fourth matrix.
The fourth matrix is a space matrix for initial configuration of the processor, i.e., the matrix K in the above description. The target matrix is the matrix that minimizes the time-area product amplification.
The model learning framework predicts all configurations in a design space by taking the highest energy efficiency probability as a training target, and obtains a configuration matrix K which enables the highest energy efficiency probability to be the maximum. The present invention will be described in detail in the following examples.
S105, determining target parameters and values of the processor based on the target matrix;
and S106, configuring a functional module of the processor according to the target parameter and the value of the processor to obtain the special processor for the target password.
After the target matrix is determined, the corresponding target parameters of the processor can be obtained, the target parameters can be parameters representing the types of the functional components or specific processing parameters, and when a certain parameter has multiple values, the corresponding value or value range can be determined according to the target matrix.
And then, configuring a functional module of the current processor based on the target parameters and the values, so that the configured and generated target password special processor is more consistent with the current application scene or more consistent with the encryption algorithm to be executed currently.
The embodiment of the invention provides a method for determining a special password processor, which comprises the following steps: acquiring a parameter set of a processor, and determining a first matrix corresponding to a functional component set, a second matrix corresponding to a time-area product set and a third matrix corresponding to a path delay parameter set based on the parameter set of the processor; determining time-area product amplification according to the first matrix, the second matrix and the third matrix; inputting the time-area product amplification and the initially configured fourth matrix into a target energy efficiency analysis model to obtain a target matrix corresponding to the fourth matrix; determining target parameters and values of a processor based on the target matrix; and configuring a functional module of the processor according to the target parameter and the value of the processor to obtain the target password special processor. The method and the device can predict the values of various parameters in the processor frame more accurately and efficiently by using the model, realize that the special password processor meets the actual application requirements, and improve the processing accuracy and efficiency.
In an implementation manner of the embodiment of the present invention, the process of generating the target energy efficiency analysis model includes:
and acquiring a training sample corresponding to the processor parameter set, and training based on the training sample to obtain a target energy efficiency analysis model. The training sample configures space matrixes for a plurality of processors, each processor configures the space matrix corresponding to a group of configuration information, and time area product amplification is marked on each processor configures the space matrix. Correspondingly, in the training stage, n configurations are sampled from the design space, and a highest energy efficiency probability model is trained. In the stage of predicting by using the model, all configurations in the design control are predicted, and a configuration matrix K which enables the highest probability of energy efficiency to be the maximum is found, namely the configuration to be obtained.
Correspondingly, the training based on the training sample to obtain a target energy efficiency analysis model includes:
extracting a group of configuration information from an unknown configuration set through random sampling, and carrying out simulation calculation on the configuration information to obtain time-area product amplification matched with the configuration information;
comparing the time area product amplification with the marked time area product amplification to determine whether a processor configuration space matrix corresponding to the marked time area product amplification is target configuration information or not, and obtaining a judgment result;
and updating the probability matrix according to the judgment result to complete iterative optimization, and obtaining a target energy efficiency analysis model.
In the embodiment of the present invention, iterative optimization is completed in a model training process through a probability matrix, wherein the iterative optimization further includes:
and creating a probability matrix based on the time-area product amplification and the fourth matrix, wherein the probability matrix represents the relation between the highest energy efficiency probability and the fourth matrix, and the highest energy efficiency probability is the probability that the time-area product amplification is minimum due to the fourth matrix.
Further, the updating the probability matrix according to the judgment result to complete iterative optimization to obtain a target energy efficiency analysis model includes:
initializing a configuration matrix K and a probability matrix P, and simulating the initialization configuration matrix K to obtain a time-area product amplification f;
selecting a matrix corresponding to any configuration information in the matrix K, and knowing the highest energy efficiency probability corresponding to all configurations in the configuration set by using the probability matrix P;
determining whether a matrix corresponding to any configuration information is an optimal matrix or not based on the highest energy efficiency probability;
if yes, selecting a matrix corresponding to any configuration information in the matrix K, and knowing the highest energy efficiency probability corresponding to all configurations in the configuration set by using the probability matrix P;
if not, adjusting parameters of elements in the probability matrix P to obtain an updated probability matrix;
and optimizing according to the updated probability matrix to obtain a target energy efficiency analysis model.
Specifically, after each information set is converted into a corresponding matrix, an expression of time-area product amplification, that is, expression (10) in the above description, is obtained. t is tijAnd sijAll can obtain its value by performing logic synthesis on the cryptographic processor architecture if CyclelAnd the relation between the matrix K and the matrix K is determined, and the optimal configuration can be solved by using an optimization algorithm. However, CyclelThe relation with the matrix K cannot be expressed by using a specific function form, and only under the condition that the matrix K is known, a specific numerical value of the matrix K is obtained by compiling simulation. Considering the possible values of the K matrix at this time, baSpecies, inability to determine Cycle by exhaustive compilationlThe relationship to matrix K. Therefore, other methods need to be sought to model f with respect to the matrix K.
In this case, the machine learning modeling mode which does not depend on specific logic but depends on data relation fully shows the advantages of the machine learning modeling mode, and can effectively assist in establishing the energy efficiency analysis model of the matrix K.
The purpose of establishing the energy efficiency analysis model of the special password processor is to find a matrix K which enables the value of f to be minimum. Without being exhaustive, the invention preferably seeks to find a matrix K that is most likely to minimize the value of f. Namely, a relation between the highest energy efficiency probability PW (the probability that f takes the minimum value through the matrix K) and the matrix K is established.
Referring to fig. 2, a probabilistic model learning framework provided for the embodiment of the present invention is composed of a training phase and a prediction phase. In the training phase, the framework samples n configurations from the design space and trains a most energy efficient probabilistic model. In the prediction stage, all configurations in the design space are predicted according to the highest energy efficiency probability model, and a configuration matrix K which enables the highest energy efficiency probability to be the maximum is found, namely the configuration is obtained. The probability model learning framework takes the highest energy efficiency probability as a training target and can assist in building the energy efficiency probability model of the special password processor.
In fig. 2, the key to training the probabilistic model is the probability matrix transfer algorithm, which directly determines the training efficiency and the accuracy of the probabilistic model. In order to design a reasonable probability matrix transfer algorithm, the relation between the highest energy efficiency probability PW and the matrix K is expressed through a probability matrix P in the embodiment of the invention. Element P in probability matrix PijIndicating that the value of "1" stays at kijThe probability that the time-total area product increases by the minimum value f. Since each row in the K matrix has only one "1" element, and the positions of the "1" elements in each row are independent of each other, it is obvious that the probabilities PW and p of the highest energy efficiency are the sameijHas the relationship shown in formula (11). Wherein p isijThe formula (12) is satisfied. According to the probability matrix P, the invention can predict the probability that any configuration in the configuration database is configured as the optimal configuration.
At the beginning, probabilityElement P in matrix PijThe probability that the reciprocal of the number of the elements of the row, i.e., the value of "1", appears at any position of the row is equal, and is 1/b. In the learning process, one configuration is extracted from an unknown configuration set through random sampling, the actual value f of the configuration is compiled and simulated, the value is compared with a marked configuration set, whether the newly sampled configuration is optimal in the known configuration set is judged, and the value of the probability matrix is updated by utilizing the judgment result. Through multiple iterative optimization, when the prediction result of r times is consistent with the actual measurement result, the training is stopped, r is a control parameter of the learning algorithm, and the larger the value is, the higher the training accuracy is, and the larger the training amount is.
In summary, the flow chart of the probability matrix transfer algorithm is shown in fig. 3, and the specific flow is as follows:
1) initializing a configuration matrix K and a probability matrix P. The first column in the matrix K is "1", and the remaining elements are "0"; element P in probability matrix PijIs the reciprocal of the number of the elements in the row; the total energy efficiency ratio f corresponding to the simulation initial matrix K is recorded as fmin(ii) a The initialization control parameter success is 0.
2) Configuration K for randomly selecting matrix KiCalculating the highest energy efficiency probability respectively corresponding to all configurations in the known configuration set by using the probability matrix P, and judging a newly selected matrix KiWhether it is an optimal configuration.
3) Simulation acquisition of a newly selected matrix KiCorresponding total energy efficiency ratio fiCalculating delta as fi-fminIf δ > 0 means that the configuration is not the optimal configuration, otherwise, the configuration is the currently known optimal configuration.
4) Comparing the prediction result of the step 2) with the actual measurement result of the step 3), and if the results are consistent, judging that success is success + 1; otherwise, success is 0.
5) If delta > 0, i.e. the configuration is not the optimal configuration, the configuration is assigned p of the corresponding positionijBy reducing a parameter α (α being a probability matrix adjustment parameter, determining the learning rate of the algorithm), p, of the remaining positions of the rowijIncreasing alpha/b; conversely, increase a parameter α, p of the remaining position of the rowijReducing alpha/b; the probability matrix P is updated.
6) If success is r, outputting a probability matrix P, and finishing the algorithm; otherwise, return to operation 2).
The invention analyzes the difference between the design problem of the special processor in the password field and the design problem of the general processor, abstracts the design problem of the special processor in the password field into a mathematical problem and provides a probability matrix transfer algorithm to assist the establishment of a model. By utilizing the model, the values of various parameters in the processor framework can be predicted more accurately and efficiently, and designers are assisted to construct high-energy-efficiency special processors for passwords with different application requirements more efficiently.
The specific application example is used to describe the method for determining a password special processor provided by the embodiment of the invention.
The energy efficiency probability model is applied on the premise that a basic processor framework is provided, and the model is used for determining values of variable parameters in the framework. Meanwhile, the model is influenced by the set of cryptographic application algorithms, and needs to be processed for a certain fixed set of algorithms.
Therefore, if the model is applied to analyze the types of the operation units and the relevant parameters of each unit in a special encryption processor, the model analyzes the structural characteristics of more than ten common encryption algorithms including grouping, sequence and hash encryption algorithms, classifies the operation types of the operation algorithms, extracts the fine-grained common logic of the common encryption algorithms, and designs the corresponding encryption operation units according to the fine-grained common logic.
Selecting common grouping, sequence, hash and public key cryptographic algorithm set including DES, AES, SM4, IDEA, A5-1, SM3, MD5, SHA256, Grain, ZUC, SNOW, RC4, CHACHACHA 20, RSA, ECC and the like. The 13 kinds of cryptographic accelerating units are designed according to the algorithm set, and a plurality of parameters to be determined in the 13 kinds of cryptographic accelerating unit structural design are selected by the experience of a designer. For example, in a typical symmetric crypto acceleration unit design, the width, depth, number of memory slices, etc. of the S-box memory region; as another example. In a typical asymmetric cryptographic acceleration unit design, a word block bit width, a shift register size, a logical operation unit parallelism and the like are processed at one time. If only the energy efficiency of one acceleration unit needs to be considered independently, the optimal design parameter is easy to determine, but when the combined action condition of a plurality of operation units is considered simultaneously, the design parameter with the optimal energy efficiency is difficult to determine due to the mutual influence of the operation units. Therefore, based on an energy efficiency probability model, design space exploration is carried out in the module libraries of the cryptographic acceleration units, an optimal module combination mode is sought, and relevant parameters of each module are determined.
Referring to Table 2, the spatial composition is designed for the cryptographic specialized processor, and the final cryptographic specialized processor is determined based on the relevant information in the design space.
TABLE 2 crypto-specific processor design space composition
In table 2, 13 proposed cryptographic acceleration operation units are applied in the energy efficiency probability model, i.e. the parameter a in the K matrix is 13. Four granularity designs are adopted for the 13 kinds of cryptographic operation units respectively, and the condition that the cryptographic operation unit is not expanded is added, so that 5 kinds of granularity are selected in total (the condition that the granularity is not expanded is equivalent to 0), namely, the parameter b in the K matrix is 5. The design space scale of the calculation acceleration unit is 513＝1,220,703,125。
The method comprises the steps of performing logic synthesis on 52 operation units in a design space under a CMOS 55 nanometer (1.2V, 25 ℃) process, collecting the area of the operation units and a key path delay structure S matrix and a key path delay structure T matrix, starting an energy efficiency probability model training program under the control of a parameter r being 20 and a parameter alpha being 0.01, and obtaining a design space exploration result through about 2240 iterations, wherein the design space exploration result is shown in table 3.
TABLE 3 crypto-specific processor design space composition
Wherein, no area in table 3 includes a storage area, and the storage parts in the unit design are uniformly integrated into the processor access level, similar to the data storage.
From the above table, a specific processor for the cipher is determined, so that the processor can obtain the highest possible performance value when the processor implements the set of cryptographic algorithms set forth above.
There is also provided in another embodiment of the present invention a password specific processor determining apparatus, see fig. 4, including:
a first obtaining unit 10, configured to obtain a parameter set of a processor, where the parameter set at least includes a functional unit of the processor, a target cryptographic algorithm, a path delay parameter, a time-area product, and a clock cycle parameter, and the time-area product represents a product of a time required by the processor to complete a specific cryptographic algorithm and a processor area;
a first determining unit 20, configured to determine, based on the parameter set of the processor, a first matrix corresponding to the functional component set, a second matrix corresponding to the time-area product set, and a third matrix corresponding to the path delay parameter set;
a second determining unit 30, configured to determine a time-area product amplification according to the first matrix, the second matrix, and the third matrix;
the model processing unit 40 is configured to input the time-area product amplification value and a fourth matrix initially configured to a target energy efficiency analysis model, and obtain a target matrix corresponding to the fourth matrix, where the fourth matrix is a spatial matrix initially configured by the processor, and the target matrix is a matrix that minimizes the time-area product amplification value;
a third determining unit 50, configured to determine a target parameter and a value of the processor based on the target matrix;
and a configuration unit 60, configured to configure the functional module of the processor according to the target parameter and the value of the processor, so as to obtain the target password special processor.
Further, the apparatus further comprises:
the second acquisition unit is used for acquiring training samples corresponding to the processor parameter set, wherein the training samples are space matrixes configured for a plurality of processors, each space matrix configured for the processors corresponds to a group of configuration information, and time area product amplification is marked on each space matrix configured for the processors;
and the training unit is used for training based on the training samples to obtain a target energy efficiency analysis model.
In one embodiment, the training unit comprises:
the calculation subunit is used for extracting a group of configuration information from an unknown configuration set through random sampling, and carrying out simulation calculation on the configuration information to obtain the time-area product amplification matched with the configuration information;
the comparison subunit is configured to compare the time-area product amplification with the labeled time-area product amplification to determine whether a processor configuration space matrix corresponding to the labeled time-area product amplification is target configuration information, and obtain a determination result;
and the optimization subunit is used for updating the probability matrix according to the judgment result so as to complete iterative optimization and obtain a target energy efficiency analysis model.
Further, the apparatus further comprises:
and the creating unit is used for creating a probability matrix based on the time-area product amplification and the fourth matrix, wherein the probability matrix represents the relation between the highest energy efficiency probability and the fourth matrix, and the highest energy efficiency probability is the probability that the time-area product amplification is minimum due to the fourth matrix.
Optionally, the optimization unit is specifically configured to:
initializing a configuration matrix K and a probability matrix P, and simulating the initialization configuration matrix K to obtain a time-area product amplification f;
selecting a matrix corresponding to any configuration information in the matrix K, and knowing the highest energy efficiency probability corresponding to all configurations in the configuration set by using the probability matrix P;
determining whether a matrix corresponding to any configuration information is an optimal matrix or not based on the highest energy efficiency probability;
if yes, selecting a matrix corresponding to any configuration information in the matrix K, and knowing the highest energy efficiency probability corresponding to all configurations in the configuration set by using the probability matrix P;
if not, adjusting parameters of elements in the probability matrix P to obtain an updated probability matrix;
and optimizing according to the updated probability matrix to obtain a target energy efficiency analysis model.
The embodiment of the invention provides a device for determining a special password processor, which comprises: acquiring a parameter set of a processor, and determining a first matrix corresponding to a functional component set, a second matrix corresponding to a time-area product set and a third matrix corresponding to a path delay parameter set based on the parameter set of the processor; determining time-area product amplification according to the first matrix, the second matrix and the third matrix; inputting the time-area product amplification and the initially configured fourth matrix into a target energy efficiency analysis model to obtain a target matrix corresponding to the fourth matrix; determining target parameters and values of a processor based on the target matrix; and configuring a functional module of the processor according to the target parameter and the value of the processor to obtain the target password special processor. The method and the device can predict the values of various parameters in the processor frame more accurately and efficiently by using the model, realize that the special password processor meets the actual application requirements, and improve the processing accuracy and efficiency.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method for determining a cryptogram processor, comprising:
acquiring a parameter set of a processor, wherein the parameter set at least comprises a functional unit of the processor, a target cryptographic algorithm, a path delay parameter, a time area product and a clock cycle parameter, and the time area product represents the product of the time required by the processor to complete a specific cryptographic algorithm and the area of the processor;
determining a first matrix corresponding to a functional component set, a second matrix corresponding to a time area product set and a third matrix corresponding to a path delay parameter set based on a parameter set of the processor;
determining a time-area product amplification according to the first matrix, the second matrix and the third matrix;
inputting the time area product amplification value and a fourth matrix which is initially configured to a target energy efficiency analysis model to obtain a target matrix corresponding to the fourth matrix, wherein the fourth matrix is a space matrix which is initially configured to a processor, and the target matrix is a matrix which enables the time area product amplification value to be minimum;
determining target parameters and values of a processor based on the target matrix;
and configuring a functional module of the processor according to the target parameter and the value of the processor to obtain the special processor for the target password.
2. The method of claim 1, further comprising:
acquiring training samples corresponding to a processor parameter set, wherein the training samples are space matrixes configured for a plurality of processors, each space matrix configured for the processors corresponds to a group of configuration information, and time area product amplification is marked on each space matrix configured for the processors;
and training based on the training samples to obtain a target energy efficiency analysis model.
3. The method according to claim 2, wherein the training based on the training samples to obtain a target energy efficiency analysis model comprises:
extracting a group of configuration information from an unknown configuration set through random sampling, and carrying out simulation calculation on the configuration information to obtain time-area product amplification matched with the configuration information;
comparing the time area product amplification with the marked time area product amplification to determine whether a processor configuration space matrix corresponding to the marked time area product amplification is target configuration information or not, and obtaining a judgment result;
and updating the probability matrix according to the judgment result to complete iterative optimization, and obtaining a target energy efficiency analysis model.
4. The method of claim 3, further comprising:
and creating a probability matrix based on the time-area product amplification and the fourth matrix, wherein the probability matrix represents the relation between the highest energy efficiency probability and the fourth matrix, and the highest energy efficiency probability is the probability that the time-area product amplification is minimum due to the fourth matrix.
5. The method according to claim 3, wherein the updating the probability matrix according to the judgment result to complete iterative optimization to obtain a target energy efficiency analysis model comprises:
initializing a configuration matrix K and a probability matrix P, and simulating the initialization configuration matrix K to obtain a time-area product amplification f;
selecting a matrix corresponding to any configuration information in the matrix K, and knowing the highest energy efficiency probability corresponding to all configurations in the configuration set by using the probability matrix P;
determining whether a matrix corresponding to any configuration information is an optimal matrix or not based on the highest energy efficiency probability;
if yes, selecting a matrix corresponding to any configuration information in the matrix K, and knowing the highest energy efficiency probability corresponding to all configurations in the configuration set by using the probability matrix P;
if not, adjusting parameters of elements in the probability matrix P to obtain an updated probability matrix;
and optimizing according to the updated probability matrix to obtain a target energy efficiency analysis model.
6. A crypto processor determination device, comprising:
the system comprises a first acquisition unit, a second acquisition unit and a third acquisition unit, wherein the first acquisition unit is used for acquiring a parameter set of the processor, the parameter set at least comprises a functional unit of the processor, a target cryptographic algorithm, a path delay parameter, a time-area product and a clock cycle parameter, and the time-area product represents the product of the time required by the processor to complete a specific cryptographic algorithm and the area of the processor;
a first determining unit, configured to determine, based on a parameter set of the processor, a first matrix corresponding to a functional component set, a second matrix corresponding to a time-area product set, and a third matrix corresponding to a path delay parameter set;
a second determining unit configured to determine a time-area product amplification according to the first matrix, the second matrix, and the third matrix;
the model processing unit is used for inputting the time-area product amplification value and a fourth matrix which is initially configured to a target energy efficiency analysis model to obtain a target matrix corresponding to the fourth matrix, wherein the fourth matrix is a space matrix which is initially configured to the processor, and the target matrix is a matrix which enables the time-area product amplification value to be minimum;
a third determining unit, configured to determine a target parameter and a value of the processor based on the target matrix;
and the configuration unit is used for configuring the functional module of the processor according to the target parameters and the values of the processor to obtain the special processor for the target password.
7. The apparatus of claim 6, further comprising:
the second acquisition unit is used for acquiring training samples corresponding to the processor parameter set, wherein the training samples are space matrixes configured for a plurality of processors, each space matrix configured for the processors corresponds to a group of configuration information, and time area product amplification is marked on each space matrix configured for the processors;
and the training unit is used for training based on the training samples to obtain a target energy efficiency analysis model.
8. The apparatus of claim 7, wherein the training unit comprises:
the calculation subunit is used for extracting a group of configuration information from an unknown configuration set through random sampling, and carrying out simulation calculation on the configuration information to obtain the time-area product amplification matched with the configuration information;
the comparison subunit is configured to compare the time-area product amplification with the labeled time-area product amplification to determine whether a processor configuration space matrix corresponding to the labeled time-area product amplification is target configuration information, and obtain a determination result;
and the optimization subunit is used for updating the probability matrix according to the judgment result so as to complete iterative optimization and obtain a target energy efficiency analysis model.
9. The apparatus of claim 8, further comprising:
and the creating unit is used for creating a probability matrix based on the time-area product amplification and the fourth matrix, wherein the probability matrix represents the relation between the highest energy efficiency probability and the fourth matrix, and the highest energy efficiency probability is the probability that the time-area product amplification is minimum due to the fourth matrix.
10. The apparatus according to claim 8, wherein the optimization unit is specifically configured to:
initializing a configuration matrix K and a probability matrix P, and simulating the initialization configuration matrix K to obtain a time-area product amplification f;
selecting a matrix corresponding to any configuration information in the matrix K, and knowing the highest energy efficiency probability corresponding to all configurations in the configuration set by using the probability matrix P;
determining whether a matrix corresponding to any configuration information is an optimal matrix or not based on the highest energy efficiency probability;
if yes, selecting a matrix corresponding to any configuration information in the matrix K, and knowing the highest energy efficiency probability corresponding to all configurations in the configuration set by using the probability matrix P;
if not, adjusting parameters of elements in the probability matrix P to obtain an updated probability matrix;
and optimizing according to the updated probability matrix to obtain a target energy efficiency analysis model.
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