CN113966529A

CN113966529A - Pixel circuit, driving method thereof and display device

Info

Publication number: CN113966529A
Application number: CN202080000281.4A
Authority: CN
Inventors: 玄明花; 齐琪; 刘静; 岳晗; 刘冬妮
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2020-03-17
Filing date: 2020-03-17
Publication date: 2022-01-21
Anticipated expiration: 2040-03-17
Also published as: CN113966529B; US11468825B2; US20220114949A1; WO2021184192A1

Abstract

The present disclosure provides a pixel circuit, including: current control circuit and time control circuit, time control circuit includes: a first reset sub-circuit configured to write a reference voltage and a first initialization voltage to a first node and a second node, respectively, in response to control of a signal of a first reset signal line; a first data writing sub-circuit configured to write a first data voltage to a first node in response to control of a signal of the first gate line; a first threshold compensation sub-circuit configured to perform threshold compensation on a transistor within the switching sub-circuit in response to control of a signal of the first gate line; a ramp writing sub-circuit configured to write a preset ramp signal to the first node in response to control of a signal of the control signal line; and the switch subcircuit is configured to control the connection and disconnection between the third node and the fourth node in response to the control of the voltage at the second node. The disclosure also provides a driving method of the pixel circuit and a display device.

Description

Pixel circuit, driving method thereof and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, and a display device.

Background

Micro Light Emitting Diode (Micro-LED) technology is to integrate a Micro-sized LED array on one chip with high density to realize the thinning, miniaturization and matrixing of LEDs, the distance between pixels can reach the micron level, and each pixel can address and emit Light individually. Micro-LED display panels are gradually developing towards display panels used by consumer terminals due to their characteristics of low driving voltage, long lifetime, wide temperature resistance, etc.

Disclosure of Invention

The embodiment of the disclosure provides a pixel circuit, a driving method thereof and a display device, which can prompt the display effect of the display device.

In a first aspect, an embodiment of the present disclosure provides a pixel circuit, including: a current control circuit and a time control circuit, the current control circuit configured to generate a drive current and output the drive current to the time control circuit, wherein the time control circuit comprises: the first reset sub-circuit, the first data write sub-circuit, the ramp wave write sub-circuit and the switch sub-circuit are connected to a first node, the first reset sub-circuit, the first threshold compensation sub-circuit and the switch sub-circuit are connected to a second node, the first threshold compensation sub-circuit, the switch sub-circuit and the current control circuit are connected to a third node, and the first threshold compensation sub-circuit, the switch sub-circuit and the element to be driven are connected to a fourth node;

the first reset sub-circuit configured to write a reference voltage and a first initialization voltage to the first node and the second node, respectively, in response to control of a signal of a first reset signal line;

the first data writing sub-circuit configured to write a first data voltage to the first node in response to control of a signal of the first gate line;

the first threshold compensation sub-circuit is configured to respond to the control of the signal of the first grid line, write the reference voltage into the third node and perform threshold compensation on a transistor in the switch sub-circuit;

the ramp writing sub-circuit is configured to write a preset ramp signal to the first node in response to control of a signal of a control signal line;

the switch subcircuit is configured to adjust the voltage at the second node according to the voltage difference between the voltage loaded with the ramp signal at the first node and the first data voltage, and to control the on-off between the third node and the fourth node in response to the control of the voltage at the second node.

In some embodiments, the first reset subcircuit includes: a first transistor and a second transistor;

a control electrode of the first transistor is connected with the first reset signal line, a first electrode of the first transistor is connected with a reference voltage end, and a second electrode of the first transistor is connected with the first node;

the control electrode of the second transistor is connected with the first reset signal line, the first electrode of the second transistor is connected with the first initialization voltage end, and the second electrode of the second transistor is connected with the second node.

In some embodiments, the first data write subcircuit includes: a third transistor;

a control electrode of the third transistor is connected to the first gate line, a first electrode of the third transistor is connected to a first data line, and a second electrode of the third transistor is connected to the first node.

In some embodiments, the first threshold compensation sub-circuit comprises: a fourth transistor and a fifth transistor;

a control electrode of the fourth transistor is connected with the first grid line, a first electrode of the fourth transistor is connected with a reference voltage end, and a second electrode of the fourth transistor is connected with the third node;

a control electrode of the fifth transistor is connected to the first gate line, a first electrode of the fifth transistor is connected to the second node, and a second electrode of the fifth transistor is connected to the fourth node.

In some embodiments, the ramp write sub-circuit comprises: a sixth transistor;

and a control electrode of the sixth transistor is connected with a control signal line, a first electrode of the sixth transistor is connected with a ramp signal line, and a second electrode of the sixth transistor is connected with the first node.

In some embodiments, the switch sub-circuit comprises: a seventh transistor and a first capacitor;

a control electrode of the seventh transistor is connected to the second node, a first electrode of the seventh transistor is connected to the third node, and a second electrode of the seventh transistor is connected to the fourth node;

the first end of the first capacitor is connected with the first node, and the second end of the first capacitor is connected with the second node.

In some embodiments, the pixel circuit further comprises: a first output control sub-circuit through which the element to be driven is connected to the fourth node;

the first output control sub-circuit is configured to control on/off between the fourth node and the element to be driven in response to control of a signal of the control signal line.

In some embodiments, the first output control sub-circuit comprises: an eighth transistor;

and a control electrode of the eighth transistor is connected with the control signal line, a first electrode of the eighth transistor is connected with the fourth node, and a second electrode of the eighth transistor is connected with the element to be driven.

In some embodiments, a signal line that provides the first data voltage to the first data writing sub-circuit and a signal line that provides the ramp signal to the ramp writing sub-circuit are the same signal line.

In some embodiments, the current control circuit comprises: the second reset sub-circuit, the control electrode of the driving transistor and the second threshold compensation sub-circuit are connected to a fifth node, the first electrode of the driving transistor, the second data write sub-circuit and the second output control sub-circuit are connected to a sixth node, and the second electrode of the driving transistor, the second threshold compensation sub-circuit and the second output control sub-circuit are connected to a seventh node;

the second reset sub-circuit configured to write a second initialization voltage to the fifth node in response to control of a signal of a second reset signal line;

the second data writing sub-circuit configured to write a second data voltage to the sixth node in response to control of a signal of a second gate line;

the second threshold compensation sub-circuit is configured to perform threshold compensation on the driving transistor in response to control of a signal of the second gate line;

the second output control sub-circuit is connected with the third node, and is configured to respond to the control of the signal of the control signal line, write a first working voltage into the sixth node, and control the conduction between the third node and the seventh node;

the driving transistor is configured to respond to the control of the voltage at the fifth node and output corresponding driving current;

and the first end of the second capacitor is connected with the first working voltage end, and the second end of the second capacitor is connected with the fifth node.

In some embodiments, the second reset sub-circuit comprises: a ninth transistor, the second data writing sub-circuit including: a tenth transistor, the second threshold compensation sub-circuit comprising: an eleventh transistor, the second output control sub-circuit comprising: a twelfth transistor and a thirteenth transistor;

a control electrode of the ninth transistor is connected to the second reset signal line, a first electrode of the ninth transistor is connected to a second initialization voltage terminal, and a second electrode of the ninth transistor is connected to the fifth node;

a control electrode of the tenth transistor is connected to the second gate line, a first electrode of the tenth transistor is connected to the second data line, and a second electrode of the tenth transistor is connected to the sixth node;

a control electrode of the eleventh transistor is connected to the second gate line, a first electrode of the eleventh transistor is connected to the fifth node, and a second electrode of the eleventh transistor is connected to the seventh node;

a control electrode of the twelfth transistor is connected with the control signal line, a first electrode of the twelfth transistor is connected with the first working voltage end, and a second electrode of the twelfth transistor is connected with the sixth node;

a control electrode of the thirteenth transistor is connected to the control signal line, a first electrode of the thirteenth transistor is connected to the seventh node, and a second electrode of the thirteenth transistor is connected to the third node.

In some embodiments, the current control circuit further comprises a third capacitance;

a first end of the third capacitor is connected to the second gate line, and a second end of the third capacitor is connected to the fifth node.

In some embodiments, the current control circuit comprises: the second reset sub-circuit, the second threshold compensation sub-circuit and the second reset sub-circuit are connected to an eighth node, the second reset sub-circuit and the second data write sub-circuit are connected to a ninth node, and the second pole of the driving transistor, the second threshold compensation sub-circuit and the second output control sub-circuit are connected to a tenth node;

the second reset sub-circuit configured to write a second initialization voltage and a preset constant voltage to the eighth node and the ninth node, respectively, in response to control of a signal of the second reset signal line, and write the preset constant voltage to the ninth node in response to control of a signal of a control signal line;

the second data writing sub-circuit configured to write a second data voltage to the ninth node in response to control of a signal of the second gate line;

the second output control sub-circuit is connected with the third node and is configured to respond to the control of the signal of the control signal line and control the conduction between the third node and the tenth node;

the driving transistor is configured to respond to the control of the voltage at the eighth node and output corresponding driving current;

a first end of the fourth capacitor is connected with the first working voltage end, and a second end of the fourth capacitor is connected with the eighth node;

and a first end of the fifth capacitor is connected with the ninth node, and a second end of the fifth capacitor is connected with the eighth node.

In some embodiments, the second reset sub-circuit comprises: a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor, the second data write sub-circuit including: a seventeenth transistor, the second threshold compensation sub-circuit comprising: an eighteenth transistor, the second output control sub-circuit including: a nineteenth transistor;

a control electrode of the fourteenth transistor is connected to the second reset signal line, a first electrode of the fourteenth transistor is connected to a second initialization voltage terminal, and a second electrode of the fourteenth transistor is connected to the eighth node;

a control electrode of the fifteenth transistor is connected with the second reset signal line, a first electrode of the fifteenth transistor is connected with a constant voltage end, and a second electrode of the fifteenth transistor is connected with the ninth node;

a control electrode of the sixteenth transistor is connected with the control signal line, a first electrode of the sixteenth transistor is connected with a constant voltage end, and a second electrode of the sixteenth transistor is connected with the ninth node;

a control electrode of the seventeenth transistor is connected with the second gate line, a first electrode of the seventeenth transistor is connected with the second data line, and a second electrode of the seventeenth transistor is connected with the ninth node;

a control electrode of the eighteenth transistor is connected with the second gate line, a first electrode of the eighteenth transistor is connected with the eighth node, and a second electrode of the eighteenth transistor is connected with the tenth node;

a control electrode of the nineteenth transistor is connected to the control signal line, a first electrode of the nineteenth transistor is connected to the tenth node, and a second electrode of the nineteenth transistor is connected to the third node.

In some embodiments, all of the transistors in the pixel circuit are N-type transistors;

alternatively, all the transistors in the pixel circuit are P-type transistors.

In a second aspect, an embodiment of the present disclosure further provides a display device, including: the display substrate comprises a plurality of sub-pixels, a pixel circuit and an element to be driven are arranged in at least one sub-pixel, and the pixel circuit is configured to provide a driving signal for the element to be driven.

In some embodiments, the element to be driven comprises: LED or Micro-LED.

In a third aspect, an embodiment of the present disclosure further provides a driving method of a pixel circuit, where the driving method is used to drive the pixel circuit provided in the first aspect, and the driving method includes:

loading a first reset signal to the first reset signal line, a reference voltage to a reference voltage terminal, and a first initialization voltage to a first initialization voltage terminal, so that the first reset sub-circuit controls writing of the reference voltage and the first initialization voltage to the first node and the second node, respectively, in response to the reset signal;

loading a first gate scan signal to the first gate line, loading a first data voltage to a first data line, so that the first data writing sub-circuit controls writing of the first data voltage to the first node in response to the first gate scan signal, and the first threshold compensation sub-circuit controls threshold compensation of a transistor in the switching sub-circuit in response to the first gate scan signal;

loading a control signal to the control signal line, loading a ramp signal to a ramp signal line, so that the ramp writing sub-circuit controls to write the ramp signal to the first node in response to the control signal, and the switching sub-circuit adjusts the voltage at the second node according to a voltage difference between the voltage of the ramp signal loaded at the first node and the first data voltage, and controls on/off between the third node and the fourth node in response to the voltage control at the second node.

In some embodiments, the current control circuit comprises: the second reset sub-circuit, the second data write sub-circuit, the second threshold compensation sub-circuit, the second output control sub-circuit, the driving transistor and the second capacitor;

before the step of applying a control signal to the control signal line and a ramp signal to the ramp signal line, the method further includes:

loading a second reset signal to the second reset signal line, loading a second initialization voltage to a second initialization voltage terminal, so that the second reset sub-circuit loads the second initialization voltage to a fifth node in response to control of the second reset signal;

loading a second gate scan signal to the second gate line, loading a second data voltage to a second data line, so that the second data writing sub-circuit controls writing of the second data voltage to a sixth node in response to the second gate scan signal, and the second threshold compensation sub-circuit controls threshold compensation of the driving transistor in response to the second gate scan signal;

when a control signal is loaded to the control signal wire, the second output control sub-circuit responds to the control signal to control writing of a first working voltage to the sixth node and control conduction between the third node and the seventh node, and the driving transistor responds to control of a voltage at the fifth node to output a corresponding driving current.

In some embodiments, the current control circuit comprises: the second reset sub-circuit, the second data write sub-circuit, the second threshold compensation sub-circuit, the second output control sub-circuit, the driving transistor, the fourth capacitor and the fifth capacitor;

loading a second reset signal to the second reset signal line, a second initialization voltage to a second initialization voltage terminal, and a constant voltage to a constant voltage terminal, so that the second reset sub-circuit loads the second initialization voltage and the constant voltage to the eighth node and the ninth node, respectively, in response to control of the second reset signal;

loading a second gate scan signal to the second gate line, loading a second data voltage to a second data line, so that the second data writing sub-circuit controls writing of the second data voltage to a ninth node in response to the second gate scan signal, and the second threshold compensation sub-circuit controls threshold compensation of the driving transistor in response to the second gate scan signal;

when a control signal is loaded to the control signal line, the second reset sub-circuit controls to write the constant voltage to the ninth node in response to the control signal, the second output control sub-circuit controls to conduct between the third node and the tenth node in response to the control signal, and the driving transistor outputs a corresponding driving current in response to the control of the voltage at the eighth node.

Drawings

Fig. 1 is a schematic circuit structure diagram of a pixel circuit according to an embodiment of the disclosure;

FIG. 2 is a schematic diagram of device characteristics of an element to be driven in an embodiment of the present disclosure;

fig. 3 is a schematic circuit structure diagram of another pixel circuit provided in the embodiment of the present disclosure;

FIG. 4 is a timing diagram illustrating operation of the pixel circuit shown in FIG. 3;

fig. 5 is a schematic circuit structure diagram of another pixel circuit provided in the embodiment of the present disclosure;

FIG. 6 is a timing diagram illustrating operation of the pixel circuit shown in FIG. 5;

fig. 7 is a schematic circuit structure diagram of another pixel circuit according to an embodiment of the disclosure;

fig. 8 is a schematic circuit diagram of a pixel circuit according to another embodiment of the disclosure;

fig. 9 is a flowchart of a driving method of a pixel circuit according to an embodiment of the disclosure;

fig. 10 is a flowchart of another driving method of a pixel circuit according to an embodiment of the disclosure;

fig. 11 is a flowchart of a driving method of a pixel circuit according to another embodiment of the disclosure;

fig. 12 is a schematic circuit structure diagram of a display device according to an embodiment of the disclosure.

Detailed Description

In order to make those skilled in the art better understand the technical solution of the present invention, a pixel circuit, a driving method thereof, and a display device provided by the present invention are described in detail below with reference to the accompanying drawings.

In the embodiments of the present disclosure, the element to be driven may be a Light Emitting element, and the Light Emitting element may be a Light Emitting device driven by current/voltage, including a Light Emitting Diode (LED) or a Micro-LED, and in the following embodiments, the element to be driven is described as a Micro-LED, and the size of the Micro-LED is in the micrometer (μm) level.

In addition, the transistors involved in the embodiments of the present disclosure may be independently selected from one of a polycrystalline silicon thin film transistor, an amorphous silicon thin film transistor, an oxide thin film transistor, and an organic thin film transistor. Reference in this disclosure to a "control electrode" is specifically to a gate of a transistor, a "first electrode" is specifically to a source of the transistor, and a corresponding "second electrode" is specifically to a drain of the transistor. Of course, those skilled in the art will appreciate that the "first pole" and "second pole" are interchangeable.

In addition, the transistors may be divided into N-type transistors and P-type transistors, and each transistor in the present disclosure may be independently selected from the N-type transistor or the P-type transistor; in the following embodiments, all transistors in a pixel unit are P-type transistors, and the transistors in the pixel circuit can be simultaneously manufactured by the same manufacturing process. Accordingly, the first operating voltage is a high level operating voltage Vdd, and the second operating voltage is a low level operating voltage Vss.

Fig. 1 is a schematic circuit structure diagram of a pixel circuit according to an embodiment of the present disclosure, and as shown in fig. 1, the pixel circuit includes: a current control circuit 1 and a time control circuit 2, the current control circuit 1 is configured to generate a drive current and output the drive current to the time control circuit 2. The time control circuit 2 includes: the first reset sub-circuit 3, the first data write sub-circuit 4, the first threshold compensation sub-circuit 5, the ramp wave write sub-circuit 6 and the switch sub-circuit 7 are connected to a first node N1, the first reset sub-circuit 3, the first data write sub-circuit 4, the ramp wave write sub-circuit 6 and the switch sub-circuit 7 are connected to a second node N2, the first threshold compensation sub-circuit 5, the switch sub-circuit 7 and the current control circuit 1 are connected to a third node N3, anodes of the first threshold compensation sub-circuit 5, the switch sub-circuit 7 and the element to be driven Micro-LED are connected to a fourth node N4, and a cathode of the element to be driven Micro-LED is connected to a second working voltage terminal.

Wherein the first Reset sub-circuit 3 is configured to write the reference voltage and the first initialization voltage to the first node N1 and the second node N2, respectively, in response to the control of the signal of the first Reset signal line Reset _ T.

The first data writing sub-circuit 4 is configured to write the first data voltage to the first node N1 in response to control of a signal of the first Gate line Gate _ T.

The first threshold compensation sub-circuit 5 is configured to write a reference voltage to the third node N3 in response to control of a signal of the first Gate line Gate _ T and perform threshold compensation on a transistor within the switching sub-circuit 7.

The ramp writing sub-circuit 6 is configured to write a preset ramp signal to the first node N1 in response to control of a signal of the control signal line EM.

The switch sub-circuit 7 is configured to adjust the voltage at the second node N2 according to the voltage difference between the voltage of the ramp signal loaded at the first node N1 and the first data voltage, and to control the on/off between the third node N3 and the fourth node N4 in response to the control of the voltage at the second node N2.

In some embodiments, when the transistors in the switch sub-circuit 7 are P-type transistors, the ramp signal is a voltage signal whose voltage magnitude increases at a fixed rate of change over time. When the transistor in the switch sub-circuit 7 is an N-type transistor, the ramp signal is a voltage signal whose voltage level decreases at a fixed rate of change with time.

In the disclosed embodiment, the switch sub-circuit 7 is switchable between a "closed" state and an "open" state in response to control of the voltage at the second node N2. Specifically, when the switch sub-circuit 7 is in the "closed" state, the third node N3 and the fourth node N4 are turned on, and the current control circuit 1 can output a driving current to the element to be driven Micro-LED; when the switch sub-circuit 7 is in the off state, the third node N3 and the fourth node N4 are disconnected, and the current control circuit 1 does not output the driving current due to the disconnection. Under the condition that the initial voltage and the voltage change rate of the ramp signal are constant, the duration from the beginning of entering the display phase to the critical voltage capable of switching the switch sub-circuit 7 from the "off" state to the "on" state can be controlled by adjusting the magnitude of the first data voltage, that is, the duration that the switch sub-circuit 7 is in the "off" state in the display phase is controlled. The duration of the switch sub-circuit 7 in the "on" state can be controlled by controlling the duration of the switch sub-circuit 7 in the "off" state for a certain total duration of the display phase during one period (e.g. one frame). Therefore, the working time of the element to be driven Micro-LED (the time of the switch sub-circuit 7 in the closed state) in one period can be controlled through the magnitude of the first data voltage.

Since the magnitude of the current flowing through the element to be driven Micro-LED and the working time of the element to be driven Micro-LED in a period (for example, one frame) affect the effective brightness of the element to be driven Micro-LED in the period, the effective brightness of the element to be driven Micro-LED in the period can be controlled by the driving current provided by the current control circuit 1 and the first Data voltage provided by the first Data line Data _ T, and the purpose of adjusting the display gray scale is achieved.

Fig. 2 is a schematic diagram of device characteristics of the element to be driven Micro-LED in the embodiment of the disclosure, and as shown in fig. 2, the light emitting efficiency of the element to be driven Micro-LED gradually increases with the increase of the current density and stabilizes at the maximum value when the current density is between J1 and J2. Thus, in view of saving display power consumption, the element to be driven Micro-LED is generally required to operate in a state where the current density is between J1 and J2. However, the range of current density between J1 and J2 is very limited for many types of Micro-LEDs, and if different gray levels are obtained by adjusting the current level only, the resulting display contrast may be very low. For this reason, in the embodiment of the present disclosure, the current control circuit 1 can set the current density of the element to be driven Micro-LED in operation within a stable range (between J1 and J2), and the time control circuit 2 adjusts the duration of the switch sub-circuit 7 in the "closed" state in each period to control the display gray scale, so as to achieve high contrast of the display device.

According to the technical scheme, the high contrast is realized on the premise that the current density of the element to be driven Micro-LED is in the stable range, the problems of color cast, efficiency reduction and the like caused by the fact that the current density of the element to be driven Micro-LED is out of the stable range can be avoided, and the high contrast required by a display product can be realized.

Fig. 3 is a schematic circuit structure diagram of another pixel circuit provided in an embodiment of the present disclosure, and as shown in fig. 3, the pixel circuit is an embodiment based on the pixel circuit shown in fig. 1. The reference voltage terminal provides a reference voltage Vref, the first initialization voltage terminal provides a first initialization voltage Vinit _ T, and the first Data line Data _ T provides a first Data voltage Vdata _ T of the pixel circuit.

In some embodiments, the first reset sub-circuit 3 comprises: a first transistor M1 and a second transistor M2; a control electrode of the first transistor M1 is connected to the first Reset signal line Reset _ T, a first electrode of the first transistor M1 is connected to the reference voltage terminal, and a second electrode of the first transistor M1 is connected to the first node N1; a control electrode of the second transistor M2 is connected to the first Reset signal line Reset _ T, a first electrode of the second transistor M2 is connected to the first initialization voltage terminal, and a second electrode of the second transistor M2 is connected to the second node N2.

In some embodiments, the first data writing sub-circuit 4 includes: a third transistor M3; a control electrode of the third transistor M3 is connected to the first Gate line Gate _ T, a first electrode of the third transistor M3 is connected to the first Data line Data _ T, and a second electrode of the third transistor M3 is connected to the first node N1.

In some embodiments, the first threshold compensation sub-circuit 5 comprises: a fourth transistor M4 and a fifth transistor M5; a control electrode of the fourth transistor M4 is connected to the first Gate line Gate _ T, a first electrode of the fourth transistor M4 is connected to the reference voltage terminal, and a second electrode of the fourth transistor M4 is connected to the third node N3; a control electrode of the fifth transistor M5 is connected to the first Gate line Gate _ T, a first electrode of the fifth transistor M5 is connected to the second node N2, and a second electrode of the fifth transistor M5 is connected to the fourth node N4.

In some embodiments, the ramp writing sub-circuit 6 includes: a sixth transistor M6; a control electrode of the sixth transistor M6 is connected to the control signal line EM, a first electrode of the sixth transistor M6 is connected to the Ramp signal line Ramp, and a second electrode of the sixth transistor M6 is connected to the first node N1.

In some embodiments, the switch sub-circuit 7 comprises: a seventh transistor M7 and a first capacitor C1; a control electrode of the seventh transistor M7 is connected to the second node N2, a first electrode of the seventh transistor M7 is connected to the third node N3, and a second electrode of the seventh transistor M7 is connected to the fourth node N4; a first terminal of the first capacitor C1 is connected to the first node N1, and a second terminal of the first capacitor C1 is connected to the second node N2.

In some embodiments, the pixel circuit further comprises: the first output control sub-circuit 8 is connected with the fourth node N4 through the first output control sub-circuit 8; the first output control sub-circuit 8 is configured to control the on/off between the fourth node N4 and the element to be driven Micro-LED in response to the control of the signal of the control signal line EM. Further, the first output control sub-circuit 8 includes: an eighth transistor M8; a control electrode of the eighth transistor M8 is connected to the control signal line EM, a first electrode of the eighth transistor M8 is connected to the fourth node N4, and a second electrode of the eighth transistor M8 is connected to the element to be driven Micro-LED.

It should be noted that, in the present embodiment, the first output control sub-circuit 8 is used to prevent a current (for example, when the first threshold compensation sub-circuit 5 performs the threshold compensation process on the seventh transistor M7 in the switch sub-circuit 7, a current is output in the seventh transistor M7 within a short time) from flowing to the element to be driven Micro-LED during the non-display period, so that the element to be driven Micro-LED emits light by mistake, and the display effect is affected. It will be appreciated by those skilled in the art that the provision of the first output control sub-circuit 8 is only an alternative embodiment of the present disclosure, and is not a necessary structure in the pixel circuit.

In order to reduce the number of signal lines in the display panel, the signal line (i.e., the first Data line Data _ T) for supplying the first Data voltage to the first Data writing sub-circuit 4 and the signal line (Ramp signal line Ramp) for supplying the Ramp signal to the Ramp writing sub-circuit 6 are the same signal line in the embodiment of the present disclosure. The signal line can provide a first data voltage for each corresponding pixel circuit in the first writing and compensation stage, and provide a ramp signal for each pixel circuit in the display stage.

The operation of the pixel circuit shown in fig. 3 will be described in detail with reference to the accompanying drawings. Fig. 4 is a timing diagram illustrating an operation of the pixel circuit shown in fig. 3, and as shown in fig. 4, the operation of the pixel circuit includes the following stages:

in the first Reset period T1, the first Reset signal provided by the first Reset signal line Reset _ T is in a low state, the first Gate scan signal provided by the first Gate line Gate _ T is in a high state, and the control signal provided by the control signal line EM is in a high state. At this time, the first transistor M1 and the second transistor M2 are in an on state, and the third transistor M3 to the eighth transistor M8 are in an off state. The reference voltage Vref provided by the reference voltage terminal is written to the first node N1 through the first transistor M1M1, and the first initialization voltage Vinit _ T provided by the first initialization voltage terminal is written to the second node N2 through the second transistor M2. Since the seventh transistor M7M7 is in an off state, a circuit is broken between the third node N3 and the fourth node N4.

In the first write and compensation period T2, the first Reset signal provided by the first Reset signal line Reset _ T is at a high level state, the first Gate scan signal provided by the first Gate line Gate _ T is at a low level state, and the control signal provided by the control signal line EM is at a high level state. At this time, the third to fifth transistors M3 to M5 are in an on state, and the first, second, sixth, and eighth transistors M1, M2, M6, and M8 are in an off state. The seventh transistor M7 is turned on and then turned off.

Here, since the third transistor M3 is turned on, the first data voltage Vdata _ T may be written to the first node N1 through the third transistor M3. Since the fourth transistor M4 is turned on, the reference voltage Vref is written to the third node N3 through the fourth transistor M4; since the fifth transistor M5 is turned on, the seventh transistor M7 forms a diode structure, and the third node N3 charges the second node N2 through the seventh transistor M7, the fourth node N4 and the fifth transistor M5, and when the voltage at the second node N2 is charged to Vref + Vth \\ u_M7The seventh transistor M7 is turned off to complete the threshold compensation of the seventh transistor M7. Wherein Vth \ u_M7Is the threshold voltage of the seventh transistor M7 (the seventh transistor M7 is a P-type transistor, Vth \ u_M7A negative value). At the end of the first writing and compensation phase T2, the voltage at the first node N1 is Vdata _ T, and the voltage at the second node N2 is Vref + Vth __M7The voltage difference between the two ends of the first capacitor C1 is Vdata _ T-Vref-Vth __M7。

In the display period T3, the first Reset signal provided by the first Reset signal line Reset _ T is in a high level state, the first Gate scan signal provided by the first Gate line Gate _ T is in a high level state, and the control signal provided by the control signal line EM is in a low level state. The sixth transistor M6 and the eighth transistor M8 are in an on state, and the first to fifth transistors M1 to M5 are in an off state. The seventh transistor M7 is turned off and then turned on.

The voltage of the ramp signal is V in the display period t3₀+k*t，V ₀The initial voltage corresponding to the ramp signal at the beginning of the display period t3 in one period is k, which is the voltage change rate (if the seventh transistor M7 is a P-type transistor, k takes a negative value, and if the seventh transistor M7 is an N-type transistor, k takes a positive value).

At the start time of the display period T3, the voltage at the first node N1 is changed from Vdata _ T to V₀Under the bootstrap action of the first capacitor C1, the voltage at the second node N2 is controlled by Vref + Vth \ u_M7Becomes Vref + Vth \ u_M7+V ₀-Vdata _ T. After that, the voltage at the first node N1 changes with the voltage change of the loaded ramp signal, and after the display period t3 goes for a time t, the voltage at the first node N1 is V₀+ k × t, and the voltage at the second node N2 is Vref + Vth \ u_M7+V ₀+ k × T-Vdata _ T at Vref and Vth __M7Under certain conditions, the voltage at the second node N2 is only equal to the voltage V at the first node N1₀+ k × T is related to the voltage difference of the first data voltage Vdata _ T, i.e. the voltage at the second node N2 is according to the voltage V at the first node N1₀The voltage difference between + k × T and the first data voltage Vdata _ T.

When the voltage at the second node N2 Vref + Vth \_M7+V ₀+ k × T-Vdata _ T down to Vth __M7At this time, the seventh transistor M7 is switched from the off state to the on state, i.e., Vref + Vth \ u_M7+V ₀+k*t-Vdata_T＝Vth_ _M7Can find out

It can be seen that at V₀When k and Vref are constant, the time when the seventh transistor M7 is turned off (the time when the switch sub-circuit 7 is turned off) in the display period t3 is equal to the first data voltage Vdata \uT is related. Accordingly, the times at which the switching sub-circuit 7 is in the "open" state and the "closed" state within the display period T3 can be controlled by the first data voltage Vdata _ T.

In addition, the duration t of the switch sub-circuit 7 in the "off" state in the display phase t3 and the threshold voltage Vth \ of the seventh transistor M7_M7Irrelevant, the problem that the time of 'disconnection'/'closing' is not accurately controlled due to threshold voltage deviation can be effectively solved, and the accuracy of gray scale control is improved.

After the seventh transistor M7 is switched to the on state, the driving current provided by the current control circuit 1 may flow into the element to be driven Micro-LED, and the element to be driven Micro-LED operates.

It should be noted that there is an interval time between the first writing and compensating phase t2 and the display phase t3, and the interval time is used for the pixel circuits of other rows in the display panel to perform the first data voltage writing and the threshold value compensation.

Fig. 5 is a schematic circuit structure diagram of another pixel circuit provided in an embodiment of the present disclosure, and as shown in fig. 5, the pixel circuit is an embodiment based on the pixel circuits shown in fig. 1 and 3, wherein the second initialization voltage terminal provides the second initialization voltage Vinit _ I.

In some embodiments, the current control circuit 1 includes: the second reset sub-circuit 9, the second data write sub-circuit 10, the second threshold compensation sub-circuit 11, the second output control sub-circuit 12, the driving transistor DTFT, and the second capacitor C2, wherein the second reset sub-circuit 9, the control electrode of the driving transistor DTFT, and the second threshold compensation sub-circuit 11 are connected to a fifth node N5, the first electrode of the driving transistor DTFT, the second data write sub-circuit 10, and the second output control sub-circuit 12 are connected to a sixth node N6, and the second electrode of the driving transistor DTFT, the second threshold compensation sub-circuit 11, and the second output control sub-circuit 12 are connected to a seventh node N7.

The second Reset sub-circuit 9 is configured to write the second initialization voltage to the fifth node N5 in response to control of a signal of the second Reset signal line Reset _ I.

The second data writing sub-circuit 10 is configured to write the second data voltage to the sixth node N6 in response to the control of the signal of the second Gate line Gate _ I.

The second threshold compensation sub-circuit 11 is configured to perform threshold compensation on the driving transistor DTFT in response to control of a signal of the second Gate line Gate _ I.

The second output control sub-circuit 12 is connected to the third node N3, and is configured to write the first operating voltage to the sixth node N6 and control conduction between the third node N3 and the seventh node N7 in response to control of a signal of the control signal line EM.

The driving transistor DTFT is configured to output a corresponding driving current in response to the control of the voltage at the fifth node N5; a first terminal of the second capacitor C2 is connected to the first operating voltage terminal, and a second terminal of the second capacitor C2 is connected to the fifth node N5.

In some embodiments, the second reset sub-circuit 9 comprises: the ninth transistor M9, the second data writing sub-circuit 10 includes: the tenth transistor M10, the second threshold compensation sub-circuit 11, includes: the eleventh transistor M11, the second output control sub-circuit 12 includes: a twelfth transistor M12 and a thirteenth transistor M13.

A control electrode of the ninth transistor M9 is connected to the second Reset signal line Reset _ I, a first electrode of the ninth transistor M9 is connected to the second initialization voltage terminal, and a second electrode of the ninth transistor M9 is connected to the fifth node N5.

A control electrode of the tenth transistor M10 is connected to the second Gate line Gate _ I, a first electrode of the tenth transistor M10 is connected to the second Data line Data _ I, and a second electrode of the tenth transistor M10 is connected to the sixth node N6.

A control electrode of the eleventh transistor M11 is connected to the second Gate line Gate _ I, a first electrode of the eleventh transistor M11 is connected to the fifth node N5, and a second electrode of the eleventh transistor M11 is connected to the seventh node N7.

A control electrode of the twelfth transistor M12 is connected to the control signal line EM, a first electrode of the twelfth transistor M12 is connected to the first operating voltage terminal, and a second electrode of the twelfth transistor M12 is connected to the sixth node N6.

A control electrode of the thirteenth transistor M13 is connected to the control signal line EM, a first electrode of the thirteenth transistor M13 is connected to the seventh node N7, and a second electrode of the thirteenth transistor M13 is connected to the third node N3.

The operation of the pixel circuit shown in fig. 5 will be described in detail with reference to the accompanying drawings. Fig. 6 is an operation timing diagram of the pixel circuit shown in fig. 5, and as shown in fig. 6, the operation process of the pixel circuit includes the following stages:

in the second Reset period T1', the first Reset signal provided by the first Reset signal line Reset _ T is in a high state, the first Gate scan signal provided by the first Gate line Gate _ T is in a high state, the second Reset signal provided by the second Reset signal line Reset _ I is in a low state, the second Gate scan signal provided by the second Gate line Gate _ I is in a high state, and the control signal provided by the control signal line EM is in a high state. At this time, the ninth transistor M9 is in an on state, and the first to eighth transistors M1 to M8 and the tenth to thirteenth transistors M10 to M13 are in an off state. Since the ninth transistor M9 is turned on, the second initialization voltage Vinit _ I is written to the fifth node N5 through the ninth transistor M9.

In the second write and compensation period T2', the first Reset signal provided by the first Reset signal line Reset _ T is in a high state, the first Gate scan signal provided by the first Gate line Gate _ T is in a high state, the second Reset signal provided by the second Reset signal line Reset _ I is in a high state, the second Gate scan signal provided by the second Gate line Gate _ I is in a low state, and the control signal provided by the control signal line EM is in a high state. At this time, the tenth transistor M10 and the eleventh transistor M11 are in an on state, and the first to ninth transistors M1 to M9, the twelfth transistor M12, and the thirteenth transistor M13 are in an off state. Since the tenth transistor M10 is turned on, the second data voltage Vdata _ I is written to the sixth node N6 through the tenth transistor M10.

Since the eleventh transistor M11 is turned on and the driving transistor DTFT forms a diode structure at this time, the sixth node N6 may pass through the driving transistor DTFT, the seventh node N7, and the eleventh transistor M11 to charge the fifth node N5 when the voltage at the fifth node N5 is charged to Vdata _ I + Vth __DTFTThe time-varying driving transistor DTFT is turned off, and the threshold compensation of the driving transistor DTFT is completed. Wherein Vth \ u_DTFTIs the threshold voltage of the driving transistor DTFT (the driving transistor DTFT is a P-type transistor, Vth \ u @_DTFTA negative value).

In the first Reset period T1, the first Reset signal provided by the first Reset signal line Reset _ T is in a low level state, the first Gate scan signal provided by the first Gate line Gate _ T is in a high level state, the second Reset signal provided by the second Reset signal line Reset _ I is in a high level state, the second Gate scan signal provided by the second Gate line Gate _ I is in a high level state, and the control signal provided by the control signal line EM is in a high level state. At this time, the first transistor M1 and the second transistor M2 are in an on state, and the third transistor M3 to the thirteenth transistor M13 are in an off state.

In the first write and compensation period T2, the first Reset signal provided by the first Reset signal line Reset _ T is at a high level state, the first Gate scan signal provided by the first Gate line Gate _ T is at a low level state, the second Reset signal provided by the second Reset signal line Reset _ I is at a high level state, the second Gate scan signal provided by the second Gate line Gate _ I is at a low level state, and the control signal provided by the control signal line EM is at a high level state. At this time, the third to fifth transistors M3 to M5 are turned on, and the first to thirteenth transistors M1, M2, M6, M8, and M9 to M13 are turned off. The seventh transistor M7 is turned on and then turned off.

In the first reset phase t1 and the first write and compensation phase t2, each transistor in the current control circuit 1 is turned off. For the description of the operation of each transistor in the time control circuit 2, reference may be made to the corresponding content in the foregoing embodiments, and details are not repeated here.

In the display period T3, the first Reset signal provided by the first Reset signal line Reset _ T is in a high level state, the first Gate scan signal provided by the first Gate line Gate _ T is in a high level state, the second Reset signal provided by the second Reset signal line Reset _ I is in a high level state, the second Gate scan signal provided by the second Gate line Gate _ I is in a high level state, and the control signal provided by the control signal line EM is in a low level state. At this time, the sixth transistor M6, the eighth transistor M8, the twelfth transistor M12, and the thirteenth transistor M13 are in an on state, the first to fifth transistors M1 to M5 are on, and the ninth to eleventh transistors M9 to M11 are in an off state. The seventh transistor M7 is turned off and then turned on.

The driving transistor DTFT operates in saturation, which is obtained according to the saturation current formula:

I_ _DTFT＝K_ _DTFT*(Vgs_ _DTFT-Vth_ _DTFT) ²

＝K_ _DTFT*(Vdata_I+Vth_ _DTFT-Vdd-Vth_ _DTFT) ²

＝K_ _DTFT*(Vdata_I-Vdd) ²

wherein, I \ u_DTFTVgs for the current output by the driving transistor DTFT in saturation_DTFTFor driving the gate-source voltage of the transistor DTFT, K \_DTFTIs a constant and is determined by the electrical characteristics of the driving transistor DTFT. It can be seen that, under a certain first operating voltage Vdd, the driving current outputted by the driving transistor DTFT is related to the second data voltage Vdata _ I only, and related to the threshold voltage Vth \/u \/of the driving transistor DTFT_DTFTIrrelevant, therefore, the influence of uneven threshold voltage and drift on the driving current output by the driving transistor DTFT can be avoided, and the uniformity of the driving current output by the driving transistor DTFT is effectively improved.

For the description of the operation of each transistor in the time control circuit 2, reference may be made to the corresponding content in the foregoing embodiments, and details are not repeated here.

In the disclosed embodiment, the driving current I _ u may be respectively driven by the first data voltage Vdata _ T and the second data voltage Vdata _ I_DTFTAnd an element to be drivenAnd the working time of the Micro-LED is controlled, so that the control of the display gray scale is realized.

It should be noted that, in some embodiments, the first reset phase t1 and the second reset phase t1 'may be performed simultaneously, and the first write and compensation phase t2 and the second write and compensation phase t2' may be performed simultaneously, which does not show a corresponding timing diagram.

Fig. 7 is a schematic circuit structure diagram of another pixel circuit provided in the embodiment of the present disclosure, and as shown in fig. 7, the difference between the current control circuit 1 in the pixel circuit shown in fig. 7 and the pixel circuit shown in fig. 5 is that the current control circuit further includes a third capacitor C3, a first end of the third capacitor C3 is connected to the second Gate line Gate _ I, and a second end of the third capacitor C3 is connected to a fifth node N5.

In practical applications, it is found that, during the second writing and compensation phase t2', the charging speed of the fifth node N5 depends on the on state of the driving transistor DTFT, which is controlled by the voltage difference between the gate and the source thereof, in this case, the voltage difference between the gate and the source is V _ N5-Vdata _ I, where V _ N5 is the voltage value at the fifth node N5. As the threshold compensation proceeds, the voltage of the fifth node N5 slowly approaches Vdata _ I + Vth \ u_DTFTAnd the closer to Vdata _ I + Vth __DTFTThe slower the charging speed of the fifth node N5, the less the charging time (e.g., charging time 1H for one row of pixels) for the limited time (e.g., charging time for one row of pixels) the fifth node N5 voltage can be charged to Vdata _ I + Vth __DTFT. Suppose at the end of the second write and compensation phase t2', the voltages V _ N5 and Vdata _ I + Vth _, at the fifth node N5_DTFTThe difference between the values is Δ V, i.e., the fifth node N5 is charged to Vdata _ I + Vth \ u_DTFT- Δ V. The difference voltage Δ V causes a difference in luminance for different gray levels.

To compensate for the difference voltage Δ V, a third capacitor C3 is provided in the present embodiment. At the end of the second writing and compensating period t2', the second Gate scan signal loaded on the second Gate line Gate _ I is switched from a low level state to a high level state, and the voltage at the fifth node N5 is pulled high by the third capacitor C3, so that the compensation for the difference voltage Δ V can be realized. Specifically, assuming that the corresponding transition voltage is Δ Vg when the second gate scan signal is switched from the low state to the high state, the voltage at the fifth node N5 will be pulled up by (C3 × Δ Vg)/(C2+ C3) under the bootstrap action of the third capacitor C3. When the circuit is designed, the capacitances of the second capacitor C2 and the third capacitor C3 are set in this ratio by setting (C3 × Δ Vg)/(C2+ C3) to Δ V, which results in C3/(C2+ C3) to Δ V/Δ Vg.

Typically, Δ Vg is tens of volts, e.g., 14V; Δ V is only a few tenths of a volt, for example 0.2V, and the value of C3/(C2+ C3) shown by way of example is 0.2/14 ≈ 1.4%, because the capacitance of the third capacitor C3 is small, the addition of the third capacitor C3 does not affect the high pixel density while enhancing the display effect (Pixels Per inc, abbreviated as PPI).

Fig. 8 is a schematic circuit structure diagram of another pixel circuit provided in the embodiment of the present disclosure, and as shown in fig. 8, the circuit structure of the current control circuit 1 in the pixel circuit provided in this embodiment is different from that in the previous embodiment. Wherein, the constant voltage provided by the constant voltage terminal is assumed as the grounding voltage V_GND。

In some embodiments, the current control circuit 1 includes: a second reset sub-circuit 9, a second data write sub-circuit 10, a second threshold compensation sub-circuit 11, a second output control sub-circuit 12, a driving transistor DTFT, a fourth capacitor C4, and a fifth capacitor C5, wherein a control electrode of the driving transistor DTFT, the second threshold compensation sub-circuit 11, and the second reset sub-circuit 9 are connected to an eighth node N8, the second reset sub-circuit 9 and the second data write sub-circuit 10 are connected to a ninth node N9, and the second electrode of the driving transistor DTFT, the second threshold compensation sub-circuit 11, and the second output control sub-circuit 12 are connected to a tenth node N10.

The second Reset sub-circuit 9 is configured to write the second initialization voltage and the preset constant voltage to the eighth node N8 and the ninth node N9, respectively, in response to control of a signal of the second Reset signal line Reset _ I, and to write the preset constant voltage to the ninth node N9 in response to control of a signal of the control signal line EM.

The second data writing sub-circuit 10 is configured to write the second data voltage to the ninth node N9 in response to the control of the signal of the second Gate line Gate _ I.

The second output control sub-circuit 12 is connected to the third node N3, and is configured to control conduction between the third node N3 and the tenth node N10 in response to control of a signal of the control signal line EM.

The driving transistor DTFT is configured to output a corresponding driving current in response to the control of the voltage at the eighth node N8. A first end of the fourth capacitor C4 is connected with the first working voltage end, and a second end of the fourth capacitor C4 is connected with the eighth node N8; a first terminal of the fifth capacitor C5 is connected to the ninth node N9, and a second terminal of the fifth capacitor C5 is connected to the eighth node N8.

In some embodiments, the second reset sub-circuit 9 comprises: a fourteenth transistor M14, a fifteenth transistor M15, and a sixteenth transistor M16, the second data writing sub-circuit 10 includes: the seventeenth transistor M17, the second threshold compensation sub-circuit 11, includes: the eighteenth transistor M18, the second output control sub-circuit 12 includes: a nineteenth transistor M19.

A control electrode of the fourteenth transistor M14 is connected to the second Reset signal line Reset _ I, a first electrode of the fourteenth transistor M14 is connected to the second initialization voltage terminal, and a second electrode of the fourteenth transistor M14 is connected to the eighth node N8.

A control electrode of the fifteenth transistor M15 is connected to the second Reset signal line Reset _ I, a first electrode of the fifteenth transistor M15 is connected to the constant voltage terminal, and a second electrode of the fifteenth transistor M15 is connected to the ninth node N9.

A control electrode of the sixteenth transistor M16 is connected to the control signal line EM, a first electrode of the sixteenth transistor M16 is connected to the constant voltage terminal, and a second electrode of the sixteenth transistor M16 is connected to the ninth node N9.

A control electrode of the seventeenth transistor M17 is connected to the second Gate line Gate _ I, a first electrode of the seventeenth transistor M17 is connected to the second Data line Data _ I, and a second electrode of the seventeenth transistor M17 is connected to the ninth node N9.

A control electrode of the eighteenth transistor M18 is connected to the second Gate line Gate _ I, a first electrode of the eighteenth transistor M18 is connected to the eighth node N8, and a second electrode of the eighteenth transistor M18 is connected to the tenth node N10.

A control electrode of the nineteenth transistor M19 is connected to the control signal line EM, a first electrode of the nineteenth transistor M19 is connected to the tenth node N10, and a second electrode of the nineteenth transistor M19 is connected to the third node N3.

The operation of the pixel circuit shown in fig. 8 will be described in detail with reference to fig. 6. Referring again to fig. 6, as shown in fig. 6, the operation of the pixel circuit includes the following stages:

in the second Reset period T1', the first Reset signal provided by the first Reset signal line Reset _ T is in a high state, the first Gate scan signal provided by the first Gate line Gate _ T is in a high state, the second Reset signal provided by the second Reset signal line Reset _ I is in a low state, the second Gate scan signal provided by the second Gate line Gate _ I is in a high state, and the control signal provided by the control signal line EM is in a high state. At this time, the fourteenth transistor M14 and the fifteenth transistor M15 are in an on state, and the first to eighth transistors M1 to M8 and the sixteenth to nineteenth transistors M16 to M19 are in an off state. Since the fourteenth transistor M14 and the fifteenth transistor M15 are turned on, the second initialization voltage Vinit _ I and the ground voltage V_GNDThe voltage difference between the two ends of the fifth capacitor C5 is Vinit _ I-V by writing into the eighth node N8 and the ninth node N9 through the fourteenth transistor M14 and the fifteenth transistor M15 respectively_GND。

In the second write and compensation period T2', the first Reset signal provided by the first Reset signal line Reset _ T is in a high state, the first Gate scan signal provided by the first Gate line Gate _ T is in a high state, the second Reset signal provided by the second Reset signal line Reset _ I is in a high state, the second Gate scan signal provided by the second Gate line Gate _ I is in a low state, and the control signal provided by the control signal line EM is in a high state. At this time, the seventeenth transistor M17 and the eighteenth transistor M18 are in an on state, and the first to eighth transistors M1 to M8, the fourteenth to sixteenth transistors M14 to M16, and the nineteenth transistor M19 are in an off state. Since the seventeenth transistor M17 is turned on, the second data voltage Vdata _ I is written to the ninth node N9 through the seventeenth transistor M17.

Since the eighteenth transistor M18 is turned on and the driving transistor DTFT forms a diode structure, the first operating voltage terminal can charge the eighth node N8 through the driving transistor DTFT, the tenth node N10 and the eighteenth transistor M18, and the voltage at the eighth node N8 is charged to Vdd + Vth \ u_DTFTThe time-varying driving transistor DTFT is turned off, and the threshold compensation of the driving transistor DTFT is completed. Wherein Vth \ u_DTFTIs the threshold voltage of the driving transistor DTFT.

At the end of the second writing and compensation phase t2', the voltage at the eighth node N8 is Vdd + Vth \ u_DTFTThe voltage at the ninth node N9 is Vdata _ I, and the voltage difference between the two ends of the fifth capacitor C5 is Vdd + Vth __DTFT-Vdata_I。

In the first Reset period T1, the first Reset signal provided by the first Reset signal line Reset _ T is in a low level state, the first Gate scan signal provided by the first Gate line Gate _ T is in a high level state, the second Reset signal provided by the second Reset signal line Reset _ I is in a high level state, the second Gate scan signal provided by the second Gate line Gate _ I is in a high level state, and the control signal provided by the control signal line EM is in a high level state. At this time, the first transistor M1 and the second transistor M2 are in an on state, and the third transistor M3 to the eighth transistor M8, and the fourteenth transistor M14 to the nineteenth transistor M19 are in an off state.

In the first write and compensation period T2, the first Reset signal provided by the first Reset signal line Reset _ T is at a high level state, the first Gate scan signal provided by the first Gate line Gate _ T is at a low level state, the second Reset signal provided by the second Reset signal line Reset _ I is at a high level state, the second Gate scan signal provided by the second Gate line Gate _ I is at a low level state, and the control signal provided by the control signal line EM is at a high level state. At this time, the third to fifth transistors M3 to M5 are turned on, and the first to fourteenth transistors M1, M2, M6, M8, M14 to M19 are turned off. The seventh transistor M7 is turned on and then turned off.

In the display period T3, the first Reset signal provided by the first Reset signal line Reset _ T is in a high level state, the first Gate scan signal provided by the first Gate line Gate _ T is in a high level state, the second Reset signal provided by the second Reset signal line Reset _ I is in a high level state, the second Gate scan signal provided by the second Gate line Gate _ I is in a high level state, and the control signal provided by the control signal line EM is in a low level state. At this time, the sixth transistor M6, the eighth transistor M8, the sixteenth transistor M16, and the nineteenth transistor M19 are in an on state, and the first to fifth transistors M1 to M5 are on, and the fourteenth transistor M14, the fifteenth transistor M15, the seventeenth transistor M17, and the eighteenth transistor M18 are in an off state. The seventh transistor M7 is turned off and then turned on.

Since the sixteenth transistor M16 is turned on, the ground voltage V_GNDThe voltage at the eighth node N8 is driven by Vdd + Vth under the bootstrap action of the fifth capacitor C5 by the sixteenth transistor M16 written to the ninth node N9_DTFTJump to Vdd + Vth \ u_DTFT+V _GND-Vdata_I。

I_ _DTFT＝K_ _DTFT*(Vgs_ _DTFT-Vth_ _DTFT) ²

＝K_ _DTFT*(Vdd+Vth_ _DTFT+V _GND-Vdata_I-Vdd-Vth_ _DTFT) ²

＝K_ _DTFT*(V _GND-Vdata_I) ²

wherein, I \ u_DTFTVgs for the current output by the driving transistor DTFT in saturation_DTFTFor driving the gate-source voltage of the transistor DTFT, K \_DTFTIs a constant and is determined by the electrical characteristics of the driving transistor DTFT. It can be seen that the ground voltage V is_GNDIn a certain case, the driving current outputted from the driving transistor DTFT is related to only the second data voltage Vdata _ I and is related to the threshold voltage Vth \/of the driving transistor DTFT_DTFTIrrelevant, therefore, the influence of uneven threshold voltage and drift on the driving current output by the driving transistor DTFT can be avoided, and the uniformity of the driving current output by the driving transistor DTFT is effectively improved.

In the disclosed embodiment, the driving current I _ u may be respectively driven by the first data voltage Vdata _ T and the second data voltage Vdata _ I_DTFTAnd the working time of the element to be driven is controlled, so that the control of the display gray scale is realized.

It should be noted that, when the working process of all the transistors in the pixel circuit provided in this embodiment are N-type transistors is the same as the working process of all the transistors are P-type transistors, details are not described here.

Those skilled in the art should understand that the current control circuit in the present embodiment may also adopt other circuit structures, which are not described herein by way of example.

Fig. 9 is a flowchart of a driving method of a pixel circuit according to an embodiment of the present disclosure, and as shown in fig. 9, the pixel circuit adopts the pixel circuit according to any one of the foregoing embodiments, the driving method includes:

step S101, a first reset signal is applied to the first reset signal line, a reference voltage is applied to the reference voltage terminal, and a first initialization voltage is applied to the first initialization voltage terminal, so that the first reset sub-circuit controls to write the reference voltage and the first initialization voltage to the first node and the second node, respectively, in response to the reset signal.

Step S102, a first gate scanning signal is applied to the first gate line, and a first data voltage is applied to the first data line, so that the first data writing sub-circuit controls to write the first data voltage to the first node in response to the first gate scanning signal, and the first threshold compensation sub-circuit controls to perform threshold compensation on the transistor in the switch sub-circuit in response to the first gate scanning signal.

Step S103, loading a control signal to the control signal line, loading a ramp signal to the ramp signal line, so that the ramp writing sub-circuit writes the ramp signal to the first node in response to the control signal control, and the switching sub-circuit adjusts the voltage at the second node according to the voltage difference between the voltage of the ramp signal loaded at the first node and the first data voltage, and controls the on-off between the third node and the fourth node in response to the voltage control at the second node.

For the specific description of the above step S101 to step S103, reference may be made to corresponding contents in the description embodiment, and details are not described here.

Fig. 10 is a flowchart of another driving method of a pixel circuit according to an embodiment of the disclosure, and as shown in fig. 10, a current control circuit in the pixel circuit includes: the second reset sub-circuit, the second data write sub-circuit, the second threshold compensation sub-circuit, the second output control sub-circuit, the driving transistor and the second capacitor; for example, the current control circuit shown in fig. 5 and 7 is employed.

Step S201, loading a second reset signal to a second reset signal line, and loading a second initialization voltage to a second initialization voltage terminal, so that the second reset sub-circuit loads the second initialization voltage to a fifth node in response to the control of the second reset signal;

step S202, loading a second gate scanning signal to the second gate line, and loading a second data voltage to the second data line, so that the second data writing sub-circuit controls to write the second data voltage to the sixth node in response to the second gate scanning signal, and the second threshold compensation sub-circuit controls to perform threshold compensation on the driving transistor in response to the second gate scanning signal;

step S203, a first reset signal is applied to the first reset signal line, a reference voltage is applied to the reference voltage terminal, and a first initialization voltage is applied to the first initialization voltage terminal, so that the first reset sub-circuit controls to write the reference voltage and the first initialization voltage to the first node and the second node, respectively, in response to the reset signal.

Step S204, a first gate scanning signal is applied to the first gate line, and a first data voltage is applied to the first data line, so that the first data writing sub-circuit controls to write the first data voltage to the first node in response to the first gate scanning signal, and the first threshold compensation sub-circuit controls to perform threshold compensation on the transistor in the switch sub-circuit in response to the first gate scanning signal.

Step S205, a control signal is loaded to the control signal line, a ramp signal is loaded to the ramp signal line, so that the second output control sub-circuit responds to the control signal to control the writing of the first working voltage to the sixth node and the conduction between the third node and the seventh node, the driving transistor responds to the control of the voltage at the fifth node to output a corresponding driving current, the ramp writing sub-circuit responds to the control signal to control the writing of the ramp signal to the first node, and the switching sub-circuit adjusts the voltage at the second node according to the voltage difference between the voltage of the ramp signal loaded at the first node and the first data voltage and responds to the voltage control at the second node to control the on/off between the third node and the fourth node.

For the specific description of the above step S201 to step S205, reference may be made to corresponding contents in the description embodiment, and details are not described here.

In some embodiments, step S201 and step S203 may be performed synchronously, and step S202 and step S204 may be performed synchronously.

Fig. 11 is a flowchart of a driving method of a pixel circuit according to another embodiment of the disclosure, and as shown in fig. 11, a current control circuit in the pixel circuit includes: the second reset sub-circuit, the second data write sub-circuit, the second threshold compensation sub-circuit, the second output control sub-circuit, the driving transistor, the fourth capacitor and the fifth capacitor.

Step S301 loads the second reset signal to the second reset signal line, loads the second initialization voltage to the second initialization voltage terminal, and loads the constant voltage to the constant voltage terminal, so that the second reset sub-circuit loads the second initialization voltage and the constant voltage to the eighth node and the ninth node, respectively, in response to control of the second reset signal.

Step S302, a second gate scanning signal is applied to the second gate line, and a second data voltage is applied to the second data line, so that the second data writing sub-circuit controls to write the second data voltage to the ninth node in response to the second gate scanning signal, and the second threshold compensation sub-circuit controls to perform threshold compensation on the driving transistor in response to the second gate scanning signal.

Step S303 loads the first reset signal to the first reset signal line, loads the reference voltage to the reference voltage terminal, and loads the first initialization voltage to the first initialization voltage terminal, so that the first reset sub-circuit controls to write the reference voltage and the first initialization voltage to the first node and the second node, respectively, in response to the reset signal.

Step S304, a first gate scanning signal is applied to the first gate line, and a first data voltage is applied to the first data line, so that the first data writing sub-circuit controls to write the first data voltage to the first node in response to the first gate scanning signal, and the first threshold compensation sub-circuit controls to perform threshold compensation on the transistor in the switch sub-circuit in response to the first gate scanning signal.

Step S305, a control signal is loaded to the control signal line, a ramp signal is loaded to the ramp signal line, so that the second reset sub-circuit responds to the control signal control to write a constant voltage to the ninth node, the second output control sub-circuit responds to the control signal control to control conduction between the third node and the tenth node, the driving transistor responds to the control of the voltage at the eighth node to output a corresponding driving current, the ramp writing sub-circuit responds to the control signal control to write a ramp signal to the first node, the switch sub-circuit adjusts the voltage at the second node according to the voltage difference between the voltage loaded with the ramp signal at the first node and the first data voltage, and responds to the voltage control at the second node to control connection and disconnection between the third node and the fourth node.

For the specific description of the above steps S301 to S305, reference may be made to the corresponding contents in the description embodiment, and details are not repeated here.

In some embodiments, step S301 and step S303 may be performed synchronously, and step S302 and step S304 may be performed synchronously.

Fig. 12 is a schematic circuit structure diagram of a display device according to an embodiment of the disclosure, and as shown in fig. 12, the display device includes: the display substrate comprises a plurality of sub-pixels, wherein a pixel circuit PIX and an element to be driven Micro-LED are arranged in at least one sub-pixel, and the pixel circuit PIX is used for providing a driving signal for the element to be driven.

In some embodiments, the element to be driven comprises: LED or Micro-LED.

In some embodiments, the number of sub-pixels is greater than or equal to 2; it should be noted that 2 × 2 sub-pixels are exemplarily shown in fig. 12, and this case is merely for exemplary purposes and does not limit the technical solution of the present disclosure.

In some embodiments, in a pixel array formed by a plurality of sub-pixels, the sub-pixels in the same row correspond to the same first Gate line Gate _ T (1)/Gate _ T (2) and the same second Gate line Gate _ I (1)/Gate _ I (2), the sub-pixels in the same column correspond to the same first Data line Data _ T (1)/Data _ T (2) and the same second Data line Data _ I (1)/Data _ I (2), and all the sub-pixels correspond to the same control signal line EM. It should be noted that the above cases are only exemplary, and do not limit the technical solution of the present disclosure.

The display device provided by the embodiment of the disclosure can be any product or component with a display function, such as electronic paper, an LED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.

It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims

A pixel circuit, comprising: a current control circuit and a time control circuit, the current control circuit configured to generate a drive current and output the drive current to the time control circuit, wherein the time control circuit comprises: the first reset sub-circuit, the first data write sub-circuit, the ramp wave write sub-circuit and the switch sub-circuit are connected to a first node, the first reset sub-circuit, the first threshold compensation sub-circuit and the switch sub-circuit are connected to a second node, the first threshold compensation sub-circuit, the switch sub-circuit and the current control circuit are connected to a third node, and the first threshold compensation sub-circuit, the switch sub-circuit and the element to be driven are connected to a fourth node;

the first reset sub-circuit configured to write a reference voltage and a first initialization voltage to the first node and the second node, respectively, in response to control of a signal of a first reset signal line;

the first data writing sub-circuit configured to write a first data voltage to the first node in response to control of a signal of the first gate line;

the first threshold compensation sub-circuit is configured to respond to the control of the signal of the first grid line, write the reference voltage into the third node and perform threshold compensation on a transistor in the switch sub-circuit;

the ramp writing sub-circuit is configured to write a preset ramp signal to the first node in response to control of a signal of a control signal line;

the switch subcircuit is configured to adjust the voltage at the second node according to the voltage difference between the voltage loaded with the ramp signal at the first node and the first data voltage, and to control the on-off between the third node and the fourth node in response to the control of the voltage at the second node.
The pixel circuit of claim 1, wherein the first reset sub-circuit comprises: a first transistor and a second transistor;

a control electrode of the first transistor is connected with the first reset signal line, a first electrode of the first transistor is connected with a reference voltage end, and a second electrode of the first transistor is connected with the first node;

the control electrode of the second transistor is connected with the first reset signal line, the first electrode of the second transistor is connected with the first initialization voltage end, and the second electrode of the second transistor is connected with the second node.
The pixel circuit of claim 1, wherein the first data write sub-circuit comprises: a third transistor;

a control electrode of the third transistor is connected to the first gate line, a first electrode of the third transistor is connected to a first data line, and a second electrode of the third transistor is connected to the first node.
The pixel circuit of claim 1, wherein the first threshold compensation sub-circuit comprises: a fourth transistor and a fifth transistor;

a control electrode of the fourth transistor is connected with the first grid line, a first electrode of the fourth transistor is connected with a reference voltage end, and a second electrode of the fourth transistor is connected with the third node;

a control electrode of the fifth transistor is connected to the first gate line, a first electrode of the fifth transistor is connected to the second node, and a second electrode of the fifth transistor is connected to the fourth node.
The pixel circuit of claim 1, wherein the ramp write sub-circuit comprises: a sixth transistor;

and a control electrode of the sixth transistor is connected with a control signal line, a first electrode of the sixth transistor is connected with a ramp signal line, and a second electrode of the sixth transistor is connected with the first node.
The pixel circuit of claim 1, wherein the switch sub-circuit comprises: a seventh transistor and a first capacitor;

a control electrode of the seventh transistor is connected to the second node, a first electrode of the seventh transistor is connected to the third node, and a second electrode of the seventh transistor is connected to the fourth node;

the first end of the first capacitor is connected with the first node, and the second end of the first capacitor is connected with the second node.
The pixel circuit according to claim 1, further comprising: a first output control sub-circuit through which the element to be driven is connected to the fourth node;

the first output control sub-circuit is configured to control on/off between the fourth node and the element to be driven in response to control of a signal of the control signal line.
The pixel circuit of claim 7, wherein the first output control sub-circuit comprises: an eighth transistor;

and a control electrode of the eighth transistor is connected with the control signal line, a first electrode of the eighth transistor is connected with the fourth node, and a second electrode of the eighth transistor is connected with the element to be driven.
The pixel circuit according to claim 1, wherein a signal line that supplies the first data voltage to the first data writing sub-circuit and a signal line that supplies the ramp signal to the ramp writing sub-circuit are the same signal line.
A pixel circuit according to any one of claims 1-9, wherein the current control circuit comprises: the second reset sub-circuit, the control electrode of the driving transistor and the second threshold compensation sub-circuit are connected to a fifth node, the first electrode of the driving transistor, the second data write sub-circuit and the second output control sub-circuit are connected to a sixth node, and the second electrode of the driving transistor, the second threshold compensation sub-circuit and the second output control sub-circuit are connected to a seventh node;

the second reset sub-circuit configured to write a second initialization voltage to the fifth node in response to control of a signal of a second reset signal line;

the second data writing sub-circuit configured to write a second data voltage to the sixth node in response to control of a signal of a second gate line;

the second threshold compensation sub-circuit is configured to perform threshold compensation on the driving transistor in response to control of a signal of the second gate line;

the second output control sub-circuit is connected with the third node, and is configured to respond to the control of the signal of the control signal line, write a first working voltage into the sixth node, and control the conduction between the third node and the seventh node;

the driving transistor is configured to respond to the control of the voltage at the fifth node and output corresponding driving current;

and the first end of the second capacitor is connected with the first working voltage end, and the second end of the second capacitor is connected with the fifth node.
The pixel circuit of claim 10, wherein the second reset sub-circuit comprises: a ninth transistor, the second data writing sub-circuit including: a tenth transistor, the second threshold compensation sub-circuit comprising: an eleventh transistor, the second output control sub-circuit comprising: a twelfth transistor and a thirteenth transistor;

a control electrode of the ninth transistor is connected to the second reset signal line, a first electrode of the ninth transistor is connected to a second initialization voltage terminal, and a second electrode of the ninth transistor is connected to the fifth node;

a control electrode of the tenth transistor is connected to the second gate line, a first electrode of the tenth transistor is connected to the second data line, and a second electrode of the tenth transistor is connected to the sixth node;

a control electrode of the eleventh transistor is connected to the second gate line, a first electrode of the eleventh transistor is connected to the fifth node, and a second electrode of the eleventh transistor is connected to the seventh node;

a control electrode of the twelfth transistor is connected with the control signal line, a first electrode of the twelfth transistor is connected with the first working voltage end, and a second electrode of the twelfth transistor is connected with the sixth node;

a control electrode of the thirteenth transistor is connected to the control signal line, a first electrode of the thirteenth transistor is connected to the seventh node, and a second electrode of the thirteenth transistor is connected to the third node.
The pixel circuit according to claim 11, wherein the current control circuit further comprises a third capacitance;

a first end of the third capacitor is connected to the second gate line, and a second end of the third capacitor is connected to the fifth node.
A pixel circuit according to any one of claims 1-9, wherein the current control circuit comprises: the second reset sub-circuit, the second threshold compensation sub-circuit and the second reset sub-circuit are connected to an eighth node, the second reset sub-circuit and the second data write sub-circuit are connected to a ninth node, and the second pole of the driving transistor, the second threshold compensation sub-circuit and the second output control sub-circuit are connected to a tenth node;

the second reset sub-circuit configured to write a second initialization voltage and a preset constant voltage to the eighth node and the ninth node, respectively, in response to control of a signal of the second reset signal line, and write the preset constant voltage to the ninth node in response to control of a signal of a control signal line;

the second data writing sub-circuit configured to write a second data voltage to the ninth node in response to control of a signal of the second gate line;

the second threshold compensation sub-circuit is configured to perform threshold compensation on the driving transistor in response to control of a signal of the second gate line;

the second output control sub-circuit is connected with the third node and is configured to respond to the control of the signal of the control signal line and control the conduction between the third node and the tenth node;

the driving transistor is configured to respond to the control of the voltage at the eighth node and output corresponding driving current;

a first end of the fourth capacitor is connected with the first working voltage end, and a second end of the fourth capacitor is connected with the eighth node;

and a first end of the fifth capacitor is connected with the ninth node, and a second end of the fifth capacitor is connected with the eighth node.
The pixel circuit of claim 13, wherein the second reset sub-circuit comprises: a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor, the second data write sub-circuit including: a seventeenth transistor, the second threshold compensation sub-circuit comprising: an eighteenth transistor, the second output control sub-circuit including: a nineteenth transistor;

a control electrode of the fourteenth transistor is connected to the second reset signal line, a first electrode of the fourteenth transistor is connected to a second initialization voltage terminal, and a second electrode of the fourteenth transistor is connected to the eighth node;

a control electrode of the fifteenth transistor is connected with the second reset signal line, a first electrode of the fifteenth transistor is connected with a constant voltage end, and a second electrode of the fifteenth transistor is connected with the ninth node;

a control electrode of the sixteenth transistor is connected with the control signal line, a first electrode of the sixteenth transistor is connected with a constant voltage end, and a second electrode of the sixteenth transistor is connected with the ninth node;

a control electrode of the seventeenth transistor is connected with the second gate line, a first electrode of the seventeenth transistor is connected with the second data line, and a second electrode of the seventeenth transistor is connected with the ninth node;

a control electrode of the eighteenth transistor is connected with the second gate line, a first electrode of the eighteenth transistor is connected with the eighth node, and a second electrode of the eighteenth transistor is connected with the tenth node;

a control electrode of the nineteenth transistor is connected to the control signal line, a first electrode of the nineteenth transistor is connected to the tenth node, and a second electrode of the nineteenth transistor is connected to the third node.
A pixel circuit according to any one of claims 1-14, wherein all transistors in the pixel circuit are N-type transistors;

alternatively, all the transistors in the pixel circuit are P-type transistors.
A display device, comprising: comprising a display substrate comprising a plurality of sub-pixels, at least one of said sub-pixels having disposed therein a pixel circuit according to any one of claims 1 to 15 and an element to be driven, said pixel circuit being configured to provide a drive signal to said element to be driven.
The display device according to claim 16, wherein the element to be driven comprises: LED or Micro-LED.
A driving method of a pixel circuit for driving the pixel circuit according to any one of claims 1 to 15, the driving method comprising:

loading a first reset signal to the first reset signal line, a reference voltage to a reference voltage terminal, and a first initialization voltage to a first initialization voltage terminal, so that the first reset sub-circuit controls writing of the reference voltage and the first initialization voltage to the first node and the second node, respectively, in response to the reset signal;

loading a first gate scan signal to the first gate line, loading a first data voltage to a first data line, so that the first data writing sub-circuit controls writing of the first data voltage to the first node in response to the first gate scan signal, and the first threshold compensation sub-circuit controls threshold compensation of a transistor in the switching sub-circuit in response to the first gate scan signal;

loading a control signal to the control signal line, loading a ramp signal to a ramp signal line, so that the ramp writing sub-circuit controls to write the ramp signal to the first node in response to the control signal, and the switching sub-circuit adjusts the voltage at the second node according to a voltage difference between the voltage of the ramp signal loaded at the first node and the first data voltage, and controls on/off between the third node and the fourth node in response to the voltage control at the second node.
The driving method of a pixel circuit according to claim 18, wherein the current control circuit comprises: the second reset sub-circuit, the second data write sub-circuit, the second threshold compensation sub-circuit, the second output control sub-circuit, the driving transistor and the second capacitor;

before the step of applying a control signal to the control signal line and a ramp signal to the ramp signal line, the method further includes:

loading a second reset signal to the second reset signal line, loading a second initialization voltage to a second initialization voltage terminal, so that the second reset sub-circuit loads the second initialization voltage to a fifth node in response to control of the second reset signal;

loading a second gate scan signal to the second gate line, loading a second data voltage to a second data line, so that the second data writing sub-circuit controls writing of the second data voltage to a sixth node in response to the second gate scan signal, and the second threshold compensation sub-circuit controls threshold compensation of the driving transistor in response to the second gate scan signal;

when a control signal is loaded to the control signal wire, the second output control sub-circuit responds to the control signal to control writing of a first working voltage to the sixth node and control conduction between the third node and the seventh node, and the driving transistor responds to control of a voltage at the fifth node to output a corresponding driving current.
The driving method of a pixel circuit according to claim 18, wherein the current control circuit comprises: the second reset sub-circuit, the second data write sub-circuit, the second threshold compensation sub-circuit, the second output control sub-circuit, the driving transistor, the fourth capacitor and the fifth capacitor;

before the step of applying a control signal to the control signal line and a ramp signal to the ramp signal line, the method further includes:

loading a second reset signal to the second reset signal line, a second initialization voltage to a second initialization voltage terminal, and a constant voltage to a constant voltage terminal, so that the second reset sub-circuit loads the second initialization voltage and the constant voltage to the eighth node and the ninth node, respectively, in response to control of the second reset signal;

loading a second gate scan signal to the second gate line, loading a second data voltage to a second data line, so that the second data writing sub-circuit controls writing of the second data voltage to a ninth node in response to the second gate scan signal, and the second threshold compensation sub-circuit controls threshold compensation of the driving transistor in response to the second gate scan signal;

when a control signal is loaded to the control signal line, the second reset sub-circuit controls to write the constant voltage to the ninth node in response to the control signal, the second output control sub-circuit controls to conduct between the third node and the tenth node in response to the control signal, and the driving transistor outputs a corresponding driving current in response to the control of the voltage at the eighth node.